1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_7.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_7_ppt.h"
39 #include "smu_v13_0_7_pptable.h"
40 #include "smu_v13_0_7_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70
71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028
72
73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
74
75 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
98 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
107 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
108 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
110 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
111 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
112 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
113 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
114 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
115 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
116 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
117 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
118 };
119
120 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
121 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
122 CLK_MAP(SCLK, PPCLK_GFXCLK),
123 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
124 CLK_MAP(FCLK, PPCLK_FCLK),
125 CLK_MAP(UCLK, PPCLK_UCLK),
126 CLK_MAP(MCLK, PPCLK_UCLK),
127 CLK_MAP(VCLK, PPCLK_VCLK_0),
128 CLK_MAP(VCLK1, PPCLK_VCLK_1),
129 CLK_MAP(DCLK, PPCLK_DCLK_0),
130 CLK_MAP(DCLK1, PPCLK_DCLK_1),
131 };
132
133 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
134 FEA_MAP(FW_DATA_READ),
135 FEA_MAP(DPM_GFXCLK),
136 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
137 FEA_MAP(DPM_UCLK),
138 FEA_MAP(DPM_FCLK),
139 FEA_MAP(DPM_SOCCLK),
140 FEA_MAP(DPM_MP0CLK),
141 FEA_MAP(DPM_LINK),
142 FEA_MAP(DPM_DCN),
143 FEA_MAP(VMEMP_SCALING),
144 FEA_MAP(VDDIO_MEM_SCALING),
145 FEA_MAP(DS_GFXCLK),
146 FEA_MAP(DS_SOCCLK),
147 FEA_MAP(DS_FCLK),
148 FEA_MAP(DS_LCLK),
149 FEA_MAP(DS_DCFCLK),
150 FEA_MAP(DS_UCLK),
151 FEA_MAP(GFX_ULV),
152 FEA_MAP(FW_DSTATE),
153 FEA_MAP(GFXOFF),
154 FEA_MAP(BACO),
155 FEA_MAP(MM_DPM),
156 FEA_MAP(SOC_MPCLK_DS),
157 FEA_MAP(BACO_MPCLK_DS),
158 FEA_MAP(THROTTLERS),
159 FEA_MAP(SMARTSHIFT),
160 FEA_MAP(GTHR),
161 FEA_MAP(ACDC),
162 FEA_MAP(VR0HOT),
163 FEA_MAP(FW_CTF),
164 FEA_MAP(FAN_CONTROL),
165 FEA_MAP(GFX_DCS),
166 FEA_MAP(GFX_READ_MARGIN),
167 FEA_MAP(LED_DISPLAY),
168 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
169 FEA_MAP(OUT_OF_BAND_MONITOR),
170 FEA_MAP(OPTIMIZED_VMIN),
171 FEA_MAP(GFX_IMU),
172 FEA_MAP(BOOT_TIME_CAL),
173 FEA_MAP(GFX_PCC_DFLL),
174 FEA_MAP(SOC_CG),
175 FEA_MAP(DF_CSTATE),
176 FEA_MAP(GFX_EDC),
177 FEA_MAP(BOOT_POWER_OPT),
178 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
179 FEA_MAP(DS_VCN),
180 FEA_MAP(BACO_CG),
181 FEA_MAP(MEM_TEMP_READ),
182 FEA_MAP(ATHUB_MMHUB_PG),
183 FEA_MAP(SOC_PCC),
184 };
185
186 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
187 TAB_MAP(PPTABLE),
188 TAB_MAP(WATERMARKS),
189 TAB_MAP(AVFS_PSM_DEBUG),
190 TAB_MAP(PMSTATUSLOG),
191 TAB_MAP(SMU_METRICS),
192 TAB_MAP(DRIVER_SMU_CONFIG),
193 TAB_MAP(ACTIVITY_MONITOR_COEFF),
194 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
195 };
196
197 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
198 PWR_MAP(AC),
199 PWR_MAP(DC),
200 };
201
202 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
211 };
212
213 static const uint8_t smu_v13_0_7_throttler_map[] = {
214 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
215 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
216 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
217 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
218 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
219 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
220 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
221 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
222 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
223 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
224 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
225 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
226 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
227 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
228 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
229 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
230 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
231 };
232
233 static int
smu_v13_0_7_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)234 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
235 uint32_t *feature_mask, uint32_t num)
236 {
237 struct amdgpu_device *adev = smu->adev;
238
239 if (num > 2)
240 return -EINVAL;
241
242 memset(feature_mask, 0, sizeof(uint32_t) * num);
243
244 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
245
246 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
247 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
248 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
249 }
250
251 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
252 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
253 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
254 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
255 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
256 }
257
258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
259
260 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
261 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
262
263 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
264 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
265
266 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
268 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
269 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
277 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
284
285 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
287
288 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
289 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
291
292 return 0;
293 }
294
smu_v13_0_7_check_powerplay_table(struct smu_context * smu)295 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
296 {
297 struct smu_table_context *table_context = &smu->smu_table;
298 struct smu_13_0_7_powerplay_table *powerplay_table =
299 table_context->power_play_table;
300 struct smu_baco_context *smu_baco = &smu->smu_baco;
301
302 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
303 smu->dc_controlled_by_gpio = true;
304
305 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO ||
306 powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
307 smu_baco->platform_support = true;
308
309 table_context->thermal_controller_type =
310 powerplay_table->thermal_controller_type;
311
312 /*
313 * Instead of having its own buffer space and get overdrive_table copied,
314 * smu->od_settings just points to the actual overdrive_table
315 */
316 smu->od_settings = &powerplay_table->overdrive_table;
317
318 return 0;
319 }
320
smu_v13_0_7_store_powerplay_table(struct smu_context * smu)321 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
322 {
323 struct smu_table_context *table_context = &smu->smu_table;
324 struct smu_13_0_7_powerplay_table *powerplay_table =
325 table_context->power_play_table;
326 struct amdgpu_device *adev = smu->adev;
327
328 if (adev->pdev->device == 0x51)
329 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
330
331 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
332 sizeof(PPTable_t));
333
334 return 0;
335 }
336
smu_v13_0_7_check_fw_status(struct smu_context * smu)337 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
338 {
339 struct amdgpu_device *adev = smu->adev;
340 uint32_t mp1_fw_flags;
341
342 mp1_fw_flags = RREG32_PCIE(MP1_Public |
343 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
344
345 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
346 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
347 return 0;
348
349 return -EIO;
350 }
351
352 #ifndef atom_smc_dpm_info_table_13_0_7
353 struct atom_smc_dpm_info_table_13_0_7
354 {
355 struct atom_common_table_header table_header;
356 BoardTable_t BoardTable;
357 };
358 #endif
359
smu_v13_0_7_append_powerplay_table(struct smu_context * smu)360 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
361 {
362 struct smu_table_context *table_context = &smu->smu_table;
363
364 PPTable_t *smc_pptable = table_context->driver_pptable;
365
366 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
367
368 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
369
370 int index, ret;
371
372 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
373 smc_dpm_info);
374
375 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
376 (uint8_t **)&smc_dpm_table);
377 if (ret)
378 return ret;
379
380 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
381
382 return 0;
383 }
384
smu_v13_0_7_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)385 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
386 void **table,
387 uint32_t *size)
388 {
389 struct smu_table_context *smu_table = &smu->smu_table;
390 void *combo_pptable = smu_table->combo_pptable;
391 int ret = 0;
392
393 ret = smu_cmn_get_combo_pptable(smu);
394 if (ret)
395 return ret;
396
397 *table = combo_pptable;
398 *size = sizeof(struct smu_13_0_7_powerplay_table);
399
400 return 0;
401 }
402
smu_v13_0_7_setup_pptable(struct smu_context * smu)403 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
404 {
405 struct smu_table_context *smu_table = &smu->smu_table;
406 struct amdgpu_device *adev = smu->adev;
407 int ret = 0;
408
409 /*
410 * With SCPM enabled, the pptable used will be signed. It cannot
411 * be used directly by driver. To get the raw pptable, we need to
412 * rely on the combo pptable(and its revelant SMU message).
413 */
414 ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
415 &smu_table->power_play_table,
416 &smu_table->power_play_table_size);
417 if (ret)
418 return ret;
419
420 ret = smu_v13_0_7_store_powerplay_table(smu);
421 if (ret)
422 return ret;
423
424 /*
425 * With SCPM enabled, the operation below will be handled
426 * by PSP. Driver involvment is unnecessary and useless.
427 */
428 if (!adev->scpm_enabled) {
429 ret = smu_v13_0_7_append_powerplay_table(smu);
430 if (ret)
431 return ret;
432 }
433
434 ret = smu_v13_0_7_check_powerplay_table(smu);
435 if (ret)
436 return ret;
437
438 return ret;
439 }
440
smu_v13_0_7_tables_init(struct smu_context * smu)441 static int smu_v13_0_7_tables_init(struct smu_context *smu)
442 {
443 struct smu_table_context *smu_table = &smu->smu_table;
444 struct smu_table *tables = smu_table->tables;
445
446 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
447 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
448
449 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
450 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
451 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
452 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
453 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
454 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
455 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
457 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
458 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
459 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
460 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
461 AMDGPU_GEM_DOMAIN_VRAM);
462 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
463 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
464
465 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
466 if (!smu_table->metrics_table)
467 goto err0_out;
468 smu_table->metrics_time = 0;
469
470 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
471 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
472 if (!smu_table->gpu_metrics_table)
473 goto err1_out;
474
475 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
476 if (!smu_table->watermarks_table)
477 goto err2_out;
478
479 return 0;
480
481 err2_out:
482 kfree(smu_table->gpu_metrics_table);
483 err1_out:
484 kfree(smu_table->metrics_table);
485 err0_out:
486 return -ENOMEM;
487 }
488
smu_v13_0_7_allocate_dpm_context(struct smu_context * smu)489 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
490 {
491 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
492
493 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
494 GFP_KERNEL);
495 if (!smu_dpm->dpm_context)
496 return -ENOMEM;
497
498 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
499
500 return 0;
501 }
502
smu_v13_0_7_init_smc_tables(struct smu_context * smu)503 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
504 {
505 int ret = 0;
506
507 ret = smu_v13_0_7_tables_init(smu);
508 if (ret)
509 return ret;
510
511 ret = smu_v13_0_7_allocate_dpm_context(smu);
512 if (ret)
513 return ret;
514
515 return smu_v13_0_init_smc_tables(smu);
516 }
517
smu_v13_0_7_set_default_dpm_table(struct smu_context * smu)518 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
519 {
520 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
521 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
522 SkuTable_t *skutable = &driver_ppt->SkuTable;
523 struct smu_13_0_dpm_table *dpm_table;
524 struct smu_13_0_pcie_table *pcie_table;
525 uint32_t link_level;
526 int ret = 0;
527
528 /* socclk dpm table setup */
529 dpm_table = &dpm_context->dpm_tables.soc_table;
530 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
531 ret = smu_v13_0_set_single_dpm_table(smu,
532 SMU_SOCCLK,
533 dpm_table);
534 if (ret)
535 return ret;
536 } else {
537 dpm_table->count = 1;
538 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
539 dpm_table->dpm_levels[0].enabled = true;
540 dpm_table->min = dpm_table->dpm_levels[0].value;
541 dpm_table->max = dpm_table->dpm_levels[0].value;
542 }
543
544 /* gfxclk dpm table setup */
545 dpm_table = &dpm_context->dpm_tables.gfx_table;
546 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
547 ret = smu_v13_0_set_single_dpm_table(smu,
548 SMU_GFXCLK,
549 dpm_table);
550 if (ret)
551 return ret;
552 } else {
553 dpm_table->count = 1;
554 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
555 dpm_table->dpm_levels[0].enabled = true;
556 dpm_table->min = dpm_table->dpm_levels[0].value;
557 dpm_table->max = dpm_table->dpm_levels[0].value;
558 }
559
560 /* uclk dpm table setup */
561 dpm_table = &dpm_context->dpm_tables.uclk_table;
562 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
563 ret = smu_v13_0_set_single_dpm_table(smu,
564 SMU_UCLK,
565 dpm_table);
566 if (ret)
567 return ret;
568 } else {
569 dpm_table->count = 1;
570 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
571 dpm_table->dpm_levels[0].enabled = true;
572 dpm_table->min = dpm_table->dpm_levels[0].value;
573 dpm_table->max = dpm_table->dpm_levels[0].value;
574 }
575
576 /* fclk dpm table setup */
577 dpm_table = &dpm_context->dpm_tables.fclk_table;
578 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
579 ret = smu_v13_0_set_single_dpm_table(smu,
580 SMU_FCLK,
581 dpm_table);
582 if (ret)
583 return ret;
584 } else {
585 dpm_table->count = 1;
586 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
587 dpm_table->dpm_levels[0].enabled = true;
588 dpm_table->min = dpm_table->dpm_levels[0].value;
589 dpm_table->max = dpm_table->dpm_levels[0].value;
590 }
591
592 /* vclk dpm table setup */
593 dpm_table = &dpm_context->dpm_tables.vclk_table;
594 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
595 ret = smu_v13_0_set_single_dpm_table(smu,
596 SMU_VCLK,
597 dpm_table);
598 if (ret)
599 return ret;
600 } else {
601 dpm_table->count = 1;
602 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
603 dpm_table->dpm_levels[0].enabled = true;
604 dpm_table->min = dpm_table->dpm_levels[0].value;
605 dpm_table->max = dpm_table->dpm_levels[0].value;
606 }
607
608 /* dclk dpm table setup */
609 dpm_table = &dpm_context->dpm_tables.dclk_table;
610 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
611 ret = smu_v13_0_set_single_dpm_table(smu,
612 SMU_DCLK,
613 dpm_table);
614 if (ret)
615 return ret;
616 } else {
617 dpm_table->count = 1;
618 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
619 dpm_table->dpm_levels[0].enabled = true;
620 dpm_table->min = dpm_table->dpm_levels[0].value;
621 dpm_table->max = dpm_table->dpm_levels[0].value;
622 }
623
624 /* lclk dpm table setup */
625 pcie_table = &dpm_context->dpm_tables.pcie_table;
626 pcie_table->num_of_link_levels = 0;
627 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
628 if (!skutable->PcieGenSpeed[link_level] &&
629 !skutable->PcieLaneCount[link_level] &&
630 !skutable->LclkFreq[link_level])
631 continue;
632
633 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
634 skutable->PcieGenSpeed[link_level];
635 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
636 skutable->PcieLaneCount[link_level];
637 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
638 skutable->LclkFreq[link_level];
639 pcie_table->num_of_link_levels++;
640 }
641
642 return 0;
643 }
644
smu_v13_0_7_is_dpm_running(struct smu_context * smu)645 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
646 {
647 int ret = 0;
648 uint64_t feature_enabled;
649
650 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
651 if (ret)
652 return false;
653
654 return !!(feature_enabled & SMC_DPM_FEATURE);
655 }
656
smu_v13_0_7_dump_pptable(struct smu_context * smu)657 static void smu_v13_0_7_dump_pptable(struct smu_context *smu)
658 {
659 struct smu_table_context *table_context = &smu->smu_table;
660 PPTable_t *pptable = table_context->driver_pptable;
661 SkuTable_t *skutable = &pptable->SkuTable;
662
663 dev_info(smu->adev->dev, "Dumped PPTable:\n");
664
665 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
666 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
667 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
668 }
669
smu_v13_0_7_get_throttler_status(SmuMetrics_t * metrics)670 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
671 {
672 uint32_t throttler_status = 0;
673 int i;
674
675 for (i = 0; i < THROTTLER_COUNT; i++)
676 throttler_status |=
677 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
678
679 return throttler_status;
680 }
681
682 #define SMU_13_0_7_BUSY_THRESHOLD 15
smu_v13_0_7_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)683 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
684 MetricsMember_t member,
685 uint32_t *value)
686 {
687 struct smu_table_context *smu_table= &smu->smu_table;
688 SmuMetrics_t *metrics =
689 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
690 int ret = 0;
691
692 ret = smu_cmn_get_metrics_table(smu,
693 NULL,
694 false);
695 if (ret)
696 return ret;
697
698 switch (member) {
699 case METRICS_CURR_GFXCLK:
700 *value = metrics->CurrClock[PPCLK_GFXCLK];
701 break;
702 case METRICS_CURR_SOCCLK:
703 *value = metrics->CurrClock[PPCLK_SOCCLK];
704 break;
705 case METRICS_CURR_UCLK:
706 *value = metrics->CurrClock[PPCLK_UCLK];
707 break;
708 case METRICS_CURR_VCLK:
709 *value = metrics->CurrClock[PPCLK_VCLK_0];
710 break;
711 case METRICS_CURR_VCLK1:
712 *value = metrics->CurrClock[PPCLK_VCLK_1];
713 break;
714 case METRICS_CURR_DCLK:
715 *value = metrics->CurrClock[PPCLK_DCLK_0];
716 break;
717 case METRICS_CURR_DCLK1:
718 *value = metrics->CurrClock[PPCLK_DCLK_1];
719 break;
720 case METRICS_CURR_FCLK:
721 *value = metrics->CurrClock[PPCLK_FCLK];
722 break;
723 case METRICS_AVERAGE_GFXCLK:
724 *value = metrics->AverageGfxclkFrequencyPreDs;
725 break;
726 case METRICS_AVERAGE_FCLK:
727 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
728 *value = metrics->AverageFclkFrequencyPostDs;
729 else
730 *value = metrics->AverageFclkFrequencyPreDs;
731 break;
732 case METRICS_AVERAGE_UCLK:
733 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
734 *value = metrics->AverageMemclkFrequencyPostDs;
735 else
736 *value = metrics->AverageMemclkFrequencyPreDs;
737 break;
738 case METRICS_AVERAGE_VCLK:
739 *value = metrics->AverageVclk0Frequency;
740 break;
741 case METRICS_AVERAGE_DCLK:
742 *value = metrics->AverageDclk0Frequency;
743 break;
744 case METRICS_AVERAGE_VCLK1:
745 *value = metrics->AverageVclk1Frequency;
746 break;
747 case METRICS_AVERAGE_DCLK1:
748 *value = metrics->AverageDclk1Frequency;
749 break;
750 case METRICS_AVERAGE_GFXACTIVITY:
751 *value = metrics->AverageGfxActivity;
752 break;
753 case METRICS_AVERAGE_MEMACTIVITY:
754 *value = metrics->AverageUclkActivity;
755 break;
756 case METRICS_AVERAGE_SOCKETPOWER:
757 *value = metrics->AverageSocketPower << 8;
758 break;
759 case METRICS_TEMPERATURE_EDGE:
760 *value = metrics->AvgTemperature[TEMP_EDGE] *
761 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
762 break;
763 case METRICS_TEMPERATURE_HOTSPOT:
764 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
765 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
766 break;
767 case METRICS_TEMPERATURE_MEM:
768 *value = metrics->AvgTemperature[TEMP_MEM] *
769 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
770 break;
771 case METRICS_TEMPERATURE_VRGFX:
772 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
773 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
774 break;
775 case METRICS_TEMPERATURE_VRSOC:
776 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
777 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
778 break;
779 case METRICS_THROTTLER_STATUS:
780 *value = smu_v13_0_7_get_throttler_status(metrics);
781 break;
782 case METRICS_CURR_FANSPEED:
783 *value = metrics->AvgFanRpm;
784 break;
785 case METRICS_CURR_FANPWM:
786 *value = metrics->AvgFanPwm;
787 break;
788 case METRICS_VOLTAGE_VDDGFX:
789 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
790 break;
791 case METRICS_PCIE_RATE:
792 *value = metrics->PcieRate;
793 break;
794 case METRICS_PCIE_WIDTH:
795 *value = metrics->PcieWidth;
796 break;
797 default:
798 *value = UINT_MAX;
799 break;
800 }
801
802 return ret;
803 }
804
smu_v13_0_7_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)805 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
806 enum amd_pp_sensors sensor,
807 void *data,
808 uint32_t *size)
809 {
810 struct smu_table_context *table_context = &smu->smu_table;
811 PPTable_t *smc_pptable = table_context->driver_pptable;
812 int ret = 0;
813
814 switch (sensor) {
815 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
816 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
817 *size = 4;
818 break;
819 case AMDGPU_PP_SENSOR_MEM_LOAD:
820 ret = smu_v13_0_7_get_smu_metrics_data(smu,
821 METRICS_AVERAGE_MEMACTIVITY,
822 (uint32_t *)data);
823 *size = 4;
824 break;
825 case AMDGPU_PP_SENSOR_GPU_LOAD:
826 ret = smu_v13_0_7_get_smu_metrics_data(smu,
827 METRICS_AVERAGE_GFXACTIVITY,
828 (uint32_t *)data);
829 *size = 4;
830 break;
831 case AMDGPU_PP_SENSOR_GPU_POWER:
832 ret = smu_v13_0_7_get_smu_metrics_data(smu,
833 METRICS_AVERAGE_SOCKETPOWER,
834 (uint32_t *)data);
835 *size = 4;
836 break;
837 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
838 ret = smu_v13_0_7_get_smu_metrics_data(smu,
839 METRICS_TEMPERATURE_HOTSPOT,
840 (uint32_t *)data);
841 *size = 4;
842 break;
843 case AMDGPU_PP_SENSOR_EDGE_TEMP:
844 ret = smu_v13_0_7_get_smu_metrics_data(smu,
845 METRICS_TEMPERATURE_EDGE,
846 (uint32_t *)data);
847 *size = 4;
848 break;
849 case AMDGPU_PP_SENSOR_MEM_TEMP:
850 ret = smu_v13_0_7_get_smu_metrics_data(smu,
851 METRICS_TEMPERATURE_MEM,
852 (uint32_t *)data);
853 *size = 4;
854 break;
855 case AMDGPU_PP_SENSOR_GFX_MCLK:
856 ret = smu_v13_0_7_get_smu_metrics_data(smu,
857 METRICS_AVERAGE_UCLK,
858 (uint32_t *)data);
859 *(uint32_t *)data *= 100;
860 *size = 4;
861 break;
862 case AMDGPU_PP_SENSOR_GFX_SCLK:
863 ret = smu_v13_0_7_get_smu_metrics_data(smu,
864 METRICS_AVERAGE_GFXCLK,
865 (uint32_t *)data);
866 *(uint32_t *)data *= 100;
867 *size = 4;
868 break;
869 case AMDGPU_PP_SENSOR_VDDGFX:
870 ret = smu_v13_0_7_get_smu_metrics_data(smu,
871 METRICS_VOLTAGE_VDDGFX,
872 (uint32_t *)data);
873 *size = 4;
874 break;
875 default:
876 ret = -EOPNOTSUPP;
877 break;
878 }
879
880 return ret;
881 }
882
smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)883 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
884 enum smu_clk_type clk_type,
885 uint32_t *value)
886 {
887 MetricsMember_t member_type;
888 int clk_id = 0;
889
890 clk_id = smu_cmn_to_asic_specific_index(smu,
891 CMN2ASIC_MAPPING_CLK,
892 clk_type);
893 if (clk_id < 0)
894 return -EINVAL;
895
896 switch (clk_id) {
897 case PPCLK_GFXCLK:
898 member_type = METRICS_AVERAGE_GFXCLK;
899 break;
900 case PPCLK_UCLK:
901 member_type = METRICS_CURR_UCLK;
902 break;
903 case PPCLK_FCLK:
904 member_type = METRICS_CURR_FCLK;
905 break;
906 case PPCLK_SOCCLK:
907 member_type = METRICS_CURR_SOCCLK;
908 break;
909 case PPCLK_VCLK_0:
910 member_type = METRICS_CURR_VCLK;
911 break;
912 case PPCLK_DCLK_0:
913 member_type = METRICS_CURR_DCLK;
914 break;
915 case PPCLK_VCLK_1:
916 member_type = METRICS_CURR_VCLK1;
917 break;
918 case PPCLK_DCLK_1:
919 member_type = METRICS_CURR_DCLK1;
920 break;
921 default:
922 return -EINVAL;
923 }
924
925 return smu_v13_0_7_get_smu_metrics_data(smu,
926 member_type,
927 value);
928 }
929
smu_v13_0_7_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)930 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
931 enum smu_clk_type clk_type,
932 char *buf)
933 {
934 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
935 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
936 struct smu_13_0_dpm_table *single_dpm_table;
937 struct smu_13_0_pcie_table *pcie_table;
938 uint32_t gen_speed, lane_width;
939 int i, curr_freq, size = 0;
940 int ret = 0;
941
942 smu_cmn_get_sysfs_buf(&buf, &size);
943
944 if (amdgpu_ras_intr_triggered()) {
945 size += sysfs_emit_at(buf, size, "unavailable\n");
946 return size;
947 }
948
949 switch (clk_type) {
950 case SMU_SCLK:
951 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
952 break;
953 case SMU_MCLK:
954 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
955 break;
956 case SMU_SOCCLK:
957 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
958 break;
959 case SMU_FCLK:
960 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
961 break;
962 case SMU_VCLK:
963 case SMU_VCLK1:
964 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
965 break;
966 case SMU_DCLK:
967 case SMU_DCLK1:
968 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
969 break;
970 default:
971 break;
972 }
973
974 switch (clk_type) {
975 case SMU_SCLK:
976 case SMU_MCLK:
977 case SMU_SOCCLK:
978 case SMU_FCLK:
979 case SMU_VCLK:
980 case SMU_VCLK1:
981 case SMU_DCLK:
982 case SMU_DCLK1:
983 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
984 if (ret) {
985 dev_err(smu->adev->dev, "Failed to get current clock freq!");
986 return ret;
987 }
988
989 if (single_dpm_table->is_fine_grained) {
990 /*
991 * For fine grained dpms, there are only two dpm levels:
992 * - level 0 -> min clock freq
993 * - level 1 -> max clock freq
994 * And the current clock frequency can be any value between them.
995 * So, if the current clock frequency is not at level 0 or level 1,
996 * we will fake it as three dpm levels:
997 * - level 0 -> min clock freq
998 * - level 1 -> current actual clock freq
999 * - level 2 -> max clock freq
1000 */
1001 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1002 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1003 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1004 single_dpm_table->dpm_levels[0].value);
1005 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1006 curr_freq);
1007 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1008 single_dpm_table->dpm_levels[1].value);
1009 } else {
1010 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1011 single_dpm_table->dpm_levels[0].value,
1012 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1013 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1014 single_dpm_table->dpm_levels[1].value,
1015 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1016 }
1017 } else {
1018 for (i = 0; i < single_dpm_table->count; i++)
1019 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1020 i, single_dpm_table->dpm_levels[i].value,
1021 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1022 }
1023 break;
1024 case SMU_PCIE:
1025 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1026 METRICS_PCIE_RATE,
1027 &gen_speed);
1028 if (ret)
1029 return ret;
1030
1031 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1032 METRICS_PCIE_WIDTH,
1033 &lane_width);
1034 if (ret)
1035 return ret;
1036
1037 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1038 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1039 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1040 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1041 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1042 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1043 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1044 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1045 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1046 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1047 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1048 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1049 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1050 pcie_table->clk_freq[i],
1051 (gen_speed == pcie_table->pcie_gen[i]) &&
1052 (lane_width == pcie_table->pcie_lane[i]) ?
1053 "*" : "");
1054 break;
1055
1056 default:
1057 break;
1058 }
1059
1060 return size;
1061 }
1062
smu_v13_0_7_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1063 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1064 enum smu_clk_type clk_type,
1065 uint32_t mask)
1066 {
1067 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1068 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1069 struct smu_13_0_dpm_table *single_dpm_table;
1070 uint32_t soft_min_level, soft_max_level;
1071 uint32_t min_freq, max_freq;
1072 int ret = 0;
1073
1074 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1075 soft_max_level = mask ? (fls(mask) - 1) : 0;
1076
1077 switch (clk_type) {
1078 case SMU_GFXCLK:
1079 case SMU_SCLK:
1080 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1081 break;
1082 case SMU_MCLK:
1083 case SMU_UCLK:
1084 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1085 break;
1086 case SMU_SOCCLK:
1087 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1088 break;
1089 case SMU_FCLK:
1090 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1091 break;
1092 case SMU_VCLK:
1093 case SMU_VCLK1:
1094 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1095 break;
1096 case SMU_DCLK:
1097 case SMU_DCLK1:
1098 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1099 break;
1100 default:
1101 break;
1102 }
1103
1104 switch (clk_type) {
1105 case SMU_GFXCLK:
1106 case SMU_SCLK:
1107 case SMU_MCLK:
1108 case SMU_UCLK:
1109 case SMU_SOCCLK:
1110 case SMU_FCLK:
1111 case SMU_VCLK:
1112 case SMU_VCLK1:
1113 case SMU_DCLK:
1114 case SMU_DCLK1:
1115 if (single_dpm_table->is_fine_grained) {
1116 /* There is only 2 levels for fine grained DPM */
1117 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1118 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1119 } else {
1120 if ((soft_max_level >= single_dpm_table->count) ||
1121 (soft_min_level >= single_dpm_table->count))
1122 return -EINVAL;
1123 }
1124
1125 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1126 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1127
1128 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1129 clk_type,
1130 min_freq,
1131 max_freq);
1132 break;
1133 case SMU_DCEFCLK:
1134 case SMU_PCIE:
1135 default:
1136 break;
1137 }
1138
1139 return ret;
1140 }
1141
smu_v13_0_7_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)1142 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
1143 uint32_t pcie_gen_cap,
1144 uint32_t pcie_width_cap)
1145 {
1146 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1147 struct smu_13_0_pcie_table *pcie_table =
1148 &dpm_context->dpm_tables.pcie_table;
1149 uint32_t smu_pcie_arg;
1150 int ret, i;
1151
1152 for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1153 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1154 pcie_table->pcie_gen[i] = pcie_gen_cap;
1155 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1156 pcie_table->pcie_lane[i] = pcie_width_cap;
1157
1158 smu_pcie_arg = i << 16;
1159 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1160 smu_pcie_arg |= pcie_table->pcie_lane[i];
1161
1162 ret = smu_cmn_send_smc_msg_with_param(smu,
1163 SMU_MSG_OverridePcieParameters,
1164 smu_pcie_arg,
1165 NULL);
1166 if (ret)
1167 return ret;
1168 }
1169
1170 return 0;
1171 }
1172
1173 static const struct smu_temperature_range smu13_thermal_policy[] =
1174 {
1175 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1176 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1177 };
1178
smu_v13_0_7_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1179 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
1180 struct smu_temperature_range *range)
1181 {
1182 struct smu_table_context *table_context = &smu->smu_table;
1183 struct smu_13_0_7_powerplay_table *powerplay_table =
1184 table_context->power_play_table;
1185 PPTable_t *pptable = smu->smu_table.driver_pptable;
1186
1187 if (!range)
1188 return -EINVAL;
1189
1190 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1191
1192 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
1193 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1194 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1195 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1196 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1197 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1198 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1199 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1200 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
1201 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1202 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1203 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1204 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1205
1206 return 0;
1207 }
1208
1209 #define MAX(a, b) ((a) > (b) ? (a) : (b))
smu_v13_0_7_get_gpu_metrics(struct smu_context * smu,void ** table)1210 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
1211 void **table)
1212 {
1213 struct smu_table_context *smu_table = &smu->smu_table;
1214 struct gpu_metrics_v1_3 *gpu_metrics =
1215 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1216 SmuMetricsExternal_t metrics_ext;
1217 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1218 int ret = 0;
1219
1220 ret = smu_cmn_get_metrics_table(smu,
1221 &metrics_ext,
1222 true);
1223 if (ret)
1224 return ret;
1225
1226 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1227
1228 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1229 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1230 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1231 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1232 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1233 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0],
1234 metrics->AvgTemperature[TEMP_VR_MEM1]);
1235
1236 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1237 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1238 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage,
1239 metrics->Vcn1ActivityPercentage);
1240
1241 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1242 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1243
1244 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1245 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1246 else
1247 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1248
1249 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1250 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1251 else
1252 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1253
1254 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1255 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1256 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1257 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1258
1259 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
1260 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1261 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1262 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
1263 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
1264
1265 gpu_metrics->throttle_status =
1266 smu_v13_0_7_get_throttler_status(metrics);
1267 gpu_metrics->indep_throttle_status =
1268 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1269 smu_v13_0_7_throttler_map);
1270
1271 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1272
1273 gpu_metrics->pcie_link_width = metrics->PcieWidth;
1274 gpu_metrics->pcie_link_speed = metrics->PcieRate;
1275
1276 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1277
1278 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
1279 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
1280 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
1281
1282 *table = (void *)gpu_metrics;
1283
1284 return sizeof(struct gpu_metrics_v1_3);
1285 }
1286
smu_v13_0_7_populate_umd_state_clk(struct smu_context * smu)1287 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
1288 {
1289 struct smu_13_0_dpm_context *dpm_context =
1290 smu->smu_dpm.dpm_context;
1291 struct smu_13_0_dpm_table *gfx_table =
1292 &dpm_context->dpm_tables.gfx_table;
1293 struct smu_13_0_dpm_table *mem_table =
1294 &dpm_context->dpm_tables.uclk_table;
1295 struct smu_13_0_dpm_table *soc_table =
1296 &dpm_context->dpm_tables.soc_table;
1297 struct smu_13_0_dpm_table *vclk_table =
1298 &dpm_context->dpm_tables.vclk_table;
1299 struct smu_13_0_dpm_table *dclk_table =
1300 &dpm_context->dpm_tables.dclk_table;
1301 struct smu_13_0_dpm_table *fclk_table =
1302 &dpm_context->dpm_tables.fclk_table;
1303 struct smu_umd_pstate_table *pstate_table =
1304 &smu->pstate_table;
1305
1306 pstate_table->gfxclk_pstate.min = gfx_table->min;
1307 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1308
1309 pstate_table->uclk_pstate.min = mem_table->min;
1310 pstate_table->uclk_pstate.peak = mem_table->max;
1311
1312 pstate_table->socclk_pstate.min = soc_table->min;
1313 pstate_table->socclk_pstate.peak = soc_table->max;
1314
1315 pstate_table->vclk_pstate.min = vclk_table->min;
1316 pstate_table->vclk_pstate.peak = vclk_table->max;
1317
1318 pstate_table->dclk_pstate.min = dclk_table->min;
1319 pstate_table->dclk_pstate.peak = dclk_table->max;
1320
1321 pstate_table->fclk_pstate.min = fclk_table->min;
1322 pstate_table->fclk_pstate.peak = fclk_table->max;
1323
1324 /*
1325 * For now, just use the mininum clock frequency.
1326 * TODO: update them when the real pstate settings available
1327 */
1328 pstate_table->gfxclk_pstate.standard = gfx_table->min;
1329 pstate_table->uclk_pstate.standard = mem_table->min;
1330 pstate_table->socclk_pstate.standard = soc_table->min;
1331 pstate_table->vclk_pstate.standard = vclk_table->min;
1332 pstate_table->dclk_pstate.standard = dclk_table->min;
1333 pstate_table->fclk_pstate.standard = fclk_table->min;
1334
1335 return 0;
1336 }
1337
smu_v13_0_7_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1338 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
1339 uint32_t *speed)
1340 {
1341 if (!speed)
1342 return -EINVAL;
1343
1344 return smu_v13_0_7_get_smu_metrics_data(smu,
1345 METRICS_CURR_FANPWM,
1346 speed);
1347 }
1348
smu_v13_0_7_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1349 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
1350 uint32_t *speed)
1351 {
1352 if (!speed)
1353 return -EINVAL;
1354
1355 return smu_v13_0_7_get_smu_metrics_data(smu,
1356 METRICS_CURR_FANSPEED,
1357 speed);
1358 }
1359
smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context * smu)1360 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
1361 {
1362 struct smu_table_context *table_context = &smu->smu_table;
1363 PPTable_t *pptable = table_context->driver_pptable;
1364 SkuTable_t *skutable = &pptable->SkuTable;
1365
1366 /*
1367 * Skip the MGpuFanBoost setting for those ASICs
1368 * which do not support it
1369 */
1370 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
1371 return 0;
1372
1373 return smu_cmn_send_smc_msg_with_param(smu,
1374 SMU_MSG_SetMGpuFanBoostLimitRpm,
1375 0,
1376 NULL);
1377 }
1378
smu_v13_0_7_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)1379 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
1380 uint32_t *current_power_limit,
1381 uint32_t *default_power_limit,
1382 uint32_t *max_power_limit)
1383 {
1384 struct smu_table_context *table_context = &smu->smu_table;
1385 struct smu_13_0_7_powerplay_table *powerplay_table =
1386 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
1387 PPTable_t *pptable = table_context->driver_pptable;
1388 SkuTable_t *skutable = &pptable->SkuTable;
1389 uint32_t power_limit, od_percent;
1390
1391 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
1392 power_limit = smu->adev->pm.ac_power ?
1393 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1394 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1395
1396 if (current_power_limit)
1397 *current_power_limit = power_limit;
1398 if (default_power_limit)
1399 *default_power_limit = power_limit;
1400
1401 if (max_power_limit) {
1402 if (smu->od_enabled) {
1403 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
1404
1405 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1406
1407 power_limit *= (100 + od_percent);
1408 power_limit /= 100;
1409 }
1410 *max_power_limit = power_limit;
1411 }
1412
1413 return 0;
1414 }
1415
smu_v13_0_7_get_power_profile_mode(struct smu_context * smu,char * buf)1416 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
1417 {
1418 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT];
1419 uint32_t i, j, size = 0;
1420 int16_t workload_type = 0;
1421 int result = 0;
1422
1423 if (!buf)
1424 return -EINVAL;
1425
1426 size += sysfs_emit_at(buf, size, " ");
1427 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
1428 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i],
1429 (i == smu->power_profile_mode) ? "* " : " ");
1430
1431 size += sysfs_emit_at(buf, size, "\n");
1432
1433 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
1434 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1435 workload_type = smu_cmn_to_asic_specific_index(smu,
1436 CMN2ASIC_MAPPING_WORKLOAD,
1437 i);
1438 if (workload_type < 0)
1439 return -EINVAL;
1440
1441 result = smu_cmn_update_table(smu,
1442 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1443 (void *)(&activity_monitor_external[i]), false);
1444 if (result) {
1445 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1446 return result;
1447 }
1448 }
1449
1450 #define PRINT_DPM_MONITOR(field) \
1451 do { \
1452 size += sysfs_emit_at(buf, size, "%-30s", #field); \
1453 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \
1454 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \
1455 size += sysfs_emit_at(buf, size, "\n"); \
1456 } while (0)
1457
1458 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
1459 PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
1460 PRINT_DPM_MONITOR(Gfx_FPS);
1461 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
1462 PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
1463 PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
1464 PRINT_DPM_MONITOR(Gfx_BoosterFreq);
1465 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
1466 PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
1467 PRINT_DPM_MONITOR(Fclk_FPS);
1468 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
1469 PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
1470 PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
1471 PRINT_DPM_MONITOR(Fclk_BoosterFreq);
1472 #undef PRINT_DPM_MONITOR
1473
1474 return size;
1475 }
1476
smu_v13_0_7_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1477 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1478 {
1479
1480 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1481 DpmActivityMonitorCoeffInt_t *activity_monitor =
1482 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1483 int workload_type, ret = 0;
1484
1485 smu->power_profile_mode = input[size];
1486
1487 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) {
1488 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1489 return -EINVAL;
1490 }
1491
1492 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1493
1494 ret = smu_cmn_update_table(smu,
1495 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1496 (void *)(&activity_monitor_external), false);
1497 if (ret) {
1498 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1499 return ret;
1500 }
1501
1502 switch (input[0]) {
1503 case 0: /* Gfxclk */
1504 activity_monitor->Gfx_ActiveHystLimit = input[1];
1505 activity_monitor->Gfx_IdleHystLimit = input[2];
1506 activity_monitor->Gfx_FPS = input[3];
1507 activity_monitor->Gfx_MinActiveFreqType = input[4];
1508 activity_monitor->Gfx_BoosterFreqType = input[5];
1509 activity_monitor->Gfx_MinActiveFreq = input[6];
1510 activity_monitor->Gfx_BoosterFreq = input[7];
1511 break;
1512 case 1: /* Fclk */
1513 activity_monitor->Fclk_ActiveHystLimit = input[1];
1514 activity_monitor->Fclk_IdleHystLimit = input[2];
1515 activity_monitor->Fclk_FPS = input[3];
1516 activity_monitor->Fclk_MinActiveFreqType = input[4];
1517 activity_monitor->Fclk_BoosterFreqType = input[5];
1518 activity_monitor->Fclk_MinActiveFreq = input[6];
1519 activity_monitor->Fclk_BoosterFreq = input[7];
1520 break;
1521 }
1522
1523 ret = smu_cmn_update_table(smu,
1524 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1525 (void *)(&activity_monitor_external), true);
1526 if (ret) {
1527 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1528 return ret;
1529 }
1530 }
1531
1532 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1533 workload_type = smu_cmn_to_asic_specific_index(smu,
1534 CMN2ASIC_MAPPING_WORKLOAD,
1535 smu->power_profile_mode);
1536 if (workload_type < 0)
1537 return -EINVAL;
1538 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1539 1 << workload_type, NULL);
1540
1541 return ret;
1542 }
1543
1544 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
1545 .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
1546 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
1547 .is_dpm_running = smu_v13_0_7_is_dpm_running,
1548 .dump_pptable = smu_v13_0_7_dump_pptable,
1549 .init_microcode = smu_v13_0_init_microcode,
1550 .load_microcode = smu_v13_0_load_microcode,
1551 .fini_microcode = smu_v13_0_fini_microcode,
1552 .init_smc_tables = smu_v13_0_7_init_smc_tables,
1553 .fini_smc_tables = smu_v13_0_fini_smc_tables,
1554 .init_power = smu_v13_0_init_power,
1555 .check_fw_status = smu_v13_0_7_check_fw_status,
1556 .setup_pptable = smu_v13_0_7_setup_pptable,
1557 .check_fw_version = smu_v13_0_check_fw_version,
1558 .write_pptable = smu_cmn_write_pptable,
1559 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1560 .system_features_control = smu_v13_0_system_features_control,
1561 .set_allowed_mask = smu_v13_0_set_allowed_mask,
1562 .get_enabled_mask = smu_cmn_get_enabled_mask,
1563 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1564 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1565 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
1566 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
1567 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1568 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1569 .read_sensor = smu_v13_0_7_read_sensor,
1570 .feature_is_enabled = smu_cmn_feature_is_enabled,
1571 .print_clk_levels = smu_v13_0_7_print_clk_levels,
1572 .force_clk_levels = smu_v13_0_7_force_clk_levels,
1573 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
1574 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
1575 .register_irq_handler = smu_v13_0_register_irq_handler,
1576 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1577 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1578 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1579 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
1580 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
1581 .set_performance_level = smu_v13_0_set_performance_level,
1582 .gfx_off_control = smu_v13_0_gfx_off_control,
1583 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
1584 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
1585 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
1586 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
1587 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
1588 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
1589 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
1590 .get_power_limit = smu_v13_0_7_get_power_limit,
1591 .set_power_limit = smu_v13_0_set_power_limit,
1592 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
1593 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
1594 .set_tool_table_location = smu_v13_0_set_tool_table_location,
1595 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1596 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1597 };
1598
smu_v13_0_7_set_ppt_funcs(struct smu_context * smu)1599 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
1600 {
1601 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
1602 smu->message_map = smu_v13_0_7_message_map;
1603 smu->clock_map = smu_v13_0_7_clk_map;
1604 smu->feature_map = smu_v13_0_7_feature_mask_map;
1605 smu->table_map = smu_v13_0_7_table_map;
1606 smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
1607 smu->workload_map = smu_v13_0_7_workload_map;
1608 }
1609