1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28
29 #include "core_types.h"
30 #include "link_encoder.h"
31 #include "dcn31_dio_link_encoder.h"
32 #include "stream_encoder.h"
33 #include "i2caux_interface.h"
34 #include "dc_bios_types.h"
35
36 #include "gpio_service_interface.h"
37
38 #include "link_enc_cfg.h"
39 #include "dc_dmub_srv.h"
40 #include "dal_asic_id.h"
41
42 #define CTX \
43 enc10->base.ctx
44 #define DC_LOGGER \
45 enc10->base.ctx->logger
46
47 #define REG(reg)\
48 (enc10->link_regs->reg)
49
50 #undef FN
51 #define FN(reg_name, field_name) \
52 enc10->link_shift->field_name, enc10->link_mask->field_name
53
54 #define IND_REG(index) \
55 (enc10->link_regs->index)
56
57 #define AUX_REG(reg)\
58 (enc10->aux_regs->reg)
59
60 #define AUX_REG_READ(reg_name) \
61 dm_read_reg(CTX, AUX_REG(reg_name))
62
63 #define AUX_REG_WRITE(reg_name, val) \
64 dm_write_reg(CTX, AUX_REG(reg_name), val)
65
66 #ifndef MIN
67 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
68 #endif
69
phy_id_from_transmitter(enum transmitter t)70 static uint8_t phy_id_from_transmitter(enum transmitter t)
71 {
72 uint8_t phy_id;
73
74 switch (t) {
75 case TRANSMITTER_UNIPHY_A:
76 phy_id = 0;
77 break;
78 case TRANSMITTER_UNIPHY_B:
79 phy_id = 1;
80 break;
81 case TRANSMITTER_UNIPHY_C:
82 phy_id = 2;
83 break;
84 case TRANSMITTER_UNIPHY_D:
85 phy_id = 3;
86 break;
87 case TRANSMITTER_UNIPHY_E:
88 phy_id = 4;
89 break;
90 case TRANSMITTER_UNIPHY_F:
91 phy_id = 5;
92 break;
93 case TRANSMITTER_UNIPHY_G:
94 phy_id = 6;
95 break;
96 default:
97 phy_id = 0;
98 break;
99 }
100 return phy_id;
101 }
102
has_query_dp_alt(struct link_encoder * enc)103 static bool has_query_dp_alt(struct link_encoder *enc)
104 {
105 struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;
106
107 /* Supports development firmware and firmware >= 4.0.11 */
108 return dc_dmub_srv &&
109 !(dc_dmub_srv->dmub->fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
110 dc_dmub_srv->dmub->fw_version <= DMUB_FW_VERSION(4, 0, 10));
111 }
112
query_dp_alt_from_dmub(struct link_encoder * enc,union dmub_rb_cmd * cmd)113 static bool query_dp_alt_from_dmub(struct link_encoder *enc,
114 union dmub_rb_cmd *cmd)
115 {
116 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
117 struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;
118
119 memset(cmd, 0, sizeof(*cmd));
120 cmd->query_dp_alt.header.type = DMUB_CMD__VBIOS;
121 cmd->query_dp_alt.header.sub_type =
122 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT;
123 cmd->query_dp_alt.header.payload_bytes = sizeof(cmd->query_dp_alt.data);
124 cmd->query_dp_alt.data.phy_id = phy_id_from_transmitter(enc10->base.transmitter);
125
126 if (!dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, cmd))
127 return false;
128
129 return true;
130 }
131
dcn31_link_encoder_set_dio_phy_mux(struct link_encoder * enc,enum encoder_type_select sel,uint32_t hpo_inst)132 void dcn31_link_encoder_set_dio_phy_mux(
133 struct link_encoder *enc,
134 enum encoder_type_select sel,
135 uint32_t hpo_inst)
136 {
137 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
138
139 switch (enc->transmitter) {
140 case TRANSMITTER_UNIPHY_A:
141 if (sel == ENCODER_TYPE_HDMI_FRL)
142 REG_UPDATE(DIO_LINKA_CNTL,
143 HPO_HDMI_ENC_SEL, hpo_inst);
144 else if (sel == ENCODER_TYPE_DP_128B132B)
145 REG_UPDATE(DIO_LINKA_CNTL,
146 HPO_DP_ENC_SEL, hpo_inst);
147 REG_UPDATE(DIO_LINKA_CNTL,
148 ENC_TYPE_SEL, sel);
149 break;
150 case TRANSMITTER_UNIPHY_B:
151 if (sel == ENCODER_TYPE_HDMI_FRL)
152 REG_UPDATE(DIO_LINKB_CNTL,
153 HPO_HDMI_ENC_SEL, hpo_inst);
154 else if (sel == ENCODER_TYPE_DP_128B132B)
155 REG_UPDATE(DIO_LINKB_CNTL,
156 HPO_DP_ENC_SEL, hpo_inst);
157 REG_UPDATE(DIO_LINKB_CNTL,
158 ENC_TYPE_SEL, sel);
159 break;
160 case TRANSMITTER_UNIPHY_C:
161 if (sel == ENCODER_TYPE_HDMI_FRL)
162 REG_UPDATE(DIO_LINKC_CNTL,
163 HPO_HDMI_ENC_SEL, hpo_inst);
164 else if (sel == ENCODER_TYPE_DP_128B132B)
165 REG_UPDATE(DIO_LINKC_CNTL,
166 HPO_DP_ENC_SEL, hpo_inst);
167 REG_UPDATE(DIO_LINKC_CNTL,
168 ENC_TYPE_SEL, sel);
169 break;
170 case TRANSMITTER_UNIPHY_D:
171 if (sel == ENCODER_TYPE_HDMI_FRL)
172 REG_UPDATE(DIO_LINKD_CNTL,
173 HPO_HDMI_ENC_SEL, hpo_inst);
174 else if (sel == ENCODER_TYPE_DP_128B132B)
175 REG_UPDATE(DIO_LINKD_CNTL,
176 HPO_DP_ENC_SEL, hpo_inst);
177 REG_UPDATE(DIO_LINKD_CNTL,
178 ENC_TYPE_SEL, sel);
179 break;
180 case TRANSMITTER_UNIPHY_E:
181 if (sel == ENCODER_TYPE_HDMI_FRL)
182 REG_UPDATE(DIO_LINKE_CNTL,
183 HPO_HDMI_ENC_SEL, hpo_inst);
184 else if (sel == ENCODER_TYPE_DP_128B132B)
185 REG_UPDATE(DIO_LINKE_CNTL,
186 HPO_DP_ENC_SEL, hpo_inst);
187 REG_UPDATE(DIO_LINKE_CNTL,
188 ENC_TYPE_SEL, sel);
189 break;
190 case TRANSMITTER_UNIPHY_F:
191 if (sel == ENCODER_TYPE_HDMI_FRL)
192 REG_UPDATE(DIO_LINKF_CNTL,
193 HPO_HDMI_ENC_SEL, hpo_inst);
194 else if (sel == ENCODER_TYPE_DP_128B132B)
195 REG_UPDATE(DIO_LINKF_CNTL,
196 HPO_DP_ENC_SEL, hpo_inst);
197 REG_UPDATE(DIO_LINKF_CNTL,
198 ENC_TYPE_SEL, sel);
199 break;
200 default:
201 /* Do nothing */
202 break;
203 }
204 }
205
enc31_hw_init(struct link_encoder * enc)206 static void enc31_hw_init(struct link_encoder *enc)
207 {
208 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
209
210 /*
211 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
212 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
213 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
214 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
215 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
216 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
217 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
218 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
219 */
220
221 /*
222 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
223 AUX_RX_START_WINDOW = 1 [6:4]
224 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
225 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
226 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
227 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
228 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
229 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
230 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
231 AUX_RX_DETECTION_THRESHOLD [30:28] = 1
232 */
233 // dmub will read AUX_DPHY_RX_CONTROL0/AUX_DPHY_TX_CONTROL from vbios table in dp_aux_init
234
235 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
236 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
237 // 27MHz -> 0xd
238 // 100MHz -> 0x32
239 // 48MHz -> 0x18
240
241 // Set TMDS_CTL0 to 1. This is a legacy setting.
242 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
243
244 dcn10_aux_initialize(enc10);
245 }
246
247 static const struct link_encoder_funcs dcn31_link_enc_funcs = {
248 .read_state = link_enc2_read_state,
249 .validate_output_with_stream =
250 dcn30_link_encoder_validate_output_with_stream,
251 .hw_init = enc31_hw_init,
252 .setup = dcn10_link_encoder_setup,
253 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
254 .enable_dp_output = dcn31_link_encoder_enable_dp_output,
255 .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
256 .disable_output = dcn31_link_encoder_disable_output,
257 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
258 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
259 .update_mst_stream_allocation_table =
260 dcn10_link_encoder_update_mst_stream_allocation_table,
261 .psr_program_dp_dphy_fast_training =
262 dcn10_psr_program_dp_dphy_fast_training,
263 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
264 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
265 .enable_hpd = dcn10_link_encoder_enable_hpd,
266 .disable_hpd = dcn10_link_encoder_disable_hpd,
267 .is_dig_enabled = dcn10_is_dig_enabled,
268 .destroy = dcn10_link_encoder_destroy,
269 .fec_set_enable = enc2_fec_set_enable,
270 .fec_set_ready = enc2_fec_set_ready,
271 .fec_is_active = enc2_fec_is_active,
272 .get_dig_frontend = dcn10_get_dig_frontend,
273 .get_dig_mode = dcn10_get_dig_mode,
274 .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
275 .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
276 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
277 };
278
dcn31_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)279 void dcn31_link_encoder_construct(
280 struct dcn20_link_encoder *enc20,
281 const struct encoder_init_data *init_data,
282 const struct encoder_feature_support *enc_features,
283 const struct dcn10_link_enc_registers *link_regs,
284 const struct dcn10_link_enc_aux_registers *aux_regs,
285 const struct dcn10_link_enc_hpd_registers *hpd_regs,
286 const struct dcn10_link_enc_shift *link_shift,
287 const struct dcn10_link_enc_mask *link_mask)
288 {
289 struct bp_encoder_cap_info bp_cap_info = {0};
290 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
291 enum bp_result result = BP_RESULT_OK;
292 struct dcn10_link_encoder *enc10 = &enc20->enc10;
293
294 enc10->base.funcs = &dcn31_link_enc_funcs;
295 enc10->base.ctx = init_data->ctx;
296 enc10->base.id = init_data->encoder;
297
298 enc10->base.hpd_source = init_data->hpd_source;
299 enc10->base.connector = init_data->connector;
300
301 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
302
303 enc10->base.features = *enc_features;
304
305 enc10->base.transmitter = init_data->transmitter;
306
307 /* set the flag to indicate whether driver poll the I2C data pin
308 * while doing the DP sink detect
309 */
310
311 /* if (dal_adapter_service_is_feature_supported(as,
312 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
313 enc10->base.features.flags.bits.
314 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
315
316 enc10->base.output_signals =
317 SIGNAL_TYPE_DVI_SINGLE_LINK |
318 SIGNAL_TYPE_DVI_DUAL_LINK |
319 SIGNAL_TYPE_LVDS |
320 SIGNAL_TYPE_DISPLAY_PORT |
321 SIGNAL_TYPE_DISPLAY_PORT_MST |
322 SIGNAL_TYPE_EDP |
323 SIGNAL_TYPE_HDMI_TYPE_A;
324
325 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
326 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
327 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
328 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
329 * Prefer DIG assignment is decided by board design.
330 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
331 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
332 * By this, adding DIGG should not hurt DCE 8.0.
333 * This will let DCE 8.1 share DCE 8.0 as much as possible
334 */
335
336 enc10->link_regs = link_regs;
337 enc10->aux_regs = aux_regs;
338 enc10->hpd_regs = hpd_regs;
339 enc10->link_shift = link_shift;
340 enc10->link_mask = link_mask;
341
342 switch (enc10->base.transmitter) {
343 case TRANSMITTER_UNIPHY_A:
344 enc10->base.preferred_engine = ENGINE_ID_DIGA;
345 break;
346 case TRANSMITTER_UNIPHY_B:
347 enc10->base.preferred_engine = ENGINE_ID_DIGB;
348 break;
349 case TRANSMITTER_UNIPHY_C:
350 enc10->base.preferred_engine = ENGINE_ID_DIGC;
351 break;
352 case TRANSMITTER_UNIPHY_D:
353 enc10->base.preferred_engine = ENGINE_ID_DIGD;
354 break;
355 case TRANSMITTER_UNIPHY_E:
356 enc10->base.preferred_engine = ENGINE_ID_DIGE;
357 break;
358 case TRANSMITTER_UNIPHY_F:
359 enc10->base.preferred_engine = ENGINE_ID_DIGF;
360 break;
361 default:
362 ASSERT_CRITICAL(false);
363 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
364 }
365
366 /* default to one to mirror Windows behavior */
367 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
368
369 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
370 enc10->base.id, &bp_cap_info);
371
372 /* Override features with DCE-specific values */
373 if (result == BP_RESULT_OK) {
374 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
375 bp_cap_info.DP_HBR2_EN;
376 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
377 bp_cap_info.DP_HBR3_EN;
378 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
379 enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;
380 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
381 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
382 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
383 enc10->base.features.flags.bits.DP_IS_USB_C =
384 bp_cap_info.DP_IS_USB_C;
385 } else {
386 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
387 __func__,
388 result);
389 }
390 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
391 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
392 }
393 }
394
dcn31_link_encoder_construct_minimal(struct dcn20_link_encoder * enc20,struct dc_context * ctx,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,enum engine_id eng_id)395 void dcn31_link_encoder_construct_minimal(
396 struct dcn20_link_encoder *enc20,
397 struct dc_context *ctx,
398 const struct encoder_feature_support *enc_features,
399 const struct dcn10_link_enc_registers *link_regs,
400 enum engine_id eng_id)
401 {
402 struct dcn10_link_encoder *enc10 = &enc20->enc10;
403
404 enc10->base.funcs = &dcn31_link_enc_funcs;
405 enc10->base.ctx = ctx;
406 enc10->base.id.type = OBJECT_TYPE_ENCODER;
407 enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
408 enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
409 enc10->base.preferred_engine = eng_id;
410 enc10->base.features = *enc_features;
411 enc10->base.transmitter = TRANSMITTER_UNKNOWN;
412 enc10->link_regs = link_regs;
413
414 enc10->base.output_signals =
415 SIGNAL_TYPE_DISPLAY_PORT |
416 SIGNAL_TYPE_DISPLAY_PORT_MST |
417 SIGNAL_TYPE_EDP;
418 }
419
420 /* DPIA equivalent of link_transmitter_control. */
link_dpia_control(struct dc_context * dc_ctx,struct dmub_cmd_dig_dpia_control_data * dpia_control)421 static bool link_dpia_control(struct dc_context *dc_ctx,
422 struct dmub_cmd_dig_dpia_control_data *dpia_control)
423 {
424 union dmub_rb_cmd cmd;
425 struct dc_dmub_srv *dmub = dc_ctx->dmub_srv;
426
427 memset(&cmd, 0, sizeof(cmd));
428
429 cmd.dig1_dpia_control.header.type = DMUB_CMD__DPIA;
430 cmd.dig1_dpia_control.header.sub_type =
431 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL;
432 cmd.dig1_dpia_control.header.payload_bytes =
433 sizeof(cmd.dig1_dpia_control) -
434 sizeof(cmd.dig1_dpia_control.header);
435
436 cmd.dig1_dpia_control.dpia_control = *dpia_control;
437
438 dc_dmub_srv_cmd_queue(dmub, &cmd);
439 dc_dmub_srv_cmd_execute(dmub);
440 dc_dmub_srv_wait_idle(dmub);
441
442 return true;
443 }
444
link_encoder_disable(struct dcn10_link_encoder * enc10)445 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
446 {
447 /* reset training complete */
448 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
449 }
450
dcn31_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)451 void dcn31_link_encoder_enable_dp_output(
452 struct link_encoder *enc,
453 const struct dc_link_settings *link_settings,
454 enum clock_source_id clock_source)
455 {
456 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
457
458 /* Enable transmitter and encoder. */
459 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
460
461 dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
462
463 } else {
464
465 struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
466 struct dc_link *link;
467
468 link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
469
470 enc1_configure_encoder(enc10, link_settings);
471
472 dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;
473 dpia_control.enc_id = enc->preferred_engine;
474 dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */
475 dpia_control.lanenum = (uint8_t)link_settings->lane_count;
476 dpia_control.symclk_10khz = link_settings->link_rate *
477 LINK_RATE_REF_FREQ_IN_KHZ / 10;
478 /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin
479 * unused by DPIA.
480 */
481 dpia_control.hpdsel = 6;
482
483 if (link) {
484 dpia_control.dpia_id = link->ddc_hw_inst;
485 dpia_control.fec_rdy = dc_link_should_enable_fec(link);
486 } else {
487 DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
488 BREAK_TO_DEBUGGER();
489 return;
490 }
491
492 link_dpia_control(enc->ctx, &dpia_control);
493 }
494 }
495
dcn31_link_encoder_enable_dp_mst_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)496 void dcn31_link_encoder_enable_dp_mst_output(
497 struct link_encoder *enc,
498 const struct dc_link_settings *link_settings,
499 enum clock_source_id clock_source)
500 {
501 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
502
503 /* Enable transmitter and encoder. */
504 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
505
506 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
507
508 } else {
509
510 struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
511 struct dc_link *link;
512
513 link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
514
515 enc1_configure_encoder(enc10, link_settings);
516
517 dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;
518 dpia_control.enc_id = enc->preferred_engine;
519 dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */
520 dpia_control.lanenum = (uint8_t)link_settings->lane_count;
521 dpia_control.symclk_10khz = link_settings->link_rate *
522 LINK_RATE_REF_FREQ_IN_KHZ / 10;
523 /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin
524 * unused by DPIA.
525 */
526 dpia_control.hpdsel = 6;
527
528 if (link) {
529 dpia_control.dpia_id = link->ddc_hw_inst;
530 dpia_control.fec_rdy = dc_link_should_enable_fec(link);
531 } else {
532 DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
533 BREAK_TO_DEBUGGER();
534 return;
535 }
536
537 link_dpia_control(enc->ctx, &dpia_control);
538 }
539 }
540
dcn31_link_encoder_disable_output(struct link_encoder * enc,enum signal_type signal)541 void dcn31_link_encoder_disable_output(
542 struct link_encoder *enc,
543 enum signal_type signal)
544 {
545 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
546
547 /* Disable transmitter and encoder. */
548 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
549
550 dcn10_link_encoder_disable_output(enc, signal);
551
552 } else {
553
554 struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
555 struct dc_link *link;
556
557 if (!dcn10_is_dig_enabled(enc))
558 return;
559
560 link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
561
562 dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_DISABLE;
563 dpia_control.enc_id = enc->preferred_engine;
564 if (signal == SIGNAL_TYPE_DISPLAY_PORT) {
565 dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */
566 } else if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
567 dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */
568 } else {
569 DC_LOG_ERROR("%s: USB4 DPIA only supports DisplayPort.\n", __func__);
570 BREAK_TO_DEBUGGER();
571 }
572
573 if (link) {
574 dpia_control.dpia_id = link->ddc_hw_inst;
575 } else {
576 DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
577 BREAK_TO_DEBUGGER();
578 return;
579 }
580
581 link_dpia_control(enc->ctx, &dpia_control);
582
583 link_encoder_disable(enc10);
584 }
585 }
586
dcn31_link_encoder_is_in_alt_mode(struct link_encoder * enc)587 bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
588 {
589 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
590 union dmub_rb_cmd cmd;
591 uint32_t dp_alt_mode_disable;
592
593 /* Only applicable to USB-C PHY. */
594 if (!enc->features.flags.bits.DP_IS_USB_C)
595 return false;
596
597 /*
598 * Use the new interface from DMCUB if available.
599 * Avoids hanging the RDCPSPIPE if DMCUB wasn't already running.
600 */
601 if (has_query_dp_alt(enc)) {
602 if (!query_dp_alt_from_dmub(enc, &cmd))
603 return false;
604
605 return (cmd.query_dp_alt.data.is_dp_alt_disable == 0);
606 }
607
608 /* Legacy path, avoid if possible. */
609 if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
610 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
611 &dp_alt_mode_disable);
612 } else {
613 /*
614 * B0 phys use a new set of registers to check whether alt mode is disabled.
615 * if value == 1 alt mode is disabled, otherwise it is enabled.
616 */
617 if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A) ||
618 (enc10->base.transmitter == TRANSMITTER_UNIPHY_B) ||
619 (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
620 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
621 &dp_alt_mode_disable);
622 } else {
623 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
624 &dp_alt_mode_disable);
625 }
626 }
627
628 return (dp_alt_mode_disable == 0);
629 }
630
dcn31_link_encoder_get_max_link_cap(struct link_encoder * enc,struct dc_link_settings * link_settings)631 void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc, struct dc_link_settings *link_settings)
632 {
633 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
634 union dmub_rb_cmd cmd;
635 uint32_t is_in_usb_c_dp4_mode = 0;
636
637 dcn10_link_encoder_get_max_link_cap(enc, link_settings);
638
639 /* Take the link cap directly if not USB */
640 if (!enc->features.flags.bits.DP_IS_USB_C)
641 return;
642
643 /*
644 * Use the new interface from DMCUB if available.
645 * Avoids hanging the RDCPSPIPE if DMCUB wasn't already running.
646 */
647 if (has_query_dp_alt(enc)) {
648 if (!query_dp_alt_from_dmub(enc, &cmd))
649 return;
650
651 if (cmd.query_dp_alt.data.is_usb &&
652 cmd.query_dp_alt.data.is_dp4 == 0)
653 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
654
655 return;
656 }
657
658 /* Legacy path, avoid if possible. */
659 if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
660 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
661 &is_in_usb_c_dp4_mode);
662 } else {
663 if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A) ||
664 (enc10->base.transmitter == TRANSMITTER_UNIPHY_B) ||
665 (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
666 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
667 &is_in_usb_c_dp4_mode);
668 } else {
669 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
670 &is_in_usb_c_dp4_mode);
671 }
672 }
673
674 if (!is_in_usb_c_dp4_mode)
675 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
676 }
677