1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "reg_helper.h"
29 #include "dcn30_dpp.h"
30 #include "basics/conversion.h"
31 #include "dcn30_cm_common.h"
32
33 #define REG(reg)\
34 dpp->tf_regs->reg
35
36 #define CTX \
37 dpp->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
dpp30_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)44 static void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
45 {
46 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
47
48 REG_GET(DPP_CONTROL,
49 DPP_CLOCK_ENABLE, &s->is_enabled);
50
51 // TODO: Implement for DCN3
52 }
53 /*program post scaler scs block in dpp CM*/
dpp3_program_post_csc(struct dpp * dpp_base,enum dc_color_space color_space,enum dcn10_input_csc_select input_select,const struct out_csc_color_matrix * tbl_entry)54 void dpp3_program_post_csc(
55 struct dpp *dpp_base,
56 enum dc_color_space color_space,
57 enum dcn10_input_csc_select input_select,
58 const struct out_csc_color_matrix *tbl_entry)
59 {
60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
61 int i;
62 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
63 const uint16_t *regval = NULL;
64 uint32_t cur_select = 0;
65 enum dcn10_input_csc_select select;
66 struct color_matrices_reg gam_regs;
67
68 if (input_select == INPUT_CSC_SELECT_BYPASS) {
69 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
70 return;
71 }
72
73 if (tbl_entry == NULL) {
74 for (i = 0; i < arr_size; i++)
75 if (dpp_input_csc_matrix[i].color_space == color_space) {
76 regval = dpp_input_csc_matrix[i].regval;
77 break;
78 }
79
80 if (regval == NULL) {
81 BREAK_TO_DEBUGGER();
82 return;
83 }
84 } else {
85 regval = tbl_entry->regval;
86 }
87
88 /* determine which CSC matrix (icsc or coma) we are using
89 * currently. select the alternate set to double buffer
90 * the CSC update so CSC is updated on frame boundary
91 */
92 REG_GET(CM_POST_CSC_CONTROL,
93 CM_POST_CSC_MODE_CURRENT, &cur_select);
94
95 if (cur_select != INPUT_CSC_SELECT_ICSC)
96 select = INPUT_CSC_SELECT_ICSC;
97 else
98 select = INPUT_CSC_SELECT_COMA;
99
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
104
105 if (select == INPUT_CSC_SELECT_ICSC) {
106
107 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
108 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
109
110 } else {
111
112 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
113 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
114
115 }
116
117 cm_helper_program_color_matrices(
118 dpp->base.ctx,
119 regval,
120 &gam_regs);
121
122 REG_SET(CM_POST_CSC_CONTROL, 0,
123 CM_POST_CSC_MODE, select);
124 }
125
126
127 /*CNVC degam unit has read only LUTs*/
dpp3_set_pre_degam(struct dpp * dpp_base,enum dc_transfer_func_predefined tr)128 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
129 {
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
131 int pre_degam_en = 1;
132 int degamma_lut_selection = 0;
133
134 switch (tr) {
135 case TRANSFER_FUNCTION_LINEAR:
136 case TRANSFER_FUNCTION_UNITY:
137 pre_degam_en = 0; //bypass
138 break;
139 case TRANSFER_FUNCTION_SRGB:
140 degamma_lut_selection = 0;
141 break;
142 case TRANSFER_FUNCTION_BT709:
143 degamma_lut_selection = 4;
144 break;
145 case TRANSFER_FUNCTION_PQ:
146 degamma_lut_selection = 5;
147 break;
148 case TRANSFER_FUNCTION_HLG:
149 degamma_lut_selection = 6;
150 break;
151 case TRANSFER_FUNCTION_GAMMA22:
152 degamma_lut_selection = 1;
153 break;
154 case TRANSFER_FUNCTION_GAMMA24:
155 degamma_lut_selection = 2;
156 break;
157 case TRANSFER_FUNCTION_GAMMA26:
158 degamma_lut_selection = 3;
159 break;
160 default:
161 pre_degam_en = 0;
162 break;
163 }
164
165 REG_SET_2(PRE_DEGAM, 0,
166 PRE_DEGAM_MODE, pre_degam_en,
167 PRE_DEGAM_SELECT, degamma_lut_selection);
168 }
169
dpp3_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)170 static void dpp3_cnv_setup (
171 struct dpp *dpp_base,
172 enum surface_pixel_format format,
173 enum expansion_mode mode,
174 struct dc_csc_transform input_csc_color_matrix,
175 enum dc_color_space input_color_space,
176 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
177 {
178 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
179 uint32_t pixel_format = 0;
180 uint32_t alpha_en = 1;
181 enum dc_color_space color_space = COLOR_SPACE_SRGB;
182 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
183 bool force_disable_cursor = false;
184 uint32_t is_2bit = 0;
185 uint32_t alpha_plane_enable = 0;
186 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
187 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
188 uint32_t program_prealpha_dealpha = 0;
189 struct out_csc_color_matrix tbl_entry;
190 int i;
191
192 REG_SET_2(FORMAT_CONTROL, 0,
193 CNVC_BYPASS, 0,
194 FORMAT_EXPANSION_MODE, mode);
195
196 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
197 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
198 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
200
201 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
204
205 switch (format) {
206 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
207 pixel_format = 1;
208 break;
209 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
210 pixel_format = 3;
211 alpha_en = 0;
212 break;
213 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
214 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
215 pixel_format = 8;
216 break;
217 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
218 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
219 pixel_format = 10;
220 is_2bit = 1;
221 break;
222 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
223 force_disable_cursor = false;
224 pixel_format = 65;
225 color_space = COLOR_SPACE_YCBCR709;
226 select = INPUT_CSC_SELECT_ICSC;
227 break;
228 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
229 force_disable_cursor = true;
230 pixel_format = 64;
231 color_space = COLOR_SPACE_YCBCR709;
232 select = INPUT_CSC_SELECT_ICSC;
233 break;
234 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
235 force_disable_cursor = true;
236 pixel_format = 67;
237 color_space = COLOR_SPACE_YCBCR709;
238 select = INPUT_CSC_SELECT_ICSC;
239 break;
240 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
241 force_disable_cursor = true;
242 pixel_format = 66;
243 color_space = COLOR_SPACE_YCBCR709;
244 select = INPUT_CSC_SELECT_ICSC;
245 break;
246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
247 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
248 pixel_format = 26; /* ARGB16161616_UNORM */
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
251 pixel_format = 24;
252 break;
253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
254 pixel_format = 25;
255 break;
256 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
257 pixel_format = 12;
258 color_space = COLOR_SPACE_YCBCR709;
259 select = INPUT_CSC_SELECT_ICSC;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
262 pixel_format = 112;
263 break;
264 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
265 pixel_format = 113;
266 break;
267 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
268 pixel_format = 114;
269 color_space = COLOR_SPACE_YCBCR709;
270 select = INPUT_CSC_SELECT_ICSC;
271 is_2bit = 1;
272 break;
273 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
274 pixel_format = 115;
275 color_space = COLOR_SPACE_YCBCR709;
276 select = INPUT_CSC_SELECT_ICSC;
277 is_2bit = 1;
278 break;
279 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
280 pixel_format = 116;
281 alpha_plane_enable = 0;
282 break;
283 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
284 pixel_format = 116;
285 alpha_plane_enable = 1;
286 break;
287 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
288 pixel_format = 118;
289 break;
290 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
291 pixel_format = 119;
292 break;
293 default:
294 break;
295 }
296
297 /* Set default color space based on format if none is given. */
298 color_space = input_color_space ? input_color_space : color_space;
299
300 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
302 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
303 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
304 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
305 }
306
307 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
308 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
309 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
310 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
311
312 if (program_prealpha_dealpha) {
313 dealpha_en = 1;
314 realpha_en = 1;
315 }
316 REG_SET_2(PRE_DEALPHA, 0,
317 PRE_DEALPHA_EN, dealpha_en,
318 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
319 REG_SET_2(PRE_REALPHA, 0,
320 PRE_REALPHA_EN, realpha_en,
321 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
322
323 /* If input adjustment exists, program the ICSC with those values. */
324 if (input_csc_color_matrix.enable_adjustment == true) {
325 for (i = 0; i < 12; i++)
326 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
327
328 tbl_entry.color_space = input_color_space;
329
330 if (color_space >= COLOR_SPACE_YCBCR601)
331 select = INPUT_CSC_SELECT_ICSC;
332 else
333 select = INPUT_CSC_SELECT_BYPASS;
334
335 dpp3_program_post_csc(dpp_base, color_space, select,
336 &tbl_entry);
337 } else {
338 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
339 }
340
341 if (force_disable_cursor) {
342 REG_UPDATE(CURSOR_CONTROL,
343 CURSOR_ENABLE, 0);
344 REG_UPDATE(CURSOR0_CONTROL,
345 CUR0_ENABLE, 0);
346 }
347 }
348
349 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
350
dpp3_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)351 void dpp3_set_cursor_attributes(
352 struct dpp *dpp_base,
353 struct dc_cursor_attributes *cursor_attributes)
354 {
355 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
356 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
357 int cur_rom_en = 0;
358
359 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
360 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
361 cur_rom_en = 1;
362
363 REG_UPDATE_3(CURSOR0_CONTROL,
364 CUR0_MODE, color_format,
365 CUR0_EXPANSION_MODE, 0,
366 CUR0_ROM_EN, cur_rom_en);
367
368 if (color_format == CURSOR_MODE_MONO) {
369 /* todo: clarify what to program these to */
370 REG_UPDATE(CURSOR0_COLOR0,
371 CUR0_COLOR0, 0x00000000);
372 REG_UPDATE(CURSOR0_COLOR1,
373 CUR0_COLOR1, 0xFFFFFFFF);
374 }
375 }
376
377
dpp3_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps)378 static bool dpp3_get_optimal_number_of_taps(
379 struct dpp *dpp,
380 struct scaler_data *scl_data,
381 const struct scaling_taps *in_taps)
382 {
383 int num_part_y, num_part_c;
384 int max_taps_y, max_taps_c;
385 int min_taps_y, min_taps_c;
386 enum lb_memory_config lb_config;
387
388 if (scl_data->viewport.width > scl_data->h_active &&
389 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
390 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
391 return false;
392
393 /*
394 * Set default taps if none are provided
395 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
396 * taps = 4 for upscaling
397 */
398 if (in_taps->h_taps == 0) {
399 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
400 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
401 else
402 scl_data->taps.h_taps = 4;
403 } else
404 scl_data->taps.h_taps = in_taps->h_taps;
405 if (in_taps->v_taps == 0) {
406 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
407 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
408 else
409 scl_data->taps.v_taps = 4;
410 } else
411 scl_data->taps.v_taps = in_taps->v_taps;
412 if (in_taps->v_taps_c == 0) {
413 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
414 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
415 else
416 scl_data->taps.v_taps_c = 4;
417 } else
418 scl_data->taps.v_taps_c = in_taps->v_taps_c;
419 if (in_taps->h_taps_c == 0) {
420 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
421 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
422 else
423 scl_data->taps.h_taps_c = 4;
424 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
425 /* Only 1 and even h_taps_c are supported by hw */
426 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
427 else
428 scl_data->taps.h_taps_c = in_taps->h_taps_c;
429
430 /*Ensure we can support the requested number of vtaps*/
431 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
432 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
433
434 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
435 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
436 lb_config = LB_MEMORY_CONFIG_3;
437 else
438 lb_config = LB_MEMORY_CONFIG_0;
439
440 dpp->caps->dscl_calc_lb_num_partitions(
441 scl_data, lb_config, &num_part_y, &num_part_c);
442
443 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
444 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
445 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
446 else
447 max_taps_y = num_part_y;
448
449 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
450 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
451 else
452 max_taps_c = num_part_c;
453
454 if (max_taps_y < min_taps_y)
455 return false;
456 else if (max_taps_c < min_taps_c)
457 return false;
458
459 if (scl_data->taps.v_taps > max_taps_y)
460 scl_data->taps.v_taps = max_taps_y;
461
462 if (scl_data->taps.v_taps_c > max_taps_c)
463 scl_data->taps.v_taps_c = max_taps_c;
464
465 if (!dpp->ctx->dc->debug.always_scale) {
466 if (IDENTITY_RATIO(scl_data->ratios.horz))
467 scl_data->taps.h_taps = 1;
468 if (IDENTITY_RATIO(scl_data->ratios.vert))
469 scl_data->taps.v_taps = 1;
470 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
471 scl_data->taps.h_taps_c = 1;
472 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
473 scl_data->taps.v_taps_c = 1;
474 }
475
476 return true;
477 }
478
dpp3_deferred_update(struct dpp * dpp_base)479 static void dpp3_deferred_update(struct dpp *dpp_base)
480 {
481 int bypass_state;
482 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
483
484 if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
485 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
486 dpp_base->deferred_reg_writes.bits.disable_dscl = false;
487 }
488
489 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {
490 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
491 if (bypass_state == 0) { // only program if bypass was latched
492 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);
493 } else
494 ASSERT(0); // LUT select was updated again before vupdate
495 dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
496 }
497
498 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
499 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
500 if (bypass_state == 0) { // only program if bypass was latched
501 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
502 } else
503 ASSERT(0); // LUT select was updated again before vupdate
504 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
505 }
506
507 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
508 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
509 if (bypass_state == 0) { // only program if bypass was latched
510 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
511 } else
512 ASSERT(0); // LUT select was updated again before vupdate
513 dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
514 }
515
516 if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
517 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
518 if (bypass_state == 0) { // only program if bypass was latched
519 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
520 } else
521 ASSERT(0); // LUT select was updated again before vupdate
522 dpp_base->deferred_reg_writes.bits.disable_shaper = false;
523 }
524 }
525
dpp3_power_on_blnd_lut(struct dpp * dpp_base,bool power_on)526 static void dpp3_power_on_blnd_lut(
527 struct dpp *dpp_base,
528 bool power_on)
529 {
530 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
531
532 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
533 if (power_on) {
534 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
535 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
536 } else {
537 dpp_base->ctx->dc->optimized_required = true;
538 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
539 }
540 } else {
541 REG_SET(CM_MEM_PWR_CTRL, 0,
542 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
543 }
544 }
545
dpp3_power_on_hdr3dlut(struct dpp * dpp_base,bool power_on)546 static void dpp3_power_on_hdr3dlut(
547 struct dpp *dpp_base,
548 bool power_on)
549 {
550 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
551
552 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
553 if (power_on) {
554 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
555 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
556 } else {
557 dpp_base->ctx->dc->optimized_required = true;
558 dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
559 }
560 }
561 }
562
dpp3_power_on_shaper(struct dpp * dpp_base,bool power_on)563 static void dpp3_power_on_shaper(
564 struct dpp *dpp_base,
565 bool power_on)
566 {
567 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
568
569 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
570 if (power_on) {
571 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
572 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
573 } else {
574 dpp_base->ctx->dc->optimized_required = true;
575 dpp_base->deferred_reg_writes.bits.disable_shaper = true;
576 }
577 }
578 }
579
dpp3_configure_blnd_lut(struct dpp * dpp_base,bool is_ram_a)580 static void dpp3_configure_blnd_lut(
581 struct dpp *dpp_base,
582 bool is_ram_a)
583 {
584 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
585
586 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
587 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
588 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
589
590 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
591 }
592
dpp3_program_blnd_pwl(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)593 static void dpp3_program_blnd_pwl(
594 struct dpp *dpp_base,
595 const struct pwl_result_data *rgb,
596 uint32_t num)
597 {
598 uint32_t i;
599 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
600 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
601 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
602 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
603
604 if (is_rgb_equal(rgb, num)) {
605 for (i = 0 ; i < num; i++)
606 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
607 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
608 } else {
609 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
610 for (i = 0 ; i < num; i++)
611 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
612 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
613
614 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
615 for (i = 0 ; i < num; i++)
616 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
617 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
618
619 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
620 for (i = 0 ; i < num; i++)
621 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
622 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
623 }
624 }
625
dcn3_dpp_cm_get_reg_field(struct dcn3_dpp * dpp,struct dcn3_xfer_func_reg * reg)626 static void dcn3_dpp_cm_get_reg_field(
627 struct dcn3_dpp *dpp,
628 struct dcn3_xfer_func_reg *reg)
629 {
630 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
631 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
632 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
633 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
634 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
635 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
636 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
637 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
638
639 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
640 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
641 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
642 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
643 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
644 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
645 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
646 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
647 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
648 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
649 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
650 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
651 }
652
653 /*program blnd lut RAM A*/
dpp3_program_blnd_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)654 static void dpp3_program_blnd_luta_settings(
655 struct dpp *dpp_base,
656 const struct pwl_params *params)
657 {
658 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
659 struct dcn3_xfer_func_reg gam_regs;
660
661 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
662
663 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
664 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
665 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
666 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
667 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
668 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
669 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
670 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
671 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
672 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
673 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
674 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
675 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
676 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
677
678 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
679 }
680
681 /*program blnd lut RAM B*/
dpp3_program_blnd_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)682 static void dpp3_program_blnd_lutb_settings(
683 struct dpp *dpp_base,
684 const struct pwl_params *params)
685 {
686 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
687 struct dcn3_xfer_func_reg gam_regs;
688
689 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
690
691 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
692 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
693 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
694 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
695 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
696 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
697 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
698 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
699 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
700 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
701 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
702 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
703 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
704 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
705
706 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
707 }
708
dpp3_get_blndgam_current(struct dpp * dpp_base)709 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
710 {
711 enum dc_lut_mode mode;
712 uint32_t mode_current = 0;
713 uint32_t in_use = 0;
714
715 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
716
717 REG_GET(CM_BLNDGAM_CONTROL,
718 CM_BLNDGAM_MODE_CURRENT, &mode_current);
719 REG_GET(CM_BLNDGAM_CONTROL,
720 CM_BLNDGAM_SELECT_CURRENT, &in_use);
721
722 switch (mode_current) {
723 case 0:
724 case 1:
725 mode = LUT_BYPASS;
726 break;
727
728 case 2:
729 if (in_use == 0)
730 mode = LUT_RAM_A;
731 else
732 mode = LUT_RAM_B;
733 break;
734 default:
735 mode = LUT_BYPASS;
736 break;
737 }
738 return mode;
739 }
740
dpp3_program_blnd_lut(struct dpp * dpp_base,const struct pwl_params * params)741 static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
742 const struct pwl_params *params)
743 {
744 enum dc_lut_mode current_mode;
745 enum dc_lut_mode next_mode;
746 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
747
748 if (params == NULL) {
749 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
750 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
751 dpp3_power_on_blnd_lut(dpp_base, false);
752 return false;
753 }
754
755 current_mode = dpp3_get_blndgam_current(dpp_base);
756 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
757 next_mode = LUT_RAM_A;
758 else
759 next_mode = LUT_RAM_B;
760
761 dpp3_power_on_blnd_lut(dpp_base, true);
762 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
763
764 if (next_mode == LUT_RAM_A)
765 dpp3_program_blnd_luta_settings(dpp_base, params);
766 else
767 dpp3_program_blnd_lutb_settings(dpp_base, params);
768
769 dpp3_program_blnd_pwl(
770 dpp_base, params->rgb_resulted, params->hw_points_num);
771
772 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
773 CM_BLNDGAM_MODE, 2,
774 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
775
776 return true;
777 }
778
779
dpp3_program_shaper_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)780 static void dpp3_program_shaper_lut(
781 struct dpp *dpp_base,
782 const struct pwl_result_data *rgb,
783 uint32_t num)
784 {
785 uint32_t i, red, green, blue;
786 uint32_t red_delta, green_delta, blue_delta;
787 uint32_t red_value, green_value, blue_value;
788
789 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
790
791 for (i = 0 ; i < num; i++) {
792
793 red = rgb[i].red_reg;
794 green = rgb[i].green_reg;
795 blue = rgb[i].blue_reg;
796
797 red_delta = rgb[i].delta_red_reg;
798 green_delta = rgb[i].delta_green_reg;
799 blue_delta = rgb[i].delta_blue_reg;
800
801 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
802 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
803 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
804
805 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
806 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
807 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
808 }
809
810 }
811
dpp3_get_shaper_current(struct dpp * dpp_base)812 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
813 {
814 enum dc_lut_mode mode;
815 uint32_t state_mode;
816 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
817
818 REG_GET(CM_SHAPER_CONTROL,
819 CM_SHAPER_MODE_CURRENT, &state_mode);
820
821 switch (state_mode) {
822 case 0:
823 mode = LUT_BYPASS;
824 break;
825 case 1:
826 mode = LUT_RAM_A;
827 break;
828 case 2:
829 mode = LUT_RAM_B;
830 break;
831 default:
832 mode = LUT_BYPASS;
833 break;
834 }
835 return mode;
836 }
837
dpp3_configure_shaper_lut(struct dpp * dpp_base,bool is_ram_a)838 static void dpp3_configure_shaper_lut(
839 struct dpp *dpp_base,
840 bool is_ram_a)
841 {
842 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
843
844 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
845 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
846 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
847 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
848 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
849 }
850
851 /*program shaper RAM A*/
852
dpp3_program_shaper_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)853 static void dpp3_program_shaper_luta_settings(
854 struct dpp *dpp_base,
855 const struct pwl_params *params)
856 {
857 const struct gamma_curve *curve;
858 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
859
860 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
861 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
862 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
863 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
864 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
865 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
866 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
867 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
868 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
869
870 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
871 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
872 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
873
874 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
875 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
876 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
877
878 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
879 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
880 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
881
882 curve = params->arr_curve_points;
883 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
884 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
885 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
886 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
887 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
888
889 curve += 2;
890 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
891 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
892 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
893 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
894 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
895
896 curve += 2;
897 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
898 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
899 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
900 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
901 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
902
903 curve += 2;
904 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
905 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
906 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
907 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
908 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
909
910 curve += 2;
911 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
912 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
913 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
914 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
915 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
916
917 curve += 2;
918 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
919 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
920 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
921 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
922 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
923
924 curve += 2;
925 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
926 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
927 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
928 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
929 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
930
931 curve += 2;
932 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
933 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
934 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
935 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
936 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
937
938 curve += 2;
939 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
940 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
941 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
942 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
943 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
944
945 curve += 2;
946 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
947 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
948 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
949 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
950 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
951
952 curve += 2;
953 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
954 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
955 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
956 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
957 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
958
959 curve += 2;
960 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
961 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
962 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
963 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
964 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
965
966 curve += 2;
967 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
968 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
969 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
970 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
971 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
972
973 curve += 2;
974 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
975 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
976 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
977 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
978 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
979
980 curve += 2;
981 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
982 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
983 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
984 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
985 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
986
987 curve += 2;
988 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
989 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
990 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
991 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
992 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
993
994 curve += 2;
995 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
996 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
997 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
998 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
999 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1000 }
1001
1002 /*program shaper RAM B*/
dpp3_program_shaper_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)1003 static void dpp3_program_shaper_lutb_settings(
1004 struct dpp *dpp_base,
1005 const struct pwl_params *params)
1006 {
1007 const struct gamma_curve *curve;
1008 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1009
1010 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
1011 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
1012 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
1013 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
1014 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
1015 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
1016 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
1017 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
1018 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
1019
1020 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
1021 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
1022 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
1023
1024 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
1025 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
1026 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
1027
1028 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
1029 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
1030 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
1031
1032 curve = params->arr_curve_points;
1033 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
1034 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1035 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1036 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1037 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1038
1039 curve += 2;
1040 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1041 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1042 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1043 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1044 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1045
1046 curve += 2;
1047 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1048 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1049 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1050 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1051 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1052
1053 curve += 2;
1054 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1055 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1056 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1057 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1058 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1059
1060 curve += 2;
1061 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1062 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1063 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1064 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1065 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1066
1067 curve += 2;
1068 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1069 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1070 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1071 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1072 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1073
1074 curve += 2;
1075 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1076 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1077 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1078 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1079 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1080
1081 curve += 2;
1082 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1083 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1084 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1085 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1086 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1087
1088 curve += 2;
1089 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1090 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1091 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1092 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1093 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1094
1095 curve += 2;
1096 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1097 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1098 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1099 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1100 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1101
1102 curve += 2;
1103 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1104 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1105 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1106 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1107 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1108
1109 curve += 2;
1110 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1111 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1112 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1113 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1114 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1115
1116 curve += 2;
1117 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1118 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1119 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1120 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1121 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1122
1123 curve += 2;
1124 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1125 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1126 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1127 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1128 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1129
1130 curve += 2;
1131 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1132 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1133 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1134 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1135 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1136
1137 curve += 2;
1138 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1139 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1140 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1141 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1142 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1143
1144 curve += 2;
1145 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1146 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1147 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1148 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1149 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1150
1151 }
1152
1153
dpp3_program_shaper(struct dpp * dpp_base,const struct pwl_params * params)1154 static bool dpp3_program_shaper(struct dpp *dpp_base,
1155 const struct pwl_params *params)
1156 {
1157 enum dc_lut_mode current_mode;
1158 enum dc_lut_mode next_mode;
1159
1160 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1161
1162 if (params == NULL) {
1163 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1164 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1165 dpp3_power_on_shaper(dpp_base, false);
1166 return false;
1167 }
1168
1169 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1170 dpp3_power_on_shaper(dpp_base, true);
1171
1172 current_mode = dpp3_get_shaper_current(dpp_base);
1173
1174 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1175 next_mode = LUT_RAM_B;
1176 else
1177 next_mode = LUT_RAM_A;
1178
1179 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1180
1181 if (next_mode == LUT_RAM_A)
1182 dpp3_program_shaper_luta_settings(dpp_base, params);
1183 else
1184 dpp3_program_shaper_lutb_settings(dpp_base, params);
1185
1186 dpp3_program_shaper_lut(
1187 dpp_base, params->rgb_resulted, params->hw_points_num);
1188
1189 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1190
1191 return true;
1192
1193 }
1194
get3dlut_config(struct dpp * dpp_base,bool * is_17x17x17,bool * is_12bits_color_channel)1195 static enum dc_lut_mode get3dlut_config(
1196 struct dpp *dpp_base,
1197 bool *is_17x17x17,
1198 bool *is_12bits_color_channel)
1199 {
1200 uint32_t i_mode, i_enable_10bits, lut_size;
1201 enum dc_lut_mode mode;
1202 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1203
1204 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1205 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1206 REG_GET(CM_3DLUT_MODE,
1207 CM_3DLUT_MODE_CURRENT, &i_mode);
1208
1209 switch (i_mode) {
1210 case 0:
1211 mode = LUT_BYPASS;
1212 break;
1213 case 1:
1214 mode = LUT_RAM_A;
1215 break;
1216 case 2:
1217 mode = LUT_RAM_B;
1218 break;
1219 default:
1220 mode = LUT_BYPASS;
1221 break;
1222 }
1223 if (i_enable_10bits > 0)
1224 *is_12bits_color_channel = false;
1225 else
1226 *is_12bits_color_channel = true;
1227
1228 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1229
1230 if (lut_size == 0)
1231 *is_17x17x17 = true;
1232 else
1233 *is_17x17x17 = false;
1234
1235 return mode;
1236 }
1237 /*
1238 * select ramA or ramB, or bypass
1239 * select color channel size 10 or 12 bits
1240 * select 3dlut size 17x17x17 or 9x9x9
1241 */
dpp3_set_3dlut_mode(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17)1242 static void dpp3_set_3dlut_mode(
1243 struct dpp *dpp_base,
1244 enum dc_lut_mode mode,
1245 bool is_color_channel_12bits,
1246 bool is_lut_size17x17x17)
1247 {
1248 uint32_t lut_mode;
1249 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1250
1251 if (mode == LUT_BYPASS)
1252 lut_mode = 0;
1253 else if (mode == LUT_RAM_A)
1254 lut_mode = 1;
1255 else
1256 lut_mode = 2;
1257
1258 REG_UPDATE_2(CM_3DLUT_MODE,
1259 CM_3DLUT_MODE, lut_mode,
1260 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1261 }
1262
dpp3_select_3dlut_ram(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits)1263 static void dpp3_select_3dlut_ram(
1264 struct dpp *dpp_base,
1265 enum dc_lut_mode mode,
1266 bool is_color_channel_12bits)
1267 {
1268 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1269
1270 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1271 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1272 CM_3DLUT_30BIT_EN,
1273 is_color_channel_12bits == true ? 0:1);
1274 }
1275
1276
1277
dpp3_set3dlut_ram12(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1278 static void dpp3_set3dlut_ram12(
1279 struct dpp *dpp_base,
1280 const struct dc_rgb *lut,
1281 uint32_t entries)
1282 {
1283 uint32_t i, red, green, blue, red1, green1, blue1;
1284 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1285
1286 for (i = 0 ; i < entries; i += 2) {
1287 red = lut[i].red<<4;
1288 green = lut[i].green<<4;
1289 blue = lut[i].blue<<4;
1290 red1 = lut[i+1].red<<4;
1291 green1 = lut[i+1].green<<4;
1292 blue1 = lut[i+1].blue<<4;
1293
1294 REG_SET_2(CM_3DLUT_DATA, 0,
1295 CM_3DLUT_DATA0, red,
1296 CM_3DLUT_DATA1, red1);
1297
1298 REG_SET_2(CM_3DLUT_DATA, 0,
1299 CM_3DLUT_DATA0, green,
1300 CM_3DLUT_DATA1, green1);
1301
1302 REG_SET_2(CM_3DLUT_DATA, 0,
1303 CM_3DLUT_DATA0, blue,
1304 CM_3DLUT_DATA1, blue1);
1305
1306 }
1307 }
1308
1309 /*
1310 * load selected lut with 10 bits color channels
1311 */
dpp3_set3dlut_ram10(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1312 static void dpp3_set3dlut_ram10(
1313 struct dpp *dpp_base,
1314 const struct dc_rgb *lut,
1315 uint32_t entries)
1316 {
1317 uint32_t i, red, green, blue, value;
1318 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1319
1320 for (i = 0; i < entries; i++) {
1321 red = lut[i].red;
1322 green = lut[i].green;
1323 blue = lut[i].blue;
1324
1325 value = (red<<20) | (green<<10) | blue;
1326
1327 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1328 }
1329
1330 }
1331
1332
dpp3_select_3dlut_ram_mask(struct dpp * dpp_base,uint32_t ram_selection_mask)1333 static void dpp3_select_3dlut_ram_mask(
1334 struct dpp *dpp_base,
1335 uint32_t ram_selection_mask)
1336 {
1337 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1338
1339 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1340 ram_selection_mask);
1341 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1342 }
1343
dpp3_program_3dlut(struct dpp * dpp_base,struct tetrahedral_params * params)1344 static bool dpp3_program_3dlut(struct dpp *dpp_base,
1345 struct tetrahedral_params *params)
1346 {
1347 enum dc_lut_mode mode;
1348 bool is_17x17x17;
1349 bool is_12bits_color_channel;
1350 struct dc_rgb *lut0;
1351 struct dc_rgb *lut1;
1352 struct dc_rgb *lut2;
1353 struct dc_rgb *lut3;
1354 int lut_size0;
1355 int lut_size;
1356
1357 if (params == NULL) {
1358 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1359 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1360 dpp3_power_on_hdr3dlut(dpp_base, false);
1361 return false;
1362 }
1363
1364 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1365 dpp3_power_on_hdr3dlut(dpp_base, true);
1366
1367 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1368
1369 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1370 mode = LUT_RAM_A;
1371 else
1372 mode = LUT_RAM_B;
1373
1374 is_17x17x17 = !params->use_tetrahedral_9;
1375 is_12bits_color_channel = params->use_12bits;
1376 if (is_17x17x17) {
1377 lut0 = params->tetrahedral_17.lut0;
1378 lut1 = params->tetrahedral_17.lut1;
1379 lut2 = params->tetrahedral_17.lut2;
1380 lut3 = params->tetrahedral_17.lut3;
1381 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1382 sizeof(params->tetrahedral_17.lut0[0]);
1383 lut_size = sizeof(params->tetrahedral_17.lut1)/
1384 sizeof(params->tetrahedral_17.lut1[0]);
1385 } else {
1386 lut0 = params->tetrahedral_9.lut0;
1387 lut1 = params->tetrahedral_9.lut1;
1388 lut2 = params->tetrahedral_9.lut2;
1389 lut3 = params->tetrahedral_9.lut3;
1390 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1391 sizeof(params->tetrahedral_9.lut0[0]);
1392 lut_size = sizeof(params->tetrahedral_9.lut1)/
1393 sizeof(params->tetrahedral_9.lut1[0]);
1394 }
1395
1396 dpp3_select_3dlut_ram(dpp_base, mode,
1397 is_12bits_color_channel);
1398 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1399 if (is_12bits_color_channel)
1400 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1401 else
1402 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1403
1404 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1405 if (is_12bits_color_channel)
1406 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1407 else
1408 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1409
1410 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1411 if (is_12bits_color_channel)
1412 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1413 else
1414 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1415
1416 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1417 if (is_12bits_color_channel)
1418 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1419 else
1420 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1421
1422
1423 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1424 is_17x17x17);
1425
1426 return true;
1427 }
1428 static struct dpp_funcs dcn30_dpp_funcs = {
1429 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1430 .dpp_read_state = dpp30_read_state,
1431 .dpp_reset = dpp_reset,
1432 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1433 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1434 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1435 .dpp_set_csc_adjustment = NULL,
1436 .dpp_set_csc_default = NULL,
1437 .dpp_program_regamma_pwl = NULL,
1438 .dpp_set_pre_degam = dpp3_set_pre_degam,
1439 .dpp_program_input_lut = NULL,
1440 .dpp_full_bypass = dpp1_full_bypass,
1441 .dpp_setup = dpp3_cnv_setup,
1442 .dpp_program_degamma_pwl = NULL,
1443 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1444 .dpp_program_cm_bias = dpp3_program_cm_bias,
1445 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1446 .dpp_program_shaper_lut = dpp3_program_shaper,
1447 .dpp_program_3dlut = dpp3_program_3dlut,
1448 .dpp_deferred_update = dpp3_deferred_update,
1449 .dpp_program_bias_and_scale = NULL,
1450 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1451 .set_cursor_attributes = dpp3_set_cursor_attributes,
1452 .set_cursor_position = dpp1_set_cursor_position,
1453 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1454 .dpp_dppclk_control = dpp1_dppclk_control,
1455 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1456 };
1457
1458
1459 static struct dpp_caps dcn30_dpp_cap = {
1460 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1461 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1462 };
1463
dpp3_construct(struct dcn3_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn3_dpp_registers * tf_regs,const struct dcn3_dpp_shift * tf_shift,const struct dcn3_dpp_mask * tf_mask)1464 bool dpp3_construct(
1465 struct dcn3_dpp *dpp,
1466 struct dc_context *ctx,
1467 uint32_t inst,
1468 const struct dcn3_dpp_registers *tf_regs,
1469 const struct dcn3_dpp_shift *tf_shift,
1470 const struct dcn3_dpp_mask *tf_mask)
1471 {
1472 dpp->base.ctx = ctx;
1473
1474 dpp->base.inst = inst;
1475 dpp->base.funcs = &dcn30_dpp_funcs;
1476 dpp->base.caps = &dcn30_dpp_cap;
1477
1478 dpp->tf_regs = tf_regs;
1479 dpp->tf_shift = tf_shift;
1480 dpp->tf_mask = tf_mask;
1481
1482 return true;
1483 }
1484
1485