1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * TI DaVinci GPIO Support
4  *
5  * Copyright (c) 2006-2007 David Brownell
6  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7  */
8 
9 #include <linux/gpio/driver.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/platform_data/gpio-davinci.h>
23 #include <linux/irqchip/chained_irq.h>
24 #include <linux/spinlock.h>
25 
26 #include <asm-generic/gpio.h>
27 
28 #define MAX_REGS_BANKS 5
29 #define MAX_INT_PER_BANK 32
30 
31 struct davinci_gpio_regs {
32 	u32	dir;
33 	u32	out_data;
34 	u32	set_data;
35 	u32	clr_data;
36 	u32	in_data;
37 	u32	set_rising;
38 	u32	clr_rising;
39 	u32	set_falling;
40 	u32	clr_falling;
41 	u32	intstat;
42 };
43 
44 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
45 
46 #define BINTEN	0x8 /* GPIO Interrupt Per-Bank Enable Register */
47 
48 static void __iomem *gpio_base;
49 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
50 
51 struct davinci_gpio_irq_data {
52 	void __iomem			*regs;
53 	struct davinci_gpio_controller	*chip;
54 	int				bank_num;
55 };
56 
57 struct davinci_gpio_controller {
58 	struct gpio_chip	chip;
59 	struct irq_domain	*irq_domain;
60 	/* Serialize access to GPIO registers */
61 	spinlock_t		lock;
62 	void __iomem		*regs[MAX_REGS_BANKS];
63 	int			gpio_unbanked;
64 	int			irqs[MAX_INT_PER_BANK];
65 };
66 
__gpio_mask(unsigned gpio)67 static inline u32 __gpio_mask(unsigned gpio)
68 {
69 	return 1 << (gpio % 32);
70 }
71 
irq2regs(struct irq_data * d)72 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
73 {
74 	struct davinci_gpio_regs __iomem *g;
75 
76 	g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
77 
78 	return g;
79 }
80 
81 static int davinci_gpio_irq_setup(struct platform_device *pdev);
82 
83 /*--------------------------------------------------------------------------*/
84 
85 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
__davinci_direction(struct gpio_chip * chip,unsigned offset,bool out,int value)86 static inline int __davinci_direction(struct gpio_chip *chip,
87 			unsigned offset, bool out, int value)
88 {
89 	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
90 	struct davinci_gpio_regs __iomem *g;
91 	unsigned long flags;
92 	u32 temp;
93 	int bank = offset / 32;
94 	u32 mask = __gpio_mask(offset);
95 
96 	g = d->regs[bank];
97 	spin_lock_irqsave(&d->lock, flags);
98 	temp = readl_relaxed(&g->dir);
99 	if (out) {
100 		temp &= ~mask;
101 		writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
102 	} else {
103 		temp |= mask;
104 	}
105 	writel_relaxed(temp, &g->dir);
106 	spin_unlock_irqrestore(&d->lock, flags);
107 
108 	return 0;
109 }
110 
davinci_direction_in(struct gpio_chip * chip,unsigned offset)111 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
112 {
113 	return __davinci_direction(chip, offset, false, 0);
114 }
115 
116 static int
davinci_direction_out(struct gpio_chip * chip,unsigned offset,int value)117 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
118 {
119 	return __davinci_direction(chip, offset, true, value);
120 }
121 
122 /*
123  * Read the pin's value (works even if it's set up as output);
124  * returns zero/nonzero.
125  *
126  * Note that changes are synched to the GPIO clock, so reading values back
127  * right after you've set them may give old values.
128  */
davinci_gpio_get(struct gpio_chip * chip,unsigned offset)129 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
130 {
131 	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
132 	struct davinci_gpio_regs __iomem *g;
133 	int bank = offset / 32;
134 
135 	g = d->regs[bank];
136 
137 	return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
138 }
139 
140 /*
141  * Assuming the pin is muxed as a gpio output, set its output value.
142  */
143 static void
davinci_gpio_set(struct gpio_chip * chip,unsigned offset,int value)144 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
145 {
146 	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
147 	struct davinci_gpio_regs __iomem *g;
148 	int bank = offset / 32;
149 
150 	g = d->regs[bank];
151 
152 	writel_relaxed(__gpio_mask(offset),
153 		       value ? &g->set_data : &g->clr_data);
154 }
155 
156 static struct davinci_gpio_platform_data *
davinci_gpio_get_pdata(struct platform_device * pdev)157 davinci_gpio_get_pdata(struct platform_device *pdev)
158 {
159 	struct device_node *dn = pdev->dev.of_node;
160 	struct davinci_gpio_platform_data *pdata;
161 	int ret;
162 	u32 val;
163 
164 	if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
165 		return dev_get_platdata(&pdev->dev);
166 
167 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
168 	if (!pdata)
169 		return NULL;
170 
171 	ret = of_property_read_u32(dn, "ti,ngpio", &val);
172 	if (ret)
173 		goto of_err;
174 
175 	pdata->ngpio = val;
176 
177 	ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
178 	if (ret)
179 		goto of_err;
180 
181 	pdata->gpio_unbanked = val;
182 
183 	return pdata;
184 
185 of_err:
186 	dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
187 	return NULL;
188 }
189 
davinci_gpio_probe(struct platform_device * pdev)190 static int davinci_gpio_probe(struct platform_device *pdev)
191 {
192 	int bank, i, ret = 0;
193 	unsigned int ngpio, nbank, nirq;
194 	struct davinci_gpio_controller *chips;
195 	struct davinci_gpio_platform_data *pdata;
196 	struct device *dev = &pdev->dev;
197 
198 	pdata = davinci_gpio_get_pdata(pdev);
199 	if (!pdata) {
200 		dev_err(dev, "No platform data found\n");
201 		return -EINVAL;
202 	}
203 
204 	dev->platform_data = pdata;
205 
206 	/*
207 	 * The gpio banks conceptually expose a segmented bitmap,
208 	 * and "ngpio" is one more than the largest zero-based
209 	 * bit index that's valid.
210 	 */
211 	ngpio = pdata->ngpio;
212 	if (ngpio == 0) {
213 		dev_err(dev, "How many GPIOs?\n");
214 		return -EINVAL;
215 	}
216 
217 	if (WARN_ON(ARCH_NR_GPIOS < ngpio))
218 		ngpio = ARCH_NR_GPIOS;
219 
220 	/*
221 	 * If there are unbanked interrupts then the number of
222 	 * interrupts is equal to number of gpios else all are banked so
223 	 * number of interrupts is equal to number of banks(each with 16 gpios)
224 	 */
225 	if (pdata->gpio_unbanked)
226 		nirq = pdata->gpio_unbanked;
227 	else
228 		nirq = DIV_ROUND_UP(ngpio, 16);
229 
230 	chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
231 	if (!chips)
232 		return -ENOMEM;
233 
234 	gpio_base = devm_platform_ioremap_resource(pdev, 0);
235 	if (IS_ERR(gpio_base))
236 		return PTR_ERR(gpio_base);
237 
238 	for (i = 0; i < nirq; i++) {
239 		chips->irqs[i] = platform_get_irq(pdev, i);
240 		if (chips->irqs[i] < 0)
241 			return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
242 	}
243 
244 	chips->chip.label = dev_name(dev);
245 
246 	chips->chip.direction_input = davinci_direction_in;
247 	chips->chip.get = davinci_gpio_get;
248 	chips->chip.direction_output = davinci_direction_out;
249 	chips->chip.set = davinci_gpio_set;
250 
251 	chips->chip.ngpio = ngpio;
252 	chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
253 
254 #ifdef CONFIG_OF_GPIO
255 	chips->chip.of_gpio_n_cells = 2;
256 	chips->chip.parent = dev;
257 	chips->chip.request = gpiochip_generic_request;
258 	chips->chip.free = gpiochip_generic_free;
259 #endif
260 	spin_lock_init(&chips->lock);
261 
262 	nbank = DIV_ROUND_UP(ngpio, 32);
263 	for (bank = 0; bank < nbank; bank++)
264 		chips->regs[bank] = gpio_base + offset_array[bank];
265 
266 	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
267 	if (ret)
268 		return ret;
269 
270 	platform_set_drvdata(pdev, chips);
271 	ret = davinci_gpio_irq_setup(pdev);
272 	if (ret)
273 		return ret;
274 
275 	return 0;
276 }
277 
278 /*--------------------------------------------------------------------------*/
279 /*
280  * We expect irqs will normally be set up as input pins, but they can also be
281  * used as output pins ... which is convenient for testing.
282  *
283  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
284  * to their GPIOBNK0 irq, with a bit less overhead.
285  *
286  * All those INTC hookups (direct, plus several IRQ banks) can also
287  * serve as EDMA event triggers.
288  */
289 
gpio_irq_disable(struct irq_data * d)290 static void gpio_irq_disable(struct irq_data *d)
291 {
292 	struct davinci_gpio_regs __iomem *g = irq2regs(d);
293 	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
294 
295 	writel_relaxed(mask, &g->clr_falling);
296 	writel_relaxed(mask, &g->clr_rising);
297 }
298 
gpio_irq_enable(struct irq_data * d)299 static void gpio_irq_enable(struct irq_data *d)
300 {
301 	struct davinci_gpio_regs __iomem *g = irq2regs(d);
302 	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
303 	unsigned status = irqd_get_trigger_type(d);
304 
305 	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
306 	if (!status)
307 		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
308 
309 	if (status & IRQ_TYPE_EDGE_FALLING)
310 		writel_relaxed(mask, &g->set_falling);
311 	if (status & IRQ_TYPE_EDGE_RISING)
312 		writel_relaxed(mask, &g->set_rising);
313 }
314 
gpio_irq_type(struct irq_data * d,unsigned trigger)315 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
316 {
317 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
318 		return -EINVAL;
319 
320 	return 0;
321 }
322 
323 static struct irq_chip gpio_irqchip = {
324 	.name		= "GPIO",
325 	.irq_enable	= gpio_irq_enable,
326 	.irq_disable	= gpio_irq_disable,
327 	.irq_set_type	= gpio_irq_type,
328 	.flags		= IRQCHIP_SET_TYPE_MASKED,
329 };
330 
gpio_irq_handler(struct irq_desc * desc)331 static void gpio_irq_handler(struct irq_desc *desc)
332 {
333 	struct davinci_gpio_regs __iomem *g;
334 	u32 mask = 0xffff;
335 	int bank_num;
336 	struct davinci_gpio_controller *d;
337 	struct davinci_gpio_irq_data *irqdata;
338 
339 	irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
340 	bank_num = irqdata->bank_num;
341 	g = irqdata->regs;
342 	d = irqdata->chip;
343 
344 	/* we only care about one bank */
345 	if ((bank_num % 2) == 1)
346 		mask <<= 16;
347 
348 	/* temporarily mask (level sensitive) parent IRQ */
349 	chained_irq_enter(irq_desc_get_chip(desc), desc);
350 	while (1) {
351 		u32		status;
352 		int		bit;
353 		irq_hw_number_t hw_irq;
354 
355 		/* ack any irqs */
356 		status = readl_relaxed(&g->intstat) & mask;
357 		if (!status)
358 			break;
359 		writel_relaxed(status, &g->intstat);
360 
361 		/* now demux them to the right lowlevel handler */
362 
363 		while (status) {
364 			bit = __ffs(status);
365 			status &= ~BIT(bit);
366 			/* Max number of gpios per controller is 144 so
367 			 * hw_irq will be in [0..143]
368 			 */
369 			hw_irq = (bank_num / 2) * 32 + bit;
370 
371 			generic_handle_domain_irq(d->irq_domain, hw_irq);
372 		}
373 	}
374 	chained_irq_exit(irq_desc_get_chip(desc), desc);
375 	/* now it may re-trigger */
376 }
377 
gpio_to_irq_banked(struct gpio_chip * chip,unsigned offset)378 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
379 {
380 	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
381 
382 	if (d->irq_domain)
383 		return irq_create_mapping(d->irq_domain, offset);
384 	else
385 		return -ENXIO;
386 }
387 
gpio_to_irq_unbanked(struct gpio_chip * chip,unsigned offset)388 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
389 {
390 	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
391 
392 	/*
393 	 * NOTE:  we assume for now that only irqs in the first gpio_chip
394 	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
395 	 */
396 	if (offset < d->gpio_unbanked)
397 		return d->irqs[offset];
398 	else
399 		return -ENODEV;
400 }
401 
gpio_irq_type_unbanked(struct irq_data * data,unsigned trigger)402 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
403 {
404 	struct davinci_gpio_controller *d;
405 	struct davinci_gpio_regs __iomem *g;
406 	u32 mask, i;
407 
408 	d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
409 	g = (struct davinci_gpio_regs __iomem *)d->regs[0];
410 	for (i = 0; i < MAX_INT_PER_BANK; i++)
411 		if (data->irq == d->irqs[i])
412 			break;
413 
414 	if (i == MAX_INT_PER_BANK)
415 		return -EINVAL;
416 
417 	mask = __gpio_mask(i);
418 
419 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
420 		return -EINVAL;
421 
422 	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
423 		     ? &g->set_falling : &g->clr_falling);
424 	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
425 		     ? &g->set_rising : &g->clr_rising);
426 
427 	return 0;
428 }
429 
430 static int
davinci_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)431 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
432 		     irq_hw_number_t hw)
433 {
434 	struct davinci_gpio_controller *chips =
435 				(struct davinci_gpio_controller *)d->host_data;
436 	struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
437 
438 	irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
439 				"davinci_gpio");
440 	irq_set_irq_type(irq, IRQ_TYPE_NONE);
441 	irq_set_chip_data(irq, (__force void *)g);
442 	irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
443 
444 	return 0;
445 }
446 
447 static const struct irq_domain_ops davinci_gpio_irq_ops = {
448 	.map = davinci_gpio_irq_map,
449 	.xlate = irq_domain_xlate_onetwocell,
450 };
451 
davinci_gpio_get_irq_chip(unsigned int irq)452 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
453 {
454 	static struct irq_chip_type gpio_unbanked;
455 
456 	gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
457 
458 	return &gpio_unbanked.chip;
459 };
460 
keystone_gpio_get_irq_chip(unsigned int irq)461 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
462 {
463 	static struct irq_chip gpio_unbanked;
464 
465 	gpio_unbanked = *irq_get_chip(irq);
466 	return &gpio_unbanked;
467 };
468 
469 static const struct of_device_id davinci_gpio_ids[];
470 
471 /*
472  * NOTE:  for suspend/resume, probably best to make a platform_device with
473  * suspend_late/resume_resume calls hooking into results of the set_wake()
474  * calls ... so if no gpios are wakeup events the clock can be disabled,
475  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
476  * (dm6446) can be set appropriately for GPIOV33 pins.
477  */
478 
davinci_gpio_irq_setup(struct platform_device * pdev)479 static int davinci_gpio_irq_setup(struct platform_device *pdev)
480 {
481 	unsigned	gpio, bank;
482 	int		irq;
483 	int		ret;
484 	struct clk	*clk;
485 	u32		binten = 0;
486 	unsigned	ngpio;
487 	struct device *dev = &pdev->dev;
488 	struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
489 	struct davinci_gpio_platform_data *pdata = dev->platform_data;
490 	struct davinci_gpio_regs __iomem *g;
491 	struct irq_domain	*irq_domain = NULL;
492 	const struct of_device_id *match;
493 	struct irq_chip *irq_chip;
494 	struct davinci_gpio_irq_data *irqdata;
495 	gpio_get_irq_chip_cb_t gpio_get_irq_chip;
496 
497 	/*
498 	 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
499 	 */
500 	gpio_get_irq_chip = davinci_gpio_get_irq_chip;
501 	match = of_match_device(of_match_ptr(davinci_gpio_ids),
502 				dev);
503 	if (match)
504 		gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
505 
506 	ngpio = pdata->ngpio;
507 
508 	clk = devm_clk_get(dev, "gpio");
509 	if (IS_ERR(clk)) {
510 		dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
511 		return PTR_ERR(clk);
512 	}
513 
514 	ret = clk_prepare_enable(clk);
515 	if (ret)
516 		return ret;
517 
518 	if (!pdata->gpio_unbanked) {
519 		irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
520 		if (irq < 0) {
521 			dev_err(dev, "Couldn't allocate IRQ numbers\n");
522 			clk_disable_unprepare(clk);
523 			return irq;
524 		}
525 
526 		irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
527 							&davinci_gpio_irq_ops,
528 							chips);
529 		if (!irq_domain) {
530 			dev_err(dev, "Couldn't register an IRQ domain\n");
531 			clk_disable_unprepare(clk);
532 			return -ENODEV;
533 		}
534 	}
535 
536 	/*
537 	 * Arrange gpio_to_irq() support, handling either direct IRQs or
538 	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
539 	 * IRQs, while the others use banked IRQs, would need some setup
540 	 * tweaks to recognize hardware which can do that.
541 	 */
542 	chips->chip.to_irq = gpio_to_irq_banked;
543 	chips->irq_domain = irq_domain;
544 
545 	/*
546 	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
547 	 * controller only handling trigger modes.  We currently assume no
548 	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
549 	 */
550 	if (pdata->gpio_unbanked) {
551 		/* pass "bank 0" GPIO IRQs to AINTC */
552 		chips->chip.to_irq = gpio_to_irq_unbanked;
553 		chips->gpio_unbanked = pdata->gpio_unbanked;
554 		binten = GENMASK(pdata->gpio_unbanked / 16, 0);
555 
556 		/* AINTC handles mask/unmask; GPIO handles triggering */
557 		irq = chips->irqs[0];
558 		irq_chip = gpio_get_irq_chip(irq);
559 		irq_chip->name = "GPIO-AINTC";
560 		irq_chip->irq_set_type = gpio_irq_type_unbanked;
561 
562 		/* default trigger: both edges */
563 		g = chips->regs[0];
564 		writel_relaxed(~0, &g->set_falling);
565 		writel_relaxed(~0, &g->set_rising);
566 
567 		/* set the direct IRQs up to use that irqchip */
568 		for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
569 			irq_set_chip(chips->irqs[gpio], irq_chip);
570 			irq_set_handler_data(chips->irqs[gpio], chips);
571 			irq_set_status_flags(chips->irqs[gpio],
572 					     IRQ_TYPE_EDGE_BOTH);
573 		}
574 
575 		goto done;
576 	}
577 
578 	/*
579 	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
580 	 * then chain through our own handler.
581 	 */
582 	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
583 		/* disabled by default, enabled only as needed
584 		 * There are register sets for 32 GPIOs. 2 banks of 16
585 		 * GPIOs are covered by each set of registers hence divide by 2
586 		 */
587 		g = chips->regs[bank / 2];
588 		writel_relaxed(~0, &g->clr_falling);
589 		writel_relaxed(~0, &g->clr_rising);
590 
591 		/*
592 		 * Each chip handles 32 gpios, and each irq bank consists of 16
593 		 * gpio irqs. Pass the irq bank's corresponding controller to
594 		 * the chained irq handler.
595 		 */
596 		irqdata = devm_kzalloc(&pdev->dev,
597 				       sizeof(struct
598 					      davinci_gpio_irq_data),
599 					      GFP_KERNEL);
600 		if (!irqdata) {
601 			clk_disable_unprepare(clk);
602 			return -ENOMEM;
603 		}
604 
605 		irqdata->regs = g;
606 		irqdata->bank_num = bank;
607 		irqdata->chip = chips;
608 
609 		irq_set_chained_handler_and_data(chips->irqs[bank],
610 						 gpio_irq_handler, irqdata);
611 
612 		binten |= BIT(bank);
613 	}
614 
615 done:
616 	/*
617 	 * BINTEN -- per-bank interrupt enable. genirq would also let these
618 	 * bits be set/cleared dynamically.
619 	 */
620 	writel_relaxed(binten, gpio_base + BINTEN);
621 
622 	return 0;
623 }
624 
625 static const struct of_device_id davinci_gpio_ids[] = {
626 	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
627 	{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
628 	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
629 	{ /* sentinel */ },
630 };
631 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
632 
633 static struct platform_driver davinci_gpio_driver = {
634 	.probe		= davinci_gpio_probe,
635 	.driver		= {
636 		.name		= "davinci_gpio",
637 		.of_match_table	= of_match_ptr(davinci_gpio_ids),
638 	},
639 };
640 
641 /**
642  * GPIO driver registration needs to be done before machine_init functions
643  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
644  */
davinci_gpio_drv_reg(void)645 static int __init davinci_gpio_drv_reg(void)
646 {
647 	return platform_driver_register(&davinci_gpio_driver);
648 }
649 postcore_initcall(davinci_gpio_drv_reg);
650