1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * SiFive FU540 Platform DMA driver
4  * Copyright (C) 2019 SiFive
5  *
6  * Based partially on:
7  * - drivers/dma/fsl-edma.c
8  * - drivers/dma/dw-edma/
9  * - drivers/dma/pxa-dma.c
10  *
11  * See the following sources for further documentation:
12  * - Chapter 12 "Platform DMA Engine (PDMA)" of
13  *   SiFive FU540-C000 v1.0
14  *   https://static.dev.sifive.com/FU540-C000-v1.0.pdf
15  */
16 #ifndef _SF_PDMA_H
17 #define _SF_PDMA_H
18 
19 #include <linux/dmaengine.h>
20 #include <linux/dma-direction.h>
21 
22 #include "../dmaengine.h"
23 #include "../virt-dma.h"
24 
25 #define PDMA_MAX_NR_CH					4
26 
27 #define PDMA_BASE_ADDR					0x3000000
28 #define PDMA_CHAN_OFFSET				0x1000
29 
30 /* Register Offset */
31 #define PDMA_CTRL					0x000
32 #define PDMA_XFER_TYPE					0x004
33 #define PDMA_XFER_SIZE					0x008
34 #define PDMA_DST_ADDR					0x010
35 #define PDMA_SRC_ADDR					0x018
36 #define PDMA_ACT_TYPE					0x104 /* Read-only */
37 #define PDMA_REMAINING_BYTE				0x108 /* Read-only */
38 #define PDMA_CUR_DST_ADDR				0x110 /* Read-only*/
39 #define PDMA_CUR_SRC_ADDR				0x118 /* Read-only*/
40 
41 /* CTRL */
42 #define PDMA_CLEAR_CTRL					0x0
43 #define PDMA_CLAIM_MASK					GENMASK(0, 0)
44 #define PDMA_RUN_MASK					GENMASK(1, 1)
45 #define PDMA_ENABLE_DONE_INT_MASK			GENMASK(14, 14)
46 #define PDMA_ENABLE_ERR_INT_MASK			GENMASK(15, 15)
47 #define PDMA_DONE_STATUS_MASK				GENMASK(30, 30)
48 #define PDMA_ERR_STATUS_MASK				GENMASK(31, 31)
49 
50 /* Transfer Type */
51 #define PDMA_FULL_SPEED					0xFF000008
52 
53 /* Error Recovery */
54 #define MAX_RETRY					1
55 
56 #define SF_PDMA_REG_BASE(ch)	(pdma->membase + (PDMA_CHAN_OFFSET * (ch)))
57 
58 struct pdma_regs {
59 	/* read-write regs */
60 	void __iomem *ctrl;		/* 4 bytes */
61 
62 	void __iomem *xfer_type;	/* 4 bytes */
63 	void __iomem *xfer_size;	/* 8 bytes */
64 	void __iomem *dst_addr;		/* 8 bytes */
65 	void __iomem *src_addr;		/* 8 bytes */
66 
67 	/* read-only */
68 	void __iomem *act_type;		/* 4 bytes */
69 	void __iomem *residue;		/* 8 bytes */
70 	void __iomem *cur_dst_addr;	/* 8 bytes */
71 	void __iomem *cur_src_addr;	/* 8 bytes */
72 };
73 
74 struct sf_pdma_desc {
75 	u32				xfer_type;
76 	u64				xfer_size;
77 	u64				dst_addr;
78 	u64				src_addr;
79 	struct virt_dma_desc		vdesc;
80 	struct sf_pdma_chan		*chan;
81 	bool				in_use;
82 	enum dma_transfer_direction	dirn;
83 	struct dma_async_tx_descriptor *async_tx;
84 };
85 
86 enum sf_pdma_pm_state {
87 	RUNNING = 0,
88 	SUSPENDED,
89 };
90 
91 struct sf_pdma_chan {
92 	struct virt_dma_chan		vchan;
93 	enum dma_status			status;
94 	enum sf_pdma_pm_state		pm_state;
95 	u32				slave_id;
96 	struct sf_pdma			*pdma;
97 	struct sf_pdma_desc		*desc;
98 	struct dma_slave_config		cfg;
99 	u32				attr;
100 	dma_addr_t			dma_dev_addr;
101 	u32				dma_dev_size;
102 	struct tasklet_struct		done_tasklet;
103 	struct tasklet_struct		err_tasklet;
104 	struct pdma_regs		regs;
105 	spinlock_t			lock; /* protect chan data */
106 	bool				xfer_err;
107 	int				txirq;
108 	int				errirq;
109 	int				retries;
110 };
111 
112 struct sf_pdma {
113 	struct dma_device       dma_dev;
114 	void __iomem            *membase;
115 	void __iomem            *mappedbase;
116 	u32			n_chans;
117 	struct sf_pdma_chan	chans[];
118 };
119 
120 #endif /* _SF_PDMA_H */
121