1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 *
5 * Common Clock Framework support for S3C2410 and following SoCs.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/clk/samsung.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12
13 #include <dt-bindings/clock/s3c2410.h>
14
15 #include "clk.h"
16 #include "clk-pll.h"
17
18 #define LOCKTIME 0x00
19 #define MPLLCON 0x04
20 #define UPLLCON 0x08
21 #define CLKCON 0x0c
22 #define CLKSLOW 0x10
23 #define CLKDIVN 0x14
24 #define CAMDIVN 0x18
25
26 /* the soc types */
27 enum supported_socs {
28 S3C2410,
29 S3C2440,
30 S3C2442,
31 };
32
33 /* list of PLLs to be registered */
34 enum s3c2410_plls {
35 mpll, upll,
36 };
37
38 static void __iomem *reg_base;
39
40 /*
41 * list of controller registers to be saved and restored during a
42 * suspend/resume cycle.
43 */
44 static unsigned long s3c2410_clk_regs[] __initdata = {
45 LOCKTIME,
46 MPLLCON,
47 UPLLCON,
48 CLKCON,
49 CLKSLOW,
50 CLKDIVN,
51 CAMDIVN,
52 };
53
54 PNAME(fclk_p) = { "mpll", "div_slow" };
55
56 static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
57 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
58 };
59
60 static struct clk_div_table divslow_d[] = {
61 { .val = 0, .div = 1 },
62 { .val = 1, .div = 2 },
63 { .val = 2, .div = 4 },
64 { .val = 3, .div = 6 },
65 { .val = 4, .div = 8 },
66 { .val = 5, .div = 10 },
67 { .val = 6, .div = 12 },
68 { .val = 7, .div = 14 },
69 { /* sentinel */ },
70 };
71
72 static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
73 DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
74 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
75 };
76
77 static struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
78 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
79 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
80 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
81 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
82 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
83 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
84 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
85 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
86 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
87 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
88 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
89 GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
90 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
91 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
92 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
93 };
94
95 /* should be added _after_ the soc-specific clocks are created */
96 static struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
97 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
98 ALIAS(PCLK_ADC, NULL, "adc"),
99 ALIAS(PCLK_RTC, NULL, "rtc"),
100 ALIAS(PCLK_PWM, NULL, "timers"),
101 ALIAS(HCLK_LCD, NULL, "lcd"),
102 ALIAS(HCLK_USBD, NULL, "usb-device"),
103 ALIAS(HCLK_USBH, NULL, "usb-host"),
104 ALIAS(UCLK, NULL, "usb-bus-host"),
105 ALIAS(UCLK, NULL, "usb-bus-gadget"),
106 ALIAS(ARMCLK, NULL, "armclk"),
107 ALIAS(UCLK, NULL, "uclk"),
108 ALIAS(HCLK, NULL, "hclk"),
109 ALIAS(MPLL, NULL, "mpll"),
110 ALIAS(FCLK, NULL, "fclk"),
111 ALIAS(PCLK, NULL, "watchdog"),
112 ALIAS(PCLK_SDI, NULL, "sdi"),
113 ALIAS(HCLK_NAND, NULL, "nand"),
114 ALIAS(PCLK_I2S, NULL, "iis"),
115 ALIAS(PCLK_I2C, NULL, "i2c"),
116 };
117
118 /* S3C2410 specific clocks */
119
120 static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
121 /* sorted in descending order */
122 /* 2410A extras */
123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
128 /* 2410 common */
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
132 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
133 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
134 PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
135 PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
136 PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
137 PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
138 PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
139 PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
140 PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
141 PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
142 PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
143 PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
144 PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
145 PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
146 PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
147 PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
148 PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
149 PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
150 PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
151 { /* sentinel */ },
152 };
153
154 static struct samsung_pll_clock s3c2410_plls[] __initdata = {
155 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
156 LOCKTIME, MPLLCON, NULL),
157 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
158 LOCKTIME, UPLLCON, NULL),
159 };
160
161 static struct samsung_div_clock s3c2410_dividers[] __initdata = {
162 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
163 };
164
165 static struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
166 /*
167 * armclk is directly supplied by the fclk, without
168 * switching possibility like on the s3c244x below.
169 */
170 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
171
172 /* uclk is fed from the unmodified upll */
173 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
174 };
175
176 static struct samsung_clock_alias s3c2410_aliases[] __initdata = {
177 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
178 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
179 ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
180 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
181 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
182 ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
183 ALIAS(UCLK, NULL, "clk_uart_baud1"),
184 };
185
186 /* S3C244x specific clocks */
187
188 static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
189 /* sorted in descending order */
190 PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
191 PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
192 PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
193 PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
194 PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
195 PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
196 PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
197 PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
198 PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
199 PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
200 PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
201 PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
202 PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
203 PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
204 PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
205 PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
206 PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
207 PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
208 PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
209 PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
210 PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
211 PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
212 PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
213 PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
214 PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
215 PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
216 PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
217 { /* sentinel */ },
218 };
219
220 static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
221 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
222 LOCKTIME, MPLLCON, NULL),
223 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
224 LOCKTIME, UPLLCON, NULL),
225 };
226
227 PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
228 PNAME(armclk_p) = { "fclk", "hclk" };
229
230 static struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
231 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
232 MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
233 };
234
235 static struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
236 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
237 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
238 };
239
240 static struct clk_div_table div_hclk_4_d[] = {
241 { .val = 0, .div = 4 },
242 { .val = 1, .div = 8 },
243 { /* sentinel */ },
244 };
245
246 static struct clk_div_table div_hclk_3_d[] = {
247 { .val = 0, .div = 3 },
248 { .val = 1, .div = 6 },
249 { /* sentinel */ },
250 };
251
252 static struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
253 DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
254 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
255 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
256 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
257 DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
258 };
259
260 static struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
261 GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
262 };
263
264 static struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
265 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
266 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
267 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
268 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
269 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
270 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
271 ALIAS(HCLK_CAM, NULL, "camif"),
272 ALIAS(CAMIF, NULL, "camif-upll"),
273 };
274
275 /* S3C2440 specific clocks */
276
277 PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
278
279 static struct samsung_mux_clock s3c2440_muxes[] __initdata = {
280 MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
281 };
282
283 static struct samsung_gate_clock s3c2440_gates[] __initdata = {
284 GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
285 };
286
287 /* S3C2442 specific clocks */
288
289 static struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
290 FFACTOR(0, "upll_3", "upll", 1, 3, 0),
291 };
292
293 PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
294
295 static struct samsung_mux_clock s3c2442_muxes[] __initdata = {
296 MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
297 };
298
299 /*
300 * fixed rate clocks generated outside the soc
301 * Only necessary until the devicetree-move is complete
302 */
303 #define XTI 1
304 static struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
305 FRATE(XTI, "xti", NULL, 0, 0),
306 };
307
s3c2410_common_clk_register_fixed_ext(struct samsung_clk_provider * ctx,unsigned long xti_f)308 static void __init s3c2410_common_clk_register_fixed_ext(
309 struct samsung_clk_provider *ctx,
310 unsigned long xti_f)
311 {
312 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
313
314 s3c2410_common_frate_clks[0].fixed_rate = xti_f;
315 samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
316 ARRAY_SIZE(s3c2410_common_frate_clks));
317
318 samsung_clk_register_alias(ctx, &xti_alias, 1);
319 }
320
s3c2410_common_clk_init(struct device_node * np,unsigned long xti_f,int current_soc,void __iomem * base)321 void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
322 int current_soc,
323 void __iomem *base)
324 {
325 struct samsung_clk_provider *ctx;
326 struct clk_hw **hws;
327 reg_base = base;
328
329 if (np) {
330 reg_base = of_iomap(np, 0);
331 if (!reg_base)
332 panic("%s: failed to map registers\n", __func__);
333 }
334
335 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
336 hws = ctx->clk_data.hws;
337
338 /* Register external clocks only in non-dt cases */
339 if (!np)
340 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
341
342 if (current_soc == S3C2410) {
343 if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
344 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
345 s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
346 }
347
348 /* Register PLLs. */
349 samsung_clk_register_pll(ctx, s3c2410_plls,
350 ARRAY_SIZE(s3c2410_plls), reg_base);
351
352 } else { /* S3C2440, S3C2442 */
353 if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
354 /*
355 * plls follow different calculation schemes, with the
356 * upll following the same scheme as the s3c2410 plls
357 */
358 s3c244x_common_plls[mpll].rate_table =
359 pll_s3c244x_12mhz_tbl;
360 s3c244x_common_plls[upll].rate_table =
361 pll_s3c2410_12mhz_tbl;
362 }
363
364 /* Register PLLs. */
365 samsung_clk_register_pll(ctx, s3c244x_common_plls,
366 ARRAY_SIZE(s3c244x_common_plls), reg_base);
367 }
368
369 /* Register common internal clocks. */
370 samsung_clk_register_mux(ctx, s3c2410_common_muxes,
371 ARRAY_SIZE(s3c2410_common_muxes));
372 samsung_clk_register_div(ctx, s3c2410_common_dividers,
373 ARRAY_SIZE(s3c2410_common_dividers));
374 samsung_clk_register_gate(ctx, s3c2410_common_gates,
375 ARRAY_SIZE(s3c2410_common_gates));
376
377 if (current_soc == S3C2440 || current_soc == S3C2442) {
378 samsung_clk_register_div(ctx, s3c244x_common_dividers,
379 ARRAY_SIZE(s3c244x_common_dividers));
380 samsung_clk_register_gate(ctx, s3c244x_common_gates,
381 ARRAY_SIZE(s3c244x_common_gates));
382 samsung_clk_register_mux(ctx, s3c244x_common_muxes,
383 ARRAY_SIZE(s3c244x_common_muxes));
384 samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
385 ARRAY_SIZE(s3c244x_common_ffactor));
386 }
387
388 /* Register SoC-specific clocks. */
389 switch (current_soc) {
390 case S3C2410:
391 samsung_clk_register_div(ctx, s3c2410_dividers,
392 ARRAY_SIZE(s3c2410_dividers));
393 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
394 ARRAY_SIZE(s3c2410_ffactor));
395 samsung_clk_register_alias(ctx, s3c2410_aliases,
396 ARRAY_SIZE(s3c2410_aliases));
397 break;
398 case S3C2440:
399 samsung_clk_register_mux(ctx, s3c2440_muxes,
400 ARRAY_SIZE(s3c2440_muxes));
401 samsung_clk_register_gate(ctx, s3c2440_gates,
402 ARRAY_SIZE(s3c2440_gates));
403 break;
404 case S3C2442:
405 samsung_clk_register_mux(ctx, s3c2442_muxes,
406 ARRAY_SIZE(s3c2442_muxes));
407 samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
408 ARRAY_SIZE(s3c2442_ffactor));
409 break;
410 }
411
412 /*
413 * Register common aliases at the end, as some of the aliased clocks
414 * are SoC specific.
415 */
416 samsung_clk_register_alias(ctx, s3c2410_common_aliases,
417 ARRAY_SIZE(s3c2410_common_aliases));
418
419 if (current_soc == S3C2440 || current_soc == S3C2442) {
420 samsung_clk_register_alias(ctx, s3c244x_common_aliases,
421 ARRAY_SIZE(s3c244x_common_aliases));
422 }
423
424 samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
425 ARRAY_SIZE(s3c2410_clk_regs));
426
427 samsung_clk_of_add_provider(np, ctx);
428 }
429
s3c2410_clk_init(struct device_node * np)430 static void __init s3c2410_clk_init(struct device_node *np)
431 {
432 s3c2410_common_clk_init(np, 0, S3C2410, NULL);
433 }
434 CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
435
s3c2440_clk_init(struct device_node * np)436 static void __init s3c2440_clk_init(struct device_node *np)
437 {
438 s3c2410_common_clk_init(np, 0, S3C2440, NULL);
439 }
440 CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
441
s3c2442_clk_init(struct device_node * np)442 static void __init s3c2442_clk_init(struct device_node *np)
443 {
444 s3c2410_common_clk_init(np, 0, S3C2442, NULL);
445 }
446 CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);
447