1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022 Samsung Electronics Co., Ltd.
4 * Author: Chanho Park <chanho61.park@samsung.com>
5 *
6 * Common Clock Framework support for ExynosAuto V9 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15
16 #include <dt-bindings/clock/samsung,exynosautov9.h>
17
18 #include "clk.h"
19 #include "clk-exynos-arm64.h"
20
21 /* ---- CMU_TOP ------------------------------------------------------------ */
22
23 /* Register Offset definitions for CMU_TOP (0x1b240000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
25 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
26 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
27 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
28 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
29 #define PLL_CON0_PLL_SHARED0 0x0100
30 #define PLL_CON3_PLL_SHARED0 0x010c
31 #define PLL_CON0_PLL_SHARED1 0x0140
32 #define PLL_CON3_PLL_SHARED1 0x014c
33 #define PLL_CON0_PLL_SHARED2 0x0180
34 #define PLL_CON3_PLL_SHARED2 0x018c
35 #define PLL_CON0_PLL_SHARED3 0x01c0
36 #define PLL_CON3_PLL_SHARED3 0x01cc
37 #define PLL_CON0_PLL_SHARED4 0x0200
38 #define PLL_CON3_PLL_SHARED4 0x020c
39
40 /* MUX */
41 #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000
42 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
43 #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008
44 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c
45 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010
46 #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018
47 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c
48 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020
49 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
50 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
51 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
52 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
53 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040
54 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
55 #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048
56 #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c
57 #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050
58 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054
59 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058
60 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c
61 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060
62 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
63 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068
64 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c
65 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070
66 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074
67 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078
68 #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
69 #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
70 #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084
71 #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c
72 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090
73 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094
74 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
75 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098
76 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
77 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0
78 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4
79 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8
80 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac
81 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0
82 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4
83 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0
84
85 /* DIV */
86 #define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800
87 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
88 #define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808
89 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c
90 #define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810
91 #define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818
92 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
93 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
94 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
95 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
96 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
97 #define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c
98 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
99 #define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844
100 #define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848
101 #define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c
102 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850
103 #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854
104 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858
105 #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c
106 #define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860
107 #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864
108 #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868
109 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c
110 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870
111 #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874
112 #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878
113 #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c
114 #define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884
115 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888
116 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c
117 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890
118 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894
119 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898
120 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c
121 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0
122 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4
123 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8
124 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4
125
126 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8
127 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc
128 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0
129 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4
130 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8
131 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc
132 #define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0
133 #define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4
134 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4
135 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8
136
137 /* GATE */
138 #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000
139 #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004
140 #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008
141 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
142 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
143 #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020
144 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024
145 #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028
146 #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c
147 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030
148 #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034
149 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038
150 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c
151 #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044
152 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048
153 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c
154 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050
155 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058
156 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c
157 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060
158 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c
159 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070
160 #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060
161 #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064
162 #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c
163 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080
164 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084
165 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088
166 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c
167 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090
168 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094
169 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098
170 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c
171 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0
172 #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4
173 #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8
174 #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
175 #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4
176 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8
177 #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc
178 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0
179 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4
180 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8
181 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc
182 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0
183 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4
184 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8
185
186 static const unsigned long top_clk_regs[] __initconst = {
187 PLL_LOCKTIME_PLL_SHARED0,
188 PLL_LOCKTIME_PLL_SHARED1,
189 PLL_LOCKTIME_PLL_SHARED2,
190 PLL_LOCKTIME_PLL_SHARED3,
191 PLL_LOCKTIME_PLL_SHARED4,
192 PLL_CON0_PLL_SHARED0,
193 PLL_CON3_PLL_SHARED0,
194 PLL_CON0_PLL_SHARED1,
195 PLL_CON3_PLL_SHARED1,
196 PLL_CON0_PLL_SHARED2,
197 PLL_CON3_PLL_SHARED2,
198 PLL_CON0_PLL_SHARED3,
199 PLL_CON3_PLL_SHARED3,
200 PLL_CON0_PLL_SHARED4,
201 PLL_CON3_PLL_SHARED4,
202 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS,
203 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
204 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS,
205 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
206 CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
207 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
208 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
209 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
210 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
211 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
212 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
213 CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS,
214 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
215 CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS,
216 CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS,
217 CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS,
218 CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
219 CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE,
220 CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
221 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
222 CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
223 CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS,
224 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET,
225 CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
226 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
227 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
228 CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
229 CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
230 CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
231 CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS,
232 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
233 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
234 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
235 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
236 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
237 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
238 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
239 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
240 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
241 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
242 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
243 CLK_CON_MUX_MUX_CMU_CMUREF,
244 CLK_CON_DIV_CLKCMU_ACC_BUS,
245 CLK_CON_DIV_CLKCMU_APM_BUS,
246 CLK_CON_DIV_CLKCMU_AUD_BUS,
247 CLK_CON_DIV_CLKCMU_AUD_CPU,
248 CLK_CON_DIV_CLKCMU_BUSC_BUS,
249 CLK_CON_DIV_CLKCMU_BUSMC_BUS,
250 CLK_CON_DIV_CLKCMU_CORE_BUS,
251 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
252 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
253 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
254 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
255 CLK_CON_DIV_CLKCMU_DPTX_BUS,
256 CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
257 CLK_CON_DIV_CLKCMU_DPUM_BUS,
258 CLK_CON_DIV_CLKCMU_DPUS0_BUS,
259 CLK_CON_DIV_CLKCMU_DPUS1_BUS,
260 CLK_CON_DIV_CLKCMU_FSYS0_BUS,
261 CLK_CON_DIV_CLKCMU_FSYS0_PCIE,
262 CLK_CON_DIV_CLKCMU_FSYS1_BUS,
263 CLK_CON_DIV_CLKCMU_FSYS1_USBDRD,
264 CLK_CON_DIV_CLKCMU_FSYS2_BUS,
265 CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
266 CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
267 CLK_CON_DIV_CLKCMU_G2D_G2D,
268 CLK_CON_DIV_CLKCMU_G2D_MSCL,
269 CLK_CON_DIV_CLKCMU_G3D00_SWITCH,
270 CLK_CON_DIV_CLKCMU_G3D01_SWITCH,
271 CLK_CON_DIV_CLKCMU_G3D1_SWITCH,
272 CLK_CON_DIV_CLKCMU_ISPB_BUS,
273 CLK_CON_DIV_CLKCMU_MFC_MFC,
274 CLK_CON_DIV_CLKCMU_MFC_WFD,
275 CLK_CON_DIV_CLKCMU_MIF_BUSP,
276 CLK_CON_DIV_CLKCMU_NPU_BUS,
277 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
278 CLK_CON_DIV_CLKCMU_PERIC0_IP,
279 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
280 CLK_CON_DIV_CLKCMU_PERIC1_IP,
281 CLK_CON_DIV_CLKCMU_PERIS_BUS,
282 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
283 CLK_CON_DIV_PLL_SHARED0_DIV2,
284 CLK_CON_DIV_PLL_SHARED0_DIV3,
285 CLK_CON_DIV_PLL_SHARED1_DIV2,
286 CLK_CON_DIV_PLL_SHARED1_DIV3,
287 CLK_CON_DIV_PLL_SHARED1_DIV4,
288 CLK_CON_DIV_PLL_SHARED2_DIV2,
289 CLK_CON_DIV_PLL_SHARED2_DIV3,
290 CLK_CON_DIV_PLL_SHARED2_DIV4,
291 CLK_CON_DIV_PLL_SHARED4_DIV2,
292 CLK_CON_DIV_PLL_SHARED4_DIV4,
293 CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST,
294 CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST,
295 CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST,
296 CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST,
297 CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST,
298 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST,
299 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
300 CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
301 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS,
302 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
303 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS,
304 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
305 CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
306 CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS,
307 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
308 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
309 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER,
310 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
311 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER,
312 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
313 CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
314 CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
315 CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
316 CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
317 CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
318 CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
319 CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
320 CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
321 CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
322 CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
323 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET,
324 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD,
325 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
326 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
327 CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
328 CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
329 CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
330 CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
331 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
332 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
333 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
334 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
335 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
336 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
337 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
338 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
339 CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
340 };
341
342 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
343 /* CMU_TOP_PURECLKCOMP */
344 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
345 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
346 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
347 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
348 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
349 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
350 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
351 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
352 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
353 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
354 };
355
356 /* List of parent clocks for Muxes in CMU_TOP */
357 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
358 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
359 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
360 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
361 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
362
363 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
364 "dout_shared2_div4", "dout_shared4_div4" };
365 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
366 PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
367 "dout_shared1_div4", "dout_shared2_div4" };
368 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
369 "dout_shared2_div4", "dout_shared4_div4" };
370 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
371 "dout_shared2_div2", "dout_shared0_div3",
372 "dout_shared4_div2", "dout_shared1_div3",
373 "fout_shared3_pll" };
374 PNAME(mout_clkcmu_aud_bus_p) = { "dout_shared4_div2", "dout_shared1_div3",
375 "dout_shared2_div3", "dout_shared1_div4" };
376 PNAME(mout_clkcmu_busc_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
377 "dout_shared2_div4", "dout_shared4_div4" };
378 PNAME(mout_clkcmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
379 "dout_shared2_div2", "dout_shared0_div3",
380 "dout_shared4_div2", "dout_shared1_div3",
381 "dout_shared2_div3", "fout_shared3_pll" };
382 PNAME(mout_clkcmu_cpucl0_switch_p) = {
383 "dout_shared0_div2", "dout_shared1_div2",
384 "dout_shared2_div2", "dout_shared4_div2" };
385 PNAME(mout_clkcmu_cpucl0_cluster_p) = {
386 "fout_shared2_pll", "fout_shared4_pll",
387 "dout_shared0_div2", "dout_shared1_div2",
388 "dout_shared2_div2", "dout_shared4_div2",
389 "dout_shared2_div3", "fout_shared3_pll" };
390 PNAME(mout_clkcmu_dptx_bus_p) = { "dout_shared4_div2", "dout_shared2_div3",
391 "dout_shared1_div4", "dout_shared2_div4" };
392 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
393 "dout_shared2_div4", "dout_shared4_div4" };
394 PNAME(mout_clkcmu_dpum_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
395 "dout_shared1_div4", "dout_shared2_div4",
396 "dout_shared4_div4", "fout_shared3_pll" };
397 PNAME(mout_clkcmu_fsys0_bus_p) = {
398 "dout_shared4_div2", "dout_shared2_div3",
399 "dout_shared1_div4", "dout_shared2_div4" };
400 PNAME(mout_clkcmu_fsys0_pcie_p) = { "oscclk", "dout_shared2_div4" };
401 PNAME(mout_clkcmu_fsys1_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
402 "dout_shared2_div4", "dout_shared4_div4" };
403 PNAME(mout_clkcmu_fsys1_usbdrd_p) = {
404 "oscclk", "dout_shared2_div3",
405 "dout_shared2_div4", "dout_shared4_div4" };
406 PNAME(mout_clkcmu_fsys1_mmc_card_p) = {
407 "oscclk", "dout_shared2_div2",
408 "dout_shared4_div2", "dout_shared2_div3" };
409 PNAME(mout_clkcmu_fsys2_ethernet_p) = {
410 "oscclk", "dout_shared2_div2",
411 "dout_shared0_div3", "dout_shared2_div3",
412 "dout_shared1_div4", "fout_shared3_pll" };
413 PNAME(mout_clkcmu_g2d_g2d_p) = { "dout_shared2_div2", "dout_shared0_div3",
414 "dout_shared4_div2", "dout_shared1_div3",
415 "dout_shared2_div3", "dout_shared1_div4",
416 "dout_shared2_div4", "dout_shared4_div4" };
417 PNAME(mout_clkcmu_g3d0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
418 "dout_shared2_div2", "dout_shared4_div2" };
419 PNAME(mout_clkcmu_g3d1_switch_p) = { "dout_shared2_div2", "dout_shared4_div2",
420 "dout_shared2_div3", "dout_shared1_div4" };
421 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
422 "fout_shared2_pll", "fout_shared4_pll",
423 "dout_shared0_div2", "dout_shared1_div2",
424 "dout_shared2_div2", "fout_shared3_pll" };
425 PNAME(mout_clkcmu_npu_bus_p) = { "dout_shared1_div2", "dout_shared2_div2",
426 "dout_shared0_div3", "dout_shared4_div2",
427 "dout_shared1_div3", "dout_shared2_div3",
428 "dout_shared1_div4", "fout_shared3_pll" };
429 PNAME(mout_clkcmu_peric0_bus_p) = { "dout_shared2_div3", "dout_shared2_div4" };
430
431 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
432 /* CMU_TOP_PURECLKCOMP */
433 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
434 PLL_CON0_PLL_SHARED0, 4, 1),
435 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
436 PLL_CON0_PLL_SHARED1, 4, 1),
437 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
438 PLL_CON0_PLL_SHARED2, 4, 1),
439 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
440 PLL_CON0_PLL_SHARED3, 4, 1),
441 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
442 PLL_CON0_PLL_SHARED4, 4, 1),
443
444 /* BOOST */
445 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
446 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
447 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
448 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
449
450 /* ACC */
451 MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p,
452 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
453
454 /* APM */
455 MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p,
456 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
457
458 /* AUD */
459 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p,
460 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
461 MUX(MOUT_CLKCMU_AUD_BUS, "mout_clkcmu_aud_bus", mout_clkcmu_aud_bus_p,
462 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
463
464 /* BUSC */
465 MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus",
466 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
467
468 /* BUSMC */
469 MUX(MOUT_CLKCMU_BUSMC_BUS, "mout_clkcmu_busmc_bus",
470 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
471
472 /* CORE */
473 MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus",
474 mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
475
476 /* CPUCL0 */
477 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
478 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
479 0, 2),
480 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
481 mout_clkcmu_cpucl0_cluster_p,
482 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
483
484 /* CPUCL1 */
485 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
486 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
487 0, 2),
488 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
489 mout_clkcmu_cpucl0_cluster_p,
490 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
491
492 /* DPTX */
493 MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus",
494 mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
495 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
496 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
497
498 /* DPUM */
499 MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus",
500 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
501
502 /* DPUS */
503 MUX(MOUT_CLKCMU_DPUS0_BUS, "mout_clkcmu_dpus0_bus",
504 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
505 MUX(MOUT_CLKCMU_DPUS1_BUS, "mout_clkcmu_dpus1_bus",
506 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
507
508 /* FSYS0 */
509 MUX(MOUT_CLKCMU_FSYS0_BUS, "mout_clkcmu_fsys0_bus",
510 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
511 MUX(MOUT_CLKCMU_FSYS0_PCIE, "mout_clkcmu_fsys0_pcie",
512 mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
513
514 /* FSYS1 */
515 MUX(MOUT_CLKCMU_FSYS1_BUS, "mout_clkcmu_fsys1_bus",
516 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
517 MUX(MOUT_CLKCMU_FSYS1_USBDRD, "mout_clkcmu_fsys1_usbdrd",
518 mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
519 0, 2),
520 MUX(MOUT_CLKCMU_FSYS1_MMC_CARD, "mout_clkcmu_fsys1_mmc_card",
521 mout_clkcmu_fsys1_mmc_card_p,
522 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
523
524 /* FSYS2 */
525 MUX(MOUT_CLKCMU_FSYS2_BUS, "mout_clkcmu_fsys2_bus",
526 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
527 MUX(MOUT_CLKCMU_FSYS2_UFS_EMBD, "mout_clkcmu_fsys2_ufs_embd",
528 mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
529 0, 2),
530 MUX(MOUT_CLKCMU_FSYS2_ETHERNET, "mout_clkcmu_fsys2_ethernet",
531 mout_clkcmu_fsys2_ethernet_p,
532 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
533
534 /* G2D */
535 MUX(MOUT_CLKCMU_G2D_G2D, "mout_clkcmu_g2d_g2d", mout_clkcmu_g2d_g2d_p,
536 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
537 MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl",
538 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
539
540 /* G3D0 */
541 MUX(MOUT_CLKCMU_G3D00_SWITCH, "mout_clkcmu_g3d00_switch",
542 mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
543 0, 2),
544 MUX(MOUT_CLKCMU_G3D01_SWITCH, "mout_clkcmu_g3d01_switch",
545 mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
546 0, 2),
547
548 /* G3D1 */
549 MUX(MOUT_CLKCMU_G3D1_SWITCH, "mout_clkcmu_g3d1_switch",
550 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
551 0, 2),
552
553 /* ISPB */
554 MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus",
555 mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
556
557 /* MFC */
558 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
559 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
560 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
561 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
562
563 /* MIF */
564 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
565 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
566 MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp",
567 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
568
569 /* NPU */
570 MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p,
571 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
572
573 /* PERIC0 */
574 MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus",
575 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
576 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
577 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
578
579 /* PERIC1 */
580 MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus",
581 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
582 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
583 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
584
585 /* PERIS */
586 MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus",
587 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
588 };
589
590 static const struct samsung_div_clock top_div_clks[] __initconst = {
591 /* CMU_TOP_PURECLKCOMP */
592 DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
593 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
594 DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
595 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
596
597 DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
598 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
599 DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
600 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
601 DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
602 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
603
604 DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll",
605 CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
606 DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
607 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
608 DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2",
609 CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
610
611 DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll",
612 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
613 DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2",
614 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
615
616 /* BOOST */
617 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
618 "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
619
620 /* ACC */
621 DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus",
622 CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
623
624 /* APM */
625 DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus",
626 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
627
628 /* AUD */
629 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu",
630 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
631 DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus",
632 CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
633
634 /* BUSC */
635 DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus",
636 "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
637
638 /* BUSMC */
639 DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus",
640 "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
641
642 /* CORE */
643 DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus",
644 "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
645
646 /* CPUCL0 */
647 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
648 "gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
649 0, 3),
650 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
651 "gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
652 0, 3),
653
654 /* CPUCL1 */
655 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
656 "gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
657 0, 3),
658 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
659 "gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
660 0, 3),
661
662 /* DPTX */
663 DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus",
664 "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
665 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
666 "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
667
668 /* DPUM */
669 DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus",
670 "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
671
672 /* DPUS */
673 DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus",
674 "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
675 DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus",
676 "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
677
678 /* FSYS0 */
679 DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
680 "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
681
682 /* FSYS1 */
683 DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
684 "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
685 DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd",
686 "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
687
688 /* FSYS2 */
689 DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus",
690 "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
691 DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd",
692 "gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
693 0, 3),
694 DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet",
695 "gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
696 0, 3),
697
698 /* G2D */
699 DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d",
700 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
701 DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl",
702 "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
703
704 /* G3D0 */
705 DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch",
706 "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
707 DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch",
708 "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
709
710 /* G3D1 */
711 DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch",
712 "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
713
714 /* ISPB */
715 DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus",
716 "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
717
718 /* MFC */
719 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc",
720 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
721 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd",
722 CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
723
724 /* MIF */
725 DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
726 "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
727
728 /* NPU */
729 DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus",
730 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
731
732 /* PERIC0 */
733 DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus",
734 "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
735 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
736 "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
737
738 /* PERIC1 */
739 DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus",
740 "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
741 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
742 "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
743
744 /* PERIS */
745 DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus",
746 "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
747 };
748
749 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
750 FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie",
751 "gout_clkcmu_fsys0_pcie", 1, 4, 0),
752 };
753
754 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
755 /* BOOST */
756 GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost",
757 "mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
758 21, 0, 0),
759
760 GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost",
761 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
762 GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost",
763 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
764 GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost",
765 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
766 GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost",
767 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
768
769 GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost",
770 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
771 GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost",
772 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
773
774 /* ACC */
775 GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus",
776 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
777
778 /* APM */
779 GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus",
780 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
781
782 /* AUD */
783 GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu",
784 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
785 GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus",
786 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
787
788 /* BUSC */
789 GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus",
790 "mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21,
791 CLK_IS_CRITICAL, 0),
792
793 /* BUSMC */
794 GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus",
795 "mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21,
796 CLK_IS_CRITICAL, 0),
797
798 /* CORE */
799 GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus",
800 "mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
801 21, 0, 0),
802
803 /* CPUCL0 */
804 GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch",
805 "mout_clkcmu_cpucl0_switch",
806 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
807 GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster",
808 "mout_clkcmu_cpucl0_cluster",
809 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
810
811 /* CPUCL1 */
812 GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch",
813 "mout_clkcmu_cpucl1_switch",
814 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
815 GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster",
816 "mout_clkcmu_cpucl1_cluster",
817 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
818
819 /* DPTX */
820 GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus",
821 "mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
822 21, 0, 0),
823 GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc",
824 "mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
825 21, 0, 0),
826
827 /* DPUM */
828 GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus",
829 "mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
830 21, 0, 0),
831
832 /* DPUS */
833 GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus",
834 "mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
835 21, 0, 0),
836 GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus",
837 "mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
838 21, 0, 0),
839
840 /* FSYS0 */
841 GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus",
842 "mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
843 21, 0, 0),
844 GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie",
845 "mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
846 21, 0, 0),
847
848 /* FSYS1 */
849 GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus",
850 "mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
851 21, 0, 0),
852 GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd",
853 "mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
854 21, 0, 0),
855 GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card",
856 "mout_clkcmu_fsys1_mmc_card",
857 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
858
859 /* FSYS2 */
860 GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus",
861 "mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
862 21, 0, 0),
863 GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd",
864 "mout_clkcmu_fsys2_ufs_embd",
865 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
866 GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet",
867 "mout_clkcmu_fsys2_ethernet",
868 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
869
870 /* G2D */
871 GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d",
872 "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
873 GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl",
874 "mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
875 21, 0, 0),
876
877 /* G3D0 */
878 GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch",
879 "mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
880 21, 0, 0),
881 GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch",
882 "mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
883 21, 0, 0),
884
885 /* G3D1 */
886 GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch",
887 "mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
888 21, 0, 0),
889
890 /* ISPB */
891 GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus",
892 "mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
893 21, 0, 0),
894
895 /* MFC */
896 GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc",
897 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
898 GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd",
899 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
900
901 /* MIF */
902 GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch",
903 "mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
904 21, CLK_IGNORE_UNUSED, 0),
905 GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp",
906 "mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
907 21, CLK_IGNORE_UNUSED, 0),
908
909 /* NPU */
910 GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus",
911 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
912
913 /* PERIC0 */
914 GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus",
915 "mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
916 21, 0, 0),
917 GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip",
918 "mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
919 21, 0, 0),
920
921 /* PERIC1 */
922 GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus",
923 "mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
924 21, 0, 0),
925 GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip",
926 "mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
927 21, 0, 0),
928
929 /* PERIS */
930 GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus",
931 "mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
932 21, CLK_IGNORE_UNUSED, 0),
933 };
934
935 static const struct samsung_cmu_info top_cmu_info __initconst = {
936 .pll_clks = top_pll_clks,
937 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
938 .mux_clks = top_mux_clks,
939 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
940 .div_clks = top_div_clks,
941 .nr_div_clks = ARRAY_SIZE(top_div_clks),
942 .fixed_factor_clks = top_fixed_factor_clks,
943 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
944 .gate_clks = top_gate_clks,
945 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
946 .nr_clk_ids = TOP_NR_CLK,
947 .clk_regs = top_clk_regs,
948 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
949 };
950
exynosautov9_cmu_top_init(struct device_node * np)951 static void __init exynosautov9_cmu_top_init(struct device_node *np)
952 {
953 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
954 }
955
956 /* Register CMU_TOP early, as it's a dependency for other early domains */
957 CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
958 exynosautov9_cmu_top_init);
959
960 /* ---- CMU_BUSMC ---------------------------------------------------------- */
961
962 /* Register Offset definitions for CMU_BUSMC (0x1b200000) */
963 #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0x0600
964 #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0x1800
965 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0x2078
966 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2080
967
968 static const unsigned long busmc_clk_regs[] __initconst = {
969 PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER,
970 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP,
971 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK,
972 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK,
973 };
974
975 /* List of parent clocks for Muxes in CMU_BUSMC */
976 PNAME(mout_busmc_bus_user_p) = { "oscclk", "dout_clkcmu_busmc_bus" };
977
978 static const struct samsung_mux_clock busmc_mux_clks[] __initconst = {
979 MUX(CLK_MOUT_BUSMC_BUS_USER, "mout_busmc_bus_user",
980 mout_busmc_bus_user_p, PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER, 4, 1),
981 };
982
983 static const struct samsung_div_clock busmc_div_clks[] __initconst = {
984 DIV(CLK_DOUT_BUSMC_BUSP, "dout_busmc_busp", "mout_busmc_bus_user",
985 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
986 };
987
988 static const struct samsung_gate_clock busmc_gate_clks[] __initconst = {
989 GATE(CLK_GOUT_BUSMC_PDMA0_PCLK, "gout_busmc_pdma0_pclk",
990 "dout_busmc_busp",
991 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK, 21,
992 0, 0),
993 GATE(CLK_GOUT_BUSMC_SPDMA_PCLK, "gout_busmc_spdma_pclk",
994 "dout_busmc_busp",
995 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK, 21,
996 0, 0),
997 };
998
999 static const struct samsung_cmu_info busmc_cmu_info __initconst = {
1000 .mux_clks = busmc_mux_clks,
1001 .nr_mux_clks = ARRAY_SIZE(busmc_mux_clks),
1002 .div_clks = busmc_div_clks,
1003 .nr_div_clks = ARRAY_SIZE(busmc_div_clks),
1004 .gate_clks = busmc_gate_clks,
1005 .nr_gate_clks = ARRAY_SIZE(busmc_gate_clks),
1006 .nr_clk_ids = BUSMC_NR_CLK,
1007 .clk_regs = busmc_clk_regs,
1008 .nr_clk_regs = ARRAY_SIZE(busmc_clk_regs),
1009 .clk_name = "dout_clkcmu_busmc_bus",
1010 };
1011
1012 /* ---- CMU_CORE ----------------------------------------------------------- */
1013
1014 /* Register Offset definitions for CMU_CORE (0x1b030000) */
1015 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1016 #define CLK_CON_MUX_MUX_CORE_CMUREF 0x1000
1017 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1018 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0x2000
1019 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0x2004
1020 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0x2008
1021
1022 static const unsigned long core_clk_regs[] __initconst = {
1023 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
1024 CLK_CON_MUX_MUX_CORE_CMUREF,
1025 CLK_CON_DIV_DIV_CLK_CORE_BUSP,
1026 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
1027 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
1028 CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
1029 };
1030
1031 /* List of parent clocks for Muxes in CMU_CORE */
1032 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_clkcmu_core_bus" };
1033
1034 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
1035 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
1036 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
1037 };
1038
1039 static const struct samsung_div_clock core_div_clks[] __initconst = {
1040 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
1041 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
1042 };
1043
1044 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
1045 GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_core_bus_user",
1046 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 21,
1047 CLK_IS_CRITICAL, 0),
1048 GATE(CLK_GOUT_CORE_CCI_PCLK, "gout_core_cci_pclk", "dout_core_busp",
1049 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 21,
1050 CLK_IS_CRITICAL, 0),
1051 GATE(CLK_GOUT_CORE_CMU_CORE_PCLK, "gout_core_cmu_core_pclk",
1052 "dout_core_busp",
1053 CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 21,
1054 CLK_IS_CRITICAL, 0),
1055 };
1056
1057 static const struct samsung_cmu_info core_cmu_info __initconst = {
1058 .mux_clks = core_mux_clks,
1059 .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
1060 .div_clks = core_div_clks,
1061 .nr_div_clks = ARRAY_SIZE(core_div_clks),
1062 .gate_clks = core_gate_clks,
1063 .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
1064 .nr_clk_ids = CORE_NR_CLK,
1065 .clk_regs = core_clk_regs,
1066 .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
1067 .clk_name = "dout_clkcmu_core_bus",
1068 };
1069
1070 /* ---- CMU_FSYS2 ---------------------------------------------------------- */
1071
1072 /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
1073 #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600
1074 #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620
1075 #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610
1076 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098
1077 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c
1078 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4
1079 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8
1080
1081 static const unsigned long fsys2_clk_regs[] __initconst = {
1082 PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER,
1083 PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER,
1084 PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER,
1085 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK,
1086 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1087 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK,
1088 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1089 };
1090
1091 /* List of parent clocks for Muxes in CMU_FSYS2 */
1092 PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" };
1093 PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" };
1094 PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" };
1095
1096 static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = {
1097 MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user",
1098 mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1),
1099 MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user",
1100 mout_fsys2_ufs_embd_user_p,
1101 PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1),
1102 MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user",
1103 mout_fsys2_ethernet_user_p,
1104 PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1),
1105 };
1106
1107 static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = {
1108 GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk",
1109 "mout_fsys2_ufs_embd_user",
1110 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21,
1111 0, 0),
1112 GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro",
1113 "mout_fsys2_ufs_embd_user",
1114 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1115 21, 0, 0),
1116 GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk",
1117 "mout_fsys2_ufs_embd_user",
1118 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21,
1119 0, 0),
1120 GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro",
1121 "mout_fsys2_ufs_embd_user",
1122 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1123 21, 0, 0),
1124 };
1125
1126 static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
1127 .mux_clks = fsys2_mux_clks,
1128 .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks),
1129 .gate_clks = fsys2_gate_clks,
1130 .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks),
1131 .nr_clk_ids = FSYS2_NR_CLK,
1132 .clk_regs = fsys2_clk_regs,
1133 .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs),
1134 .clk_name = "dout_clkcmu_fsys2_bus",
1135 };
1136
1137 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1138
1139 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1140 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1141 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
1142 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
1143 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
1144 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
1145 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
1146 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
1147 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
1148 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
1149 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
1150 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
1151 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
1152 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
1153 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
1154 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
1155 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
1156 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
1157 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
1158 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
1159 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
1160 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
1161 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
1162 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
1163 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
1164 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
1165 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
1166 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
1167 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
1168 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
1169 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
1170 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
1171 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
1172 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1173 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1174 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1175 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1176 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1177 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1178 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
1179 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
1180
1181 static const unsigned long peric0_clk_regs[] __initconst = {
1182 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1183 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1184 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1185 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1186 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1187 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1188 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1189 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1190 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1191 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1192 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1193 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1194 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1195 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1196 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1197 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1198 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1199 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1200 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1201 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1202 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1203 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1204 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1205 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1206 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1207 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1208 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1209 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1210 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1211 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
1212 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1213 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1214 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1215 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1216 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1217 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1218 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1219 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1220 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1221 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1222 };
1223
1224 /* List of parent clocks for Muxes in CMU_PERIC0 */
1225 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };
1226 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1227 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1228
1229 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1230 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
1231 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
1232 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1233 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1234 /* USI00 ~ USI05 */
1235 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1236 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1237 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1238 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1239 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1240 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1241 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1242 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1243 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1244 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1245 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1246 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1247 /* USI_I2C */
1248 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1249 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1250 };
1251
1252 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1253 /* USI00 ~ USI05 */
1254 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1255 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1256 0, 4),
1257 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1258 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1259 0, 4),
1260 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1261 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1262 0, 4),
1263 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1264 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1265 0, 4),
1266 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1267 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1268 0, 4),
1269 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1270 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1271 0, 4),
1272 /* USI_I2C */
1273 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1274 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1275 };
1276
1277 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
1278 /* IPCLK */
1279 GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",
1280 "dout_peric0_usi00_usi",
1281 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1282 21, 0, 0),
1283 GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",
1284 "dout_peric0_usi_i2c",
1285 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1286 21, 0, 0),
1287 GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",
1288 "dout_peric0_usi01_usi",
1289 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1290 21, 0, 0),
1291 GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",
1292 "dout_peric0_usi_i2c",
1293 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1294 21, 0, 0),
1295 GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",
1296 "dout_peric0_usi02_usi",
1297 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1298 21, 0, 0),
1299 GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",
1300 "dout_peric0_usi_i2c",
1301 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1302 21, 0, 0),
1303 GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",
1304 "dout_peric0_usi03_usi",
1305 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1306 21, 0, 0),
1307 GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",
1308 "dout_peric0_usi_i2c",
1309 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1310 21, 0, 0),
1311 GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",
1312 "dout_peric0_usi04_usi",
1313 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1314 21, 0, 0),
1315 GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",
1316 "dout_peric0_usi_i2c",
1317 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1318 21, 0, 0),
1319 GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",
1320 "dout_peric0_usi05_usi",
1321 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1322 21, 0, 0),
1323 GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",
1324 "dout_peric0_usi_i2c",
1325 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1326 21, 0, 0),
1327
1328 /* PCLK */
1329 GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",
1330 "mout_peric0_bus_user",
1331 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1332 21, 0, 0),
1333 GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
1334 "mout_peric0_bus_user",
1335 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1336 21, 0, 0),
1337 GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",
1338 "mout_peric0_bus_user",
1339 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1340 21, 0, 0),
1341 GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",
1342 "mout_peric0_bus_user",
1343 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1344 21, 0, 0),
1345 GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",
1346 "mout_peric0_bus_user",
1347 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1348 21, 0, 0),
1349 GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",
1350 "mout_peric0_bus_user",
1351 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1352 21, 0, 0),
1353 GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",
1354 "mout_peric0_bus_user",
1355 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1356 21, 0, 0),
1357 GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",
1358 "mout_peric0_bus_user",
1359 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1360 21, 0, 0),
1361 GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",
1362 "mout_peric0_bus_user",
1363 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1364 21, 0, 0),
1365 GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",
1366 "mout_peric0_bus_user",
1367 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1368 21, 0, 0),
1369 GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",
1370 "mout_peric0_bus_user",
1371 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1372 21, 0, 0),
1373 };
1374
1375 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1376 .mux_clks = peric0_mux_clks,
1377 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1378 .div_clks = peric0_div_clks,
1379 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1380 .gate_clks = peric0_gate_clks,
1381 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
1382 .nr_clk_ids = PERIC0_NR_CLK,
1383 .clk_regs = peric0_clk_regs,
1384 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1385 .clk_name = "dout_clkcmu_peric0_bus",
1386 };
1387
1388 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1389
1390 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
1391 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1392 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610
1393 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000
1394 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004
1395 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008
1396 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c
1397 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010
1398 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014
1399 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018
1400 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800
1401 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804
1402 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808
1403 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c
1404 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810
1405 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814
1406 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818
1407 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014
1408 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018
1409 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
1410 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
1411 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
1412 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
1413 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
1414 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038
1415 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c
1416 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040
1417 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c
1418 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
1419 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
1420 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
1421 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2058
1422 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x205c
1423 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2060
1424 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x206c
1425 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2064
1426 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2068
1427 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2070
1428 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2074
1429 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
1430 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
1431
1432 static const unsigned long peric1_clk_regs[] __initconst = {
1433 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
1434 PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1435 CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI,
1436 CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI,
1437 CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI,
1438 CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1439 CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1440 CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1441 CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1442 CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1443 CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1444 CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1445 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1446 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1447 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1448 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1449 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1450 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1451 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1452 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1453 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1454 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1455 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1456 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1457 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1458 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1459 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1460 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1461 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1462 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
1463 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1464 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1465 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1466 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1467 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1468 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1469 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1470 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1471 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
1472 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
1473 };
1474
1475 /* List of parent clocks for Muxes in CMU_PERIC1 */
1476 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_clkcmu_peric1_bus" };
1477 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1478 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1479
1480 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1481 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
1482 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
1483 MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1484 mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1485 /* USI06 ~ USI11 */
1486 MUX(CLK_MOUT_PERIC1_USI06_USI, "mout_peric1_usi06_usi",
1487 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
1488 MUX(CLK_MOUT_PERIC1_USI07_USI, "mout_peric1_usi07_usi",
1489 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
1490 MUX(CLK_MOUT_PERIC1_USI08_USI, "mout_peric1_usi08_usi",
1491 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
1492 MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1493 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1494 MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1495 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1496 MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1497 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1498 /* USI_I2C */
1499 MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1500 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1501 };
1502
1503 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1504 /* USI06 ~ USI11 */
1505 DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
1506 "mout_peric1_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1507 0, 4),
1508 DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
1509 "mout_peric1_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1510 0, 4),
1511 DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
1512 "mout_peric1_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1513 0, 4),
1514 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1515 "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1516 0, 4),
1517 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1518 "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1519 0, 4),
1520 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1521 "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1522 0, 4),
1523 /* USI_I2C */
1524 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1525 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1526 };
1527
1528 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
1529 /* IPCLK */
1530 GATE(CLK_GOUT_PERIC1_IPCLK_0, "gout_peric1_ipclk_0",
1531 "dout_peric1_usi06_usi",
1532 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1533 21, 0, 0),
1534 GATE(CLK_GOUT_PERIC1_IPCLK_1, "gout_peric1_ipclk_1",
1535 "dout_peric1_usi_i2c",
1536 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1537 21, 0, 0),
1538 GATE(CLK_GOUT_PERIC1_IPCLK_2, "gout_peric1_ipclk_2",
1539 "dout_peric1_usi07_usi",
1540 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1541 21, 0, 0),
1542 GATE(CLK_GOUT_PERIC1_IPCLK_3, "gout_peric1_ipclk_3",
1543 "dout_peric1_usi_i2c",
1544 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1545 21, 0, 0),
1546 GATE(CLK_GOUT_PERIC1_IPCLK_4, "gout_peric1_ipclk_4",
1547 "dout_peric1_usi08_usi",
1548 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1549 21, 0, 0),
1550 GATE(CLK_GOUT_PERIC1_IPCLK_5, "gout_peric1_ipclk_5",
1551 "dout_peric1_usi_i2c",
1552 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1553 21, 0, 0),
1554 GATE(CLK_GOUT_PERIC1_IPCLK_6, "gout_peric1_ipclk_6",
1555 "dout_peric1_usi09_usi",
1556 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1557 21, 0, 0),
1558 GATE(CLK_GOUT_PERIC1_IPCLK_7, "gout_peric1_ipclk_7",
1559 "dout_peric1_usi_i2c",
1560 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1561 21, 0, 0),
1562 GATE(CLK_GOUT_PERIC1_IPCLK_8, "gout_peric1_ipclk_8",
1563 "dout_peric1_usi10_usi",
1564 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1565 21, 0, 0),
1566 GATE(CLK_GOUT_PERIC1_IPCLK_9, "gout_peric1_ipclk_9",
1567 "dout_peric1_usi_i2c",
1568 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1569 21, 0, 0),
1570 GATE(CLK_GOUT_PERIC1_IPCLK_10, "gout_peric1_ipclk_10",
1571 "dout_peric1_usi11_usi",
1572 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1573 21, 0, 0),
1574 GATE(CLK_GOUT_PERIC1_IPCLK_11, "gout_peric1_ipclk_11",
1575 "dout_peric1_usi_i2c",
1576 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1577 21, 0, 0),
1578
1579 /* PCLK */
1580 GATE(CLK_GOUT_PERIC1_PCLK_0, "gout_peric1_pclk_0",
1581 "mout_peric1_bus_user",
1582 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1583 21, 0, 0),
1584 GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
1585 "mout_peric1_bus_user",
1586 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1587 21, 0, 0),
1588 GATE(CLK_GOUT_PERIC1_PCLK_3, "gout_peric1_pclk_3",
1589 "mout_peric1_bus_user",
1590 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1591 21, 0, 0),
1592 GATE(CLK_GOUT_PERIC1_PCLK_4, "gout_peric1_pclk_4",
1593 "mout_peric1_bus_user",
1594 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1595 21, 0, 0),
1596 GATE(CLK_GOUT_PERIC1_PCLK_5, "gout_peric1_pclk_5",
1597 "mout_peric1_bus_user",
1598 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1599 21, 0, 0),
1600 GATE(CLK_GOUT_PERIC1_PCLK_6, "gout_peric1_pclk_6",
1601 "mout_peric1_bus_user",
1602 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1603 21, 0, 0),
1604 GATE(CLK_GOUT_PERIC1_PCLK_7, "gout_peric1_pclk_7",
1605 "mout_peric1_bus_user",
1606 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1607 21, 0, 0),
1608 GATE(CLK_GOUT_PERIC1_PCLK_8, "gout_peric1_pclk_8",
1609 "mout_peric1_bus_user",
1610 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1611 21, 0, 0),
1612 GATE(CLK_GOUT_PERIC1_PCLK_9, "gout_peric1_pclk_9",
1613 "mout_peric1_bus_user",
1614 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1615 21, 0, 0),
1616 GATE(CLK_GOUT_PERIC1_PCLK_10, "gout_peric1_pclk_10",
1617 "mout_peric1_bus_user",
1618 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
1619 21, 0, 0),
1620 GATE(CLK_GOUT_PERIC1_PCLK_11, "gout_peric1_pclk_11",
1621 "mout_peric1_bus_user",
1622 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
1623 21, 0, 0),
1624 };
1625
1626 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
1627 .mux_clks = peric1_mux_clks,
1628 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
1629 .div_clks = peric1_div_clks,
1630 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
1631 .gate_clks = peric1_gate_clks,
1632 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
1633 .nr_clk_ids = PERIC1_NR_CLK,
1634 .clk_regs = peric1_clk_regs,
1635 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
1636 .clk_name = "dout_clkcmu_peric1_bus",
1637 };
1638
1639 /* ---- CMU_PERIS ---------------------------------------------------------- */
1640
1641 /* Register Offset definitions for CMU_PERIS (0x10020000) */
1642 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
1643 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2058
1644 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x205c
1645 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x2060
1646
1647 static const unsigned long peris_clk_regs[] __initconst = {
1648 PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
1649 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1650 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1651 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
1652 };
1653
1654 /* List of parent clocks for Muxes in CMU_PERIS */
1655 PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_clkcmu_peris_bus" };
1656
1657 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
1658 MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
1659 mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1),
1660 };
1661
1662 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1663 GATE(CLK_GOUT_SYSREG_PERIS_PCLK, "gout_sysreg_peris_pclk",
1664 "mout_peris_bus_user",
1665 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1666 21, CLK_IGNORE_UNUSED, 0),
1667 GATE(CLK_GOUT_WDT_CLUSTER0, "gout_wdt_cluster0", "mout_peris_bus_user",
1668 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1669 21, 0, 0),
1670 GATE(CLK_GOUT_WDT_CLUSTER1, "gout_wdt_cluster1", "mout_peris_bus_user",
1671 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
1672 21, 0, 0),
1673 };
1674
1675 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1676 .mux_clks = peris_mux_clks,
1677 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
1678 .gate_clks = peris_gate_clks,
1679 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1680 .nr_clk_ids = PERIS_NR_CLK,
1681 .clk_regs = peris_clk_regs,
1682 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1683 .clk_name = "dout_clkcmu_peris_bus",
1684 };
1685
exynosautov9_cmu_probe(struct platform_device * pdev)1686 static int __init exynosautov9_cmu_probe(struct platform_device *pdev)
1687 {
1688 const struct samsung_cmu_info *info;
1689 struct device *dev = &pdev->dev;
1690
1691 info = of_device_get_match_data(dev);
1692 exynos_arm64_register_cmu(dev, dev->of_node, info);
1693
1694 return 0;
1695 }
1696
1697 static const struct of_device_id exynosautov9_cmu_of_match[] = {
1698 {
1699 .compatible = "samsung,exynosautov9-cmu-busmc",
1700 .data = &busmc_cmu_info,
1701 }, {
1702 .compatible = "samsung,exynosautov9-cmu-core",
1703 .data = &core_cmu_info,
1704 }, {
1705 .compatible = "samsung,exynosautov9-cmu-fsys2",
1706 .data = &fsys2_cmu_info,
1707 }, {
1708 .compatible = "samsung,exynosautov9-cmu-peric0",
1709 .data = &peric0_cmu_info,
1710 }, {
1711 .compatible = "samsung,exynosautov9-cmu-peric1",
1712 .data = &peric1_cmu_info,
1713 }, {
1714 .compatible = "samsung,exynosautov9-cmu-peris",
1715 .data = &peris_cmu_info,
1716 }, {
1717 },
1718 };
1719
1720 static struct platform_driver exynosautov9_cmu_driver __refdata = {
1721 .driver = {
1722 .name = "exynosautov9-cmu",
1723 .of_match_table = exynosautov9_cmu_of_match,
1724 .suppress_bind_attrs = true,
1725 },
1726 .probe = exynosautov9_cmu_probe,
1727 };
1728
exynosautov9_cmu_init(void)1729 static int __init exynosautov9_cmu_init(void)
1730 {
1731 return platform_driver_register(&exynosautov9_cmu_driver);
1732 }
1733 core_initcall(exynosautov9_cmu_init);
1734