1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PLL clock descriptions for TI DM365
4 *
5 * Copyright (C) 2018 David Lechner <david@lechnology.com>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/clkdev.h>
10 #include <linux/clk/davinci.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14
15 #include "pll.h"
16
17 #define OCSEL_OCSRC_ENABLE 0
18
19 static const struct davinci_pll_clk_info dm365_pll1_info = {
20 .name = "pll1",
21 .pllm_mask = GENMASK(9, 0),
22 .pllm_min = 1,
23 .pllm_max = 1023,
24 .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
25 PLL_POSTDIV_ALWAYS_ENABLED | PLL_PLLM_2X,
26 };
27
28 SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
29 SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
30 SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
31 SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
32 SYSCLK(5, pll1_sysclk5, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
33 SYSCLK(6, pll1_sysclk6, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
34 SYSCLK(7, pll1_sysclk7, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
35 SYSCLK(8, pll1_sysclk8, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
36 SYSCLK(9, pll1_sysclk9, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
37
38 /*
39 * This is a bit of a hack to make OCSEL[OCSRC] on DM365 look like OCSEL[OCSRC]
40 * on DA850. On DM365, OCSEL[OCSRC] is just an enable/disable bit instead of a
41 * multiplexer. By modeling it as a single parent mux clock, the clock code will
42 * still do the right thing in this case.
43 */
44 static const char * const dm365_pll_obsclk_parent_names[] = {
45 "oscin",
46 };
47
48 static u32 dm365_pll_obsclk_table[] = {
49 OCSEL_OCSRC_ENABLE,
50 };
51
52 static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
53 .name = "pll1_obsclk",
54 .parent_names = dm365_pll_obsclk_parent_names,
55 .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
56 .table = dm365_pll_obsclk_table,
57 .ocsrc_mask = BIT(4),
58 };
59
dm365_pll1_init(struct device * dev,void __iomem * base,struct regmap * cfgchip)60 int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
61 {
62 struct clk *clk;
63
64 davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
65
66 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
67 clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
68
69 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
70 clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
71
72 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
73 clk_register_clkdev(clk, "pll1_sysclk3", "dm365-psc");
74
75 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
76 clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
77
78 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
79 clk_register_clkdev(clk, "pll1_sysclk5", "dm365-psc");
80
81 davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
82
83 davinci_pll_sysclk_register(dev, &pll1_sysclk7, base);
84
85 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
86 clk_register_clkdev(clk, "pll1_sysclk8", "dm365-psc");
87
88 davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
89
90 clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
91 clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
92
93 davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
94
95 davinci_pll_obsclk_register(dev, &dm365_pll1_obsclk_info, base);
96
97 return 0;
98 }
99
100 static const struct davinci_pll_clk_info dm365_pll2_info = {
101 .name = "pll2",
102 .pllm_mask = GENMASK(9, 0),
103 .pllm_min = 1,
104 .pllm_max = 1023,
105 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_POSTDIV_ALWAYS_ENABLED |
106 PLL_PLLM_2X,
107 };
108
109 SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
110 SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
111 SYSCLK(3, pll2_sysclk3, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
112 SYSCLK(4, pll2_sysclk4, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
113 SYSCLK(5, pll2_sysclk5, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
114
115 static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
116 .name = "pll2_obsclk",
117 .parent_names = dm365_pll_obsclk_parent_names,
118 .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
119 .table = dm365_pll_obsclk_table,
120 .ocsrc_mask = BIT(4),
121 };
122
dm365_pll2_init(struct device * dev,void __iomem * base,struct regmap * cfgchip)123 int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
124 {
125 struct clk *clk;
126
127 davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
128
129 davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
130
131 clk = davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
132 clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
133
134 davinci_pll_sysclk_register(dev, &pll2_sysclk3, base);
135
136 clk = davinci_pll_sysclk_register(dev, &pll2_sysclk4, base);
137 clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
138
139 davinci_pll_sysclk_register(dev, &pll2_sysclk5, base);
140
141 davinci_pll_auxclk_register(dev, "pll2_auxclk", base);
142
143 davinci_pll_obsclk_register(dev, &dm365_pll2_obsclk_info, base);
144
145 return 0;
146 }
147