1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34 #define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36 #include <linux/delay.h>
37 #include <linux/iopoll.h>
38 #include <linux/ktime.h>
39 #include <linux/rwsem.h>
40 #include <linux/wait.h>
41 #include <linux/topology.h>
42
43 #include <acpi/cppc_acpi.h>
44
45 struct cppc_pcc_data {
46 struct pcc_mbox_chan *pcc_channel;
47 void __iomem *pcc_comm_addr;
48 bool pcc_channel_acquired;
49 unsigned int deadline_us;
50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
51
52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
53 bool platform_owns_pcc; /* Ownership of PCC subspace */
54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
55
56 /*
57 * Lock to provide controlled access to the PCC channel.
58 *
59 * For performance critical usecases(currently cppc_set_perf)
60 * We need to take read_lock and check if channel belongs to OSPM
61 * before reading or writing to PCC subspace
62 * We need to take write_lock before transferring the channel
63 * ownership to the platform via a Doorbell
64 * This allows us to batch a number of CPPC requests if they happen
65 * to originate in about the same time
66 *
67 * For non-performance critical usecases(init)
68 * Take write_lock for all purposes which gives exclusive access
69 */
70 struct rw_semaphore pcc_lock;
71
72 /* Wait queue for CPUs whose requests were batched */
73 wait_queue_head_t pcc_write_wait_q;
74 ktime_t last_cmd_cmpl_time;
75 ktime_t last_mpar_reset;
76 int mpar_count;
77 int refcount;
78 };
79
80 /* Array to represent the PCC channel per subspace ID */
81 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
82 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
83 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
84
85 /*
86 * The cpc_desc structure contains the ACPI register details
87 * as described in the per CPU _CPC tables. The details
88 * include the type of register (e.g. PCC, System IO, FFH etc.)
89 * and destination addresses which lets us READ/WRITE CPU performance
90 * information using the appropriate I/O methods.
91 */
92 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
93
94 /* pcc mapped address + header size + offset within PCC subspace */
95 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
96 0x8 + (offs))
97
98 /* Check if a CPC register is in PCC */
99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
100 (cpc)->cpc_entry.reg.space_id == \
101 ACPI_ADR_SPACE_PLATFORM_COMM)
102
103 /* Check if a CPC register is in SystemMemory */
104 #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
105 (cpc)->cpc_entry.reg.space_id == \
106 ACPI_ADR_SPACE_SYSTEM_MEMORY)
107
108 /* Check if a CPC register is in SystemIo */
109 #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
110 (cpc)->cpc_entry.reg.space_id == \
111 ACPI_ADR_SPACE_SYSTEM_IO)
112
113 /* Evaluates to True if reg is a NULL register descriptor */
114 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
115 (reg)->address == 0 && \
116 (reg)->bit_width == 0 && \
117 (reg)->bit_offset == 0 && \
118 (reg)->access_width == 0)
119
120 /* Evaluates to True if an optional cpc field is supported */
121 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
122 !!(cpc)->cpc_entry.int_value : \
123 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
124 /*
125 * Arbitrary Retries in case the remote processor is slow to respond
126 * to PCC commands. Keeping it high enough to cover emulators where
127 * the processors run painfully slow.
128 */
129 #define NUM_RETRIES 500ULL
130
131 #define OVER_16BTS_MASK ~0xFFFFULL
132
133 #define define_one_cppc_ro(_name) \
134 static struct kobj_attribute _name = \
135 __ATTR(_name, 0444, show_##_name, NULL)
136
137 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
138
139 #define show_cppc_data(access_fn, struct_name, member_name) \
140 static ssize_t show_##member_name(struct kobject *kobj, \
141 struct kobj_attribute *attr, char *buf) \
142 { \
143 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
144 struct struct_name st_name = {0}; \
145 int ret; \
146 \
147 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
148 if (ret) \
149 return ret; \
150 \
151 return scnprintf(buf, PAGE_SIZE, "%llu\n", \
152 (u64)st_name.member_name); \
153 } \
154 define_one_cppc_ro(member_name)
155
156 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
157 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
158 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
159 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
160 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
161 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
162
163 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
164 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
165
show_feedback_ctrs(struct kobject * kobj,struct kobj_attribute * attr,char * buf)166 static ssize_t show_feedback_ctrs(struct kobject *kobj,
167 struct kobj_attribute *attr, char *buf)
168 {
169 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
170 struct cppc_perf_fb_ctrs fb_ctrs = {0};
171 int ret;
172
173 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
174 if (ret)
175 return ret;
176
177 return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
178 fb_ctrs.reference, fb_ctrs.delivered);
179 }
180 define_one_cppc_ro(feedback_ctrs);
181
182 static struct attribute *cppc_attrs[] = {
183 &feedback_ctrs.attr,
184 &reference_perf.attr,
185 &wraparound_time.attr,
186 &highest_perf.attr,
187 &lowest_perf.attr,
188 &lowest_nonlinear_perf.attr,
189 &nominal_perf.attr,
190 &nominal_freq.attr,
191 &lowest_freq.attr,
192 NULL
193 };
194 ATTRIBUTE_GROUPS(cppc);
195
196 static struct kobj_type cppc_ktype = {
197 .sysfs_ops = &kobj_sysfs_ops,
198 .default_groups = cppc_groups,
199 };
200
check_pcc_chan(int pcc_ss_id,bool chk_err_bit)201 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
202 {
203 int ret, status;
204 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
205 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
206 pcc_ss_data->pcc_comm_addr;
207
208 if (!pcc_ss_data->platform_owns_pcc)
209 return 0;
210
211 /*
212 * Poll PCC status register every 3us(delay_us) for maximum of
213 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
214 */
215 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
216 status & PCC_CMD_COMPLETE_MASK, 3,
217 pcc_ss_data->deadline_us);
218
219 if (likely(!ret)) {
220 pcc_ss_data->platform_owns_pcc = false;
221 if (chk_err_bit && (status & PCC_ERROR_MASK))
222 ret = -EIO;
223 }
224
225 if (unlikely(ret))
226 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
227 pcc_ss_id, ret);
228
229 return ret;
230 }
231
232 /*
233 * This function transfers the ownership of the PCC to the platform
234 * So it must be called while holding write_lock(pcc_lock)
235 */
send_pcc_cmd(int pcc_ss_id,u16 cmd)236 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
237 {
238 int ret = -EIO, i;
239 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
240 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
241 pcc_ss_data->pcc_comm_addr;
242 unsigned int time_delta;
243
244 /*
245 * For CMD_WRITE we know for a fact the caller should have checked
246 * the channel before writing to PCC space
247 */
248 if (cmd == CMD_READ) {
249 /*
250 * If there are pending cpc_writes, then we stole the channel
251 * before write completion, so first send a WRITE command to
252 * platform
253 */
254 if (pcc_ss_data->pending_pcc_write_cmd)
255 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
256
257 ret = check_pcc_chan(pcc_ss_id, false);
258 if (ret)
259 goto end;
260 } else /* CMD_WRITE */
261 pcc_ss_data->pending_pcc_write_cmd = FALSE;
262
263 /*
264 * Handle the Minimum Request Turnaround Time(MRTT)
265 * "The minimum amount of time that OSPM must wait after the completion
266 * of a command before issuing the next command, in microseconds"
267 */
268 if (pcc_ss_data->pcc_mrtt) {
269 time_delta = ktime_us_delta(ktime_get(),
270 pcc_ss_data->last_cmd_cmpl_time);
271 if (pcc_ss_data->pcc_mrtt > time_delta)
272 udelay(pcc_ss_data->pcc_mrtt - time_delta);
273 }
274
275 /*
276 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
277 * "The maximum number of periodic requests that the subspace channel can
278 * support, reported in commands per minute. 0 indicates no limitation."
279 *
280 * This parameter should be ideally zero or large enough so that it can
281 * handle maximum number of requests that all the cores in the system can
282 * collectively generate. If it is not, we will follow the spec and just
283 * not send the request to the platform after hitting the MPAR limit in
284 * any 60s window
285 */
286 if (pcc_ss_data->pcc_mpar) {
287 if (pcc_ss_data->mpar_count == 0) {
288 time_delta = ktime_ms_delta(ktime_get(),
289 pcc_ss_data->last_mpar_reset);
290 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
291 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
292 pcc_ss_id);
293 ret = -EIO;
294 goto end;
295 }
296 pcc_ss_data->last_mpar_reset = ktime_get();
297 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
298 }
299 pcc_ss_data->mpar_count--;
300 }
301
302 /* Write to the shared comm region. */
303 writew_relaxed(cmd, &generic_comm_base->command);
304
305 /* Flip CMD COMPLETE bit */
306 writew_relaxed(0, &generic_comm_base->status);
307
308 pcc_ss_data->platform_owns_pcc = true;
309
310 /* Ring doorbell */
311 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
312 if (ret < 0) {
313 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
314 pcc_ss_id, cmd, ret);
315 goto end;
316 }
317
318 /* wait for completion and check for PCC error bit */
319 ret = check_pcc_chan(pcc_ss_id, true);
320
321 if (pcc_ss_data->pcc_mrtt)
322 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
323
324 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
325 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
326 else
327 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
328
329 end:
330 if (cmd == CMD_WRITE) {
331 if (unlikely(ret)) {
332 for_each_possible_cpu(i) {
333 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
334
335 if (!desc)
336 continue;
337
338 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
339 desc->write_cmd_status = ret;
340 }
341 }
342 pcc_ss_data->pcc_write_cnt++;
343 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
344 }
345
346 return ret;
347 }
348
cppc_chan_tx_done(struct mbox_client * cl,void * msg,int ret)349 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
350 {
351 if (ret < 0)
352 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
353 *(u16 *)msg, ret);
354 else
355 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
356 *(u16 *)msg, ret);
357 }
358
359 static struct mbox_client cppc_mbox_cl = {
360 .tx_done = cppc_chan_tx_done,
361 .knows_txdone = true,
362 };
363
acpi_get_psd(struct cpc_desc * cpc_ptr,acpi_handle handle)364 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
365 {
366 int result = -EFAULT;
367 acpi_status status = AE_OK;
368 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
369 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
370 struct acpi_buffer state = {0, NULL};
371 union acpi_object *psd = NULL;
372 struct acpi_psd_package *pdomain;
373
374 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
375 &buffer, ACPI_TYPE_PACKAGE);
376 if (status == AE_NOT_FOUND) /* _PSD is optional */
377 return 0;
378 if (ACPI_FAILURE(status))
379 return -ENODEV;
380
381 psd = buffer.pointer;
382 if (!psd || psd->package.count != 1) {
383 pr_debug("Invalid _PSD data\n");
384 goto end;
385 }
386
387 pdomain = &(cpc_ptr->domain_info);
388
389 state.length = sizeof(struct acpi_psd_package);
390 state.pointer = pdomain;
391
392 status = acpi_extract_package(&(psd->package.elements[0]),
393 &format, &state);
394 if (ACPI_FAILURE(status)) {
395 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
396 goto end;
397 }
398
399 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
400 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
401 goto end;
402 }
403
404 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
405 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
406 goto end;
407 }
408
409 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
410 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
411 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
412 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
413 goto end;
414 }
415
416 result = 0;
417 end:
418 kfree(buffer.pointer);
419 return result;
420 }
421
acpi_cpc_valid(void)422 bool acpi_cpc_valid(void)
423 {
424 struct cpc_desc *cpc_ptr;
425 int cpu;
426
427 for_each_present_cpu(cpu) {
428 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
429 if (!cpc_ptr)
430 return false;
431 }
432
433 return true;
434 }
435 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
436
cppc_allow_fast_switch(void)437 bool cppc_allow_fast_switch(void)
438 {
439 struct cpc_register_resource *desired_reg;
440 struct cpc_desc *cpc_ptr;
441 int cpu;
442
443 for_each_possible_cpu(cpu) {
444 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
445 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
446 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
447 !CPC_IN_SYSTEM_IO(desired_reg))
448 return false;
449 }
450
451 return true;
452 }
453 EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
454
455 /**
456 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
457 * @cpu: Find all CPUs that share a domain with cpu.
458 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
459 *
460 * Return: 0 for success or negative value for err.
461 */
acpi_get_psd_map(unsigned int cpu,struct cppc_cpudata * cpu_data)462 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
463 {
464 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
465 struct acpi_psd_package *match_pdomain;
466 struct acpi_psd_package *pdomain;
467 int count_target, i;
468
469 /*
470 * Now that we have _PSD data from all CPUs, let's setup P-state
471 * domain info.
472 */
473 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
474 if (!cpc_ptr)
475 return -EFAULT;
476
477 pdomain = &(cpc_ptr->domain_info);
478 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
479 if (pdomain->num_processors <= 1)
480 return 0;
481
482 /* Validate the Domain info */
483 count_target = pdomain->num_processors;
484 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
485 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
486 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
487 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
488 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
489 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
490
491 for_each_possible_cpu(i) {
492 if (i == cpu)
493 continue;
494
495 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
496 if (!match_cpc_ptr)
497 goto err_fault;
498
499 match_pdomain = &(match_cpc_ptr->domain_info);
500 if (match_pdomain->domain != pdomain->domain)
501 continue;
502
503 /* Here i and cpu are in the same domain */
504 if (match_pdomain->num_processors != count_target)
505 goto err_fault;
506
507 if (pdomain->coord_type != match_pdomain->coord_type)
508 goto err_fault;
509
510 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
511 }
512
513 return 0;
514
515 err_fault:
516 /* Assume no coordination on any error parsing domain info */
517 cpumask_clear(cpu_data->shared_cpu_map);
518 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
519 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
520
521 return -EFAULT;
522 }
523 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
524
register_pcc_channel(int pcc_ss_idx)525 static int register_pcc_channel(int pcc_ss_idx)
526 {
527 struct pcc_mbox_chan *pcc_chan;
528 u64 usecs_lat;
529
530 if (pcc_ss_idx >= 0) {
531 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
532
533 if (IS_ERR(pcc_chan)) {
534 pr_err("Failed to find PCC channel for subspace %d\n",
535 pcc_ss_idx);
536 return -ENODEV;
537 }
538
539 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
540 /*
541 * cppc_ss->latency is just a Nominal value. In reality
542 * the remote processor could be much slower to reply.
543 * So add an arbitrary amount of wait on top of Nominal.
544 */
545 usecs_lat = NUM_RETRIES * pcc_chan->latency;
546 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
547 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
548 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
549 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
550
551 pcc_data[pcc_ss_idx]->pcc_comm_addr =
552 acpi_os_ioremap(pcc_chan->shmem_base_addr,
553 pcc_chan->shmem_size);
554 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
555 pr_err("Failed to ioremap PCC comm region mem for %d\n",
556 pcc_ss_idx);
557 return -ENOMEM;
558 }
559
560 /* Set flag so that we don't come here for each CPU. */
561 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
562 }
563
564 return 0;
565 }
566
567 /**
568 * cpc_ffh_supported() - check if FFH reading supported
569 *
570 * Check if the architecture has support for functional fixed hardware
571 * read/write capability.
572 *
573 * Return: true for supported, false for not supported
574 */
cpc_ffh_supported(void)575 bool __weak cpc_ffh_supported(void)
576 {
577 return false;
578 }
579
580 /**
581 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
582 *
583 * Check if the architectural support for CPPC is present even
584 * if the _OSC hasn't prescribed it
585 *
586 * Return: true for supported, false for not supported
587 */
cpc_supported_by_cpu(void)588 bool __weak cpc_supported_by_cpu(void)
589 {
590 return false;
591 }
592
593 /**
594 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
595 *
596 * Check and allocate the cppc_pcc_data memory.
597 * In some processor configurations it is possible that same subspace
598 * is shared between multiple CPUs. This is seen especially in CPUs
599 * with hardware multi-threading support.
600 *
601 * Return: 0 for success, errno for failure
602 */
pcc_data_alloc(int pcc_ss_id)603 static int pcc_data_alloc(int pcc_ss_id)
604 {
605 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
606 return -EINVAL;
607
608 if (pcc_data[pcc_ss_id]) {
609 pcc_data[pcc_ss_id]->refcount++;
610 } else {
611 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
612 GFP_KERNEL);
613 if (!pcc_data[pcc_ss_id])
614 return -ENOMEM;
615 pcc_data[pcc_ss_id]->refcount++;
616 }
617
618 return 0;
619 }
620
621 /*
622 * An example CPC table looks like the following.
623 *
624 * Name (_CPC, Package() {
625 * 17, // NumEntries
626 * 1, // Revision
627 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
628 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
629 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
630 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
631 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
632 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
633 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
634 * ...
635 * ...
636 * ...
637 * }
638 * Each Register() encodes how to access that specific register.
639 * e.g. a sample PCC entry has the following encoding:
640 *
641 * Register (
642 * PCC, // AddressSpaceKeyword
643 * 8, // RegisterBitWidth
644 * 8, // RegisterBitOffset
645 * 0x30, // RegisterAddress
646 * 9, // AccessSize (subspace ID)
647 * )
648 */
649
650 #ifndef arch_init_invariance_cppc
arch_init_invariance_cppc(void)651 static inline void arch_init_invariance_cppc(void) { }
652 #endif
653
654 /**
655 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
656 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
657 *
658 * Return: 0 for success or negative value for err.
659 */
acpi_cppc_processor_probe(struct acpi_processor * pr)660 int acpi_cppc_processor_probe(struct acpi_processor *pr)
661 {
662 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
663 union acpi_object *out_obj, *cpc_obj;
664 struct cpc_desc *cpc_ptr;
665 struct cpc_reg *gas_t;
666 struct device *cpu_dev;
667 acpi_handle handle = pr->handle;
668 unsigned int num_ent, i, cpc_rev;
669 int pcc_subspace_id = -1;
670 acpi_status status;
671 int ret = -ENODATA;
672
673 if (!osc_sb_cppc2_support_acked) {
674 pr_debug("CPPC v2 _OSC not acked\n");
675 if (!cpc_supported_by_cpu())
676 return -ENODEV;
677 }
678
679 /* Parse the ACPI _CPC table for this CPU. */
680 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
681 ACPI_TYPE_PACKAGE);
682 if (ACPI_FAILURE(status)) {
683 ret = -ENODEV;
684 goto out_buf_free;
685 }
686
687 out_obj = (union acpi_object *) output.pointer;
688
689 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
690 if (!cpc_ptr) {
691 ret = -ENOMEM;
692 goto out_buf_free;
693 }
694
695 /* First entry is NumEntries. */
696 cpc_obj = &out_obj->package.elements[0];
697 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
698 num_ent = cpc_obj->integer.value;
699 if (num_ent <= 1) {
700 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
701 num_ent, pr->id);
702 goto out_free;
703 }
704 } else {
705 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
706 cpc_obj->type, pr->id);
707 goto out_free;
708 }
709
710 /* Second entry should be revision. */
711 cpc_obj = &out_obj->package.elements[1];
712 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
713 cpc_rev = cpc_obj->integer.value;
714 } else {
715 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
716 cpc_obj->type, pr->id);
717 goto out_free;
718 }
719
720 if (cpc_rev < CPPC_V2_REV) {
721 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
722 pr->id);
723 goto out_free;
724 }
725
726 /*
727 * Disregard _CPC if the number of entries in the return pachage is not
728 * as expected, but support future revisions being proper supersets of
729 * the v3 and only causing more entries to be returned by _CPC.
730 */
731 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
732 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
733 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
734 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
735 num_ent, pr->id);
736 goto out_free;
737 }
738 if (cpc_rev > CPPC_V3_REV) {
739 num_ent = CPPC_V3_NUM_ENT;
740 cpc_rev = CPPC_V3_REV;
741 }
742
743 cpc_ptr->num_entries = num_ent;
744 cpc_ptr->version = cpc_rev;
745
746 /* Iterate through remaining entries in _CPC */
747 for (i = 2; i < num_ent; i++) {
748 cpc_obj = &out_obj->package.elements[i];
749
750 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
751 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
752 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
753 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
754 gas_t = (struct cpc_reg *)
755 cpc_obj->buffer.pointer;
756
757 /*
758 * The PCC Subspace index is encoded inside
759 * the CPC table entries. The same PCC index
760 * will be used for all the PCC entries,
761 * so extract it only once.
762 */
763 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
764 if (pcc_subspace_id < 0) {
765 pcc_subspace_id = gas_t->access_width;
766 if (pcc_data_alloc(pcc_subspace_id))
767 goto out_free;
768 } else if (pcc_subspace_id != gas_t->access_width) {
769 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
770 pr->id);
771 goto out_free;
772 }
773 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
774 if (gas_t->address) {
775 void __iomem *addr;
776
777 if (!osc_cpc_flexible_adr_space_confirmed) {
778 pr_debug("Flexible address space capability not supported\n");
779 if (!cpc_supported_by_cpu())
780 goto out_free;
781 }
782
783 addr = ioremap(gas_t->address, gas_t->bit_width/8);
784 if (!addr)
785 goto out_free;
786 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
787 }
788 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
789 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
790 /*
791 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
792 * SystemIO doesn't implement 64-bit
793 * registers.
794 */
795 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
796 gas_t->access_width);
797 goto out_free;
798 }
799 if (gas_t->address & OVER_16BTS_MASK) {
800 /* SystemIO registers use 16-bit integer addresses */
801 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
802 gas_t->address);
803 goto out_free;
804 }
805 if (!osc_cpc_flexible_adr_space_confirmed) {
806 pr_debug("Flexible address space capability not supported\n");
807 if (!cpc_supported_by_cpu())
808 goto out_free;
809 }
810 } else {
811 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
812 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
813 pr_debug("Unsupported register type (%d) in _CPC\n",
814 gas_t->space_id);
815 goto out_free;
816 }
817 }
818
819 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
820 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
821 } else {
822 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
823 i, pr->id);
824 goto out_free;
825 }
826 }
827 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
828
829 /*
830 * Initialize the remaining cpc_regs as unsupported.
831 * Example: In case FW exposes CPPC v2, the below loop will initialize
832 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
833 */
834 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
835 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
836 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
837 }
838
839
840 /* Store CPU Logical ID */
841 cpc_ptr->cpu_id = pr->id;
842
843 /* Parse PSD data for this CPU */
844 ret = acpi_get_psd(cpc_ptr, handle);
845 if (ret)
846 goto out_free;
847
848 /* Register PCC channel once for all PCC subspace ID. */
849 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
850 ret = register_pcc_channel(pcc_subspace_id);
851 if (ret)
852 goto out_free;
853
854 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
855 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
856 }
857
858 /* Everything looks okay */
859 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
860
861 /* Add per logical CPU nodes for reading its feedback counters. */
862 cpu_dev = get_cpu_device(pr->id);
863 if (!cpu_dev) {
864 ret = -EINVAL;
865 goto out_free;
866 }
867
868 /* Plug PSD data into this CPU's CPC descriptor. */
869 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
870
871 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
872 "acpi_cppc");
873 if (ret) {
874 per_cpu(cpc_desc_ptr, pr->id) = NULL;
875 kobject_put(&cpc_ptr->kobj);
876 goto out_free;
877 }
878
879 arch_init_invariance_cppc();
880
881 kfree(output.pointer);
882 return 0;
883
884 out_free:
885 /* Free all the mapped sys mem areas for this CPU */
886 for (i = 2; i < cpc_ptr->num_entries; i++) {
887 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
888
889 if (addr)
890 iounmap(addr);
891 }
892 kfree(cpc_ptr);
893
894 out_buf_free:
895 kfree(output.pointer);
896 return ret;
897 }
898 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
899
900 /**
901 * acpi_cppc_processor_exit - Cleanup CPC structs.
902 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
903 *
904 * Return: Void
905 */
acpi_cppc_processor_exit(struct acpi_processor * pr)906 void acpi_cppc_processor_exit(struct acpi_processor *pr)
907 {
908 struct cpc_desc *cpc_ptr;
909 unsigned int i;
910 void __iomem *addr;
911 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
912
913 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
914 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
915 pcc_data[pcc_ss_id]->refcount--;
916 if (!pcc_data[pcc_ss_id]->refcount) {
917 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
918 kfree(pcc_data[pcc_ss_id]);
919 pcc_data[pcc_ss_id] = NULL;
920 }
921 }
922 }
923
924 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
925 if (!cpc_ptr)
926 return;
927
928 /* Free all the mapped sys mem areas for this CPU */
929 for (i = 2; i < cpc_ptr->num_entries; i++) {
930 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
931 if (addr)
932 iounmap(addr);
933 }
934
935 kobject_put(&cpc_ptr->kobj);
936 kfree(cpc_ptr);
937 }
938 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
939
940 /**
941 * cpc_read_ffh() - Read FFH register
942 * @cpunum: CPU number to read
943 * @reg: cppc register information
944 * @val: place holder for return value
945 *
946 * Read bit_width bits from a specified address and bit_offset
947 *
948 * Return: 0 for success and error code
949 */
cpc_read_ffh(int cpunum,struct cpc_reg * reg,u64 * val)950 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
951 {
952 return -ENOTSUPP;
953 }
954
955 /**
956 * cpc_write_ffh() - Write FFH register
957 * @cpunum: CPU number to write
958 * @reg: cppc register information
959 * @val: value to write
960 *
961 * Write value of bit_width bits to a specified address and bit_offset
962 *
963 * Return: 0 for success and error code
964 */
cpc_write_ffh(int cpunum,struct cpc_reg * reg,u64 val)965 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
966 {
967 return -ENOTSUPP;
968 }
969
970 /*
971 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
972 * as fast as possible. We have already mapped the PCC subspace during init, so
973 * we can directly write to it.
974 */
975
cpc_read(int cpu,struct cpc_register_resource * reg_res,u64 * val)976 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
977 {
978 void __iomem *vaddr = NULL;
979 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
980 struct cpc_reg *reg = ®_res->cpc_entry.reg;
981
982 if (reg_res->type == ACPI_TYPE_INTEGER) {
983 *val = reg_res->cpc_entry.int_value;
984 return 0;
985 }
986
987 *val = 0;
988
989 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
990 u32 width = 8 << (reg->access_width - 1);
991 u32 val_u32;
992 acpi_status status;
993
994 status = acpi_os_read_port((acpi_io_address)reg->address,
995 &val_u32, width);
996 if (ACPI_FAILURE(status)) {
997 pr_debug("Error: Failed to read SystemIO port %llx\n",
998 reg->address);
999 return -EFAULT;
1000 }
1001
1002 *val = val_u32;
1003 return 0;
1004 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
1005 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1006 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1007 vaddr = reg_res->sys_mem_vaddr;
1008 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1009 return cpc_read_ffh(cpu, reg, val);
1010 else
1011 return acpi_os_read_memory((acpi_physical_address)reg->address,
1012 val, reg->bit_width);
1013
1014 switch (reg->bit_width) {
1015 case 8:
1016 *val = readb_relaxed(vaddr);
1017 break;
1018 case 16:
1019 *val = readw_relaxed(vaddr);
1020 break;
1021 case 32:
1022 *val = readl_relaxed(vaddr);
1023 break;
1024 case 64:
1025 *val = readq_relaxed(vaddr);
1026 break;
1027 default:
1028 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1029 reg->bit_width, pcc_ss_id);
1030 return -EFAULT;
1031 }
1032
1033 return 0;
1034 }
1035
cpc_write(int cpu,struct cpc_register_resource * reg_res,u64 val)1036 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1037 {
1038 int ret_val = 0;
1039 void __iomem *vaddr = NULL;
1040 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1041 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1042
1043 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1044 u32 width = 8 << (reg->access_width - 1);
1045 acpi_status status;
1046
1047 status = acpi_os_write_port((acpi_io_address)reg->address,
1048 (u32)val, width);
1049 if (ACPI_FAILURE(status)) {
1050 pr_debug("Error: Failed to write SystemIO port %llx\n",
1051 reg->address);
1052 return -EFAULT;
1053 }
1054
1055 return 0;
1056 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
1057 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1058 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1059 vaddr = reg_res->sys_mem_vaddr;
1060 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1061 return cpc_write_ffh(cpu, reg, val);
1062 else
1063 return acpi_os_write_memory((acpi_physical_address)reg->address,
1064 val, reg->bit_width);
1065
1066 switch (reg->bit_width) {
1067 case 8:
1068 writeb_relaxed(val, vaddr);
1069 break;
1070 case 16:
1071 writew_relaxed(val, vaddr);
1072 break;
1073 case 32:
1074 writel_relaxed(val, vaddr);
1075 break;
1076 case 64:
1077 writeq_relaxed(val, vaddr);
1078 break;
1079 default:
1080 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1081 reg->bit_width, pcc_ss_id);
1082 ret_val = -EFAULT;
1083 break;
1084 }
1085
1086 return ret_val;
1087 }
1088
cppc_get_perf(int cpunum,enum cppc_regs reg_idx,u64 * perf)1089 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1090 {
1091 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1092 struct cpc_register_resource *reg;
1093
1094 if (!cpc_desc) {
1095 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1096 return -ENODEV;
1097 }
1098
1099 reg = &cpc_desc->cpc_regs[reg_idx];
1100
1101 if (CPC_IN_PCC(reg)) {
1102 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1103 struct cppc_pcc_data *pcc_ss_data = NULL;
1104 int ret = 0;
1105
1106 if (pcc_ss_id < 0)
1107 return -EIO;
1108
1109 pcc_ss_data = pcc_data[pcc_ss_id];
1110
1111 down_write(&pcc_ss_data->pcc_lock);
1112
1113 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1114 cpc_read(cpunum, reg, perf);
1115 else
1116 ret = -EIO;
1117
1118 up_write(&pcc_ss_data->pcc_lock);
1119
1120 return ret;
1121 }
1122
1123 cpc_read(cpunum, reg, perf);
1124
1125 return 0;
1126 }
1127
1128 /**
1129 * cppc_get_desired_perf - Get the desired performance register value.
1130 * @cpunum: CPU from which to get desired performance.
1131 * @desired_perf: Return address.
1132 *
1133 * Return: 0 for success, -EIO otherwise.
1134 */
cppc_get_desired_perf(int cpunum,u64 * desired_perf)1135 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1136 {
1137 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1138 }
1139 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1140
1141 /**
1142 * cppc_get_nominal_perf - Get the nominal performance register value.
1143 * @cpunum: CPU from which to get nominal performance.
1144 * @nominal_perf: Return address.
1145 *
1146 * Return: 0 for success, -EIO otherwise.
1147 */
cppc_get_nominal_perf(int cpunum,u64 * nominal_perf)1148 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1149 {
1150 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1151 }
1152
1153 /**
1154 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1155 * @cpunum: CPU from which to get capabilities info.
1156 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1157 *
1158 * Return: 0 for success with perf_caps populated else -ERRNO.
1159 */
cppc_get_perf_caps(int cpunum,struct cppc_perf_caps * perf_caps)1160 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1161 {
1162 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1163 struct cpc_register_resource *highest_reg, *lowest_reg,
1164 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1165 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1166 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1167 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1168 struct cppc_pcc_data *pcc_ss_data = NULL;
1169 int ret = 0, regs_in_pcc = 0;
1170
1171 if (!cpc_desc) {
1172 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1173 return -ENODEV;
1174 }
1175
1176 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1177 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1178 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1179 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1180 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1181 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1182 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1183
1184 /* Are any of the regs PCC ?*/
1185 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1186 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1187 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1188 if (pcc_ss_id < 0) {
1189 pr_debug("Invalid pcc_ss_id\n");
1190 return -ENODEV;
1191 }
1192 pcc_ss_data = pcc_data[pcc_ss_id];
1193 regs_in_pcc = 1;
1194 down_write(&pcc_ss_data->pcc_lock);
1195 /* Ring doorbell once to update PCC subspace */
1196 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1197 ret = -EIO;
1198 goto out_err;
1199 }
1200 }
1201
1202 cpc_read(cpunum, highest_reg, &high);
1203 perf_caps->highest_perf = high;
1204
1205 cpc_read(cpunum, lowest_reg, &low);
1206 perf_caps->lowest_perf = low;
1207
1208 cpc_read(cpunum, nominal_reg, &nom);
1209 perf_caps->nominal_perf = nom;
1210
1211 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1212 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1213 perf_caps->guaranteed_perf = 0;
1214 } else {
1215 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1216 perf_caps->guaranteed_perf = guaranteed;
1217 }
1218
1219 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1220 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1221
1222 if (!high || !low || !nom || !min_nonlinear)
1223 ret = -EFAULT;
1224
1225 /* Read optional lowest and nominal frequencies if present */
1226 if (CPC_SUPPORTED(low_freq_reg))
1227 cpc_read(cpunum, low_freq_reg, &low_f);
1228
1229 if (CPC_SUPPORTED(nom_freq_reg))
1230 cpc_read(cpunum, nom_freq_reg, &nom_f);
1231
1232 perf_caps->lowest_freq = low_f;
1233 perf_caps->nominal_freq = nom_f;
1234
1235
1236 out_err:
1237 if (regs_in_pcc)
1238 up_write(&pcc_ss_data->pcc_lock);
1239 return ret;
1240 }
1241 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1242
1243 /**
1244 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1245 * @cpunum: CPU from which to read counters.
1246 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1247 *
1248 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1249 */
cppc_get_perf_ctrs(int cpunum,struct cppc_perf_fb_ctrs * perf_fb_ctrs)1250 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1251 {
1252 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1253 struct cpc_register_resource *delivered_reg, *reference_reg,
1254 *ref_perf_reg, *ctr_wrap_reg;
1255 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1256 struct cppc_pcc_data *pcc_ss_data = NULL;
1257 u64 delivered, reference, ref_perf, ctr_wrap_time;
1258 int ret = 0, regs_in_pcc = 0;
1259
1260 if (!cpc_desc) {
1261 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1262 return -ENODEV;
1263 }
1264
1265 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1266 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1267 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1268 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1269
1270 /*
1271 * If reference perf register is not supported then we should
1272 * use the nominal perf value
1273 */
1274 if (!CPC_SUPPORTED(ref_perf_reg))
1275 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1276
1277 /* Are any of the regs PCC ?*/
1278 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1279 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1280 if (pcc_ss_id < 0) {
1281 pr_debug("Invalid pcc_ss_id\n");
1282 return -ENODEV;
1283 }
1284 pcc_ss_data = pcc_data[pcc_ss_id];
1285 down_write(&pcc_ss_data->pcc_lock);
1286 regs_in_pcc = 1;
1287 /* Ring doorbell once to update PCC subspace */
1288 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1289 ret = -EIO;
1290 goto out_err;
1291 }
1292 }
1293
1294 cpc_read(cpunum, delivered_reg, &delivered);
1295 cpc_read(cpunum, reference_reg, &reference);
1296 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1297
1298 /*
1299 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1300 * performance counters are assumed to never wrap during the lifetime of
1301 * platform
1302 */
1303 ctr_wrap_time = (u64)(~((u64)0));
1304 if (CPC_SUPPORTED(ctr_wrap_reg))
1305 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1306
1307 if (!delivered || !reference || !ref_perf) {
1308 ret = -EFAULT;
1309 goto out_err;
1310 }
1311
1312 perf_fb_ctrs->delivered = delivered;
1313 perf_fb_ctrs->reference = reference;
1314 perf_fb_ctrs->reference_perf = ref_perf;
1315 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1316 out_err:
1317 if (regs_in_pcc)
1318 up_write(&pcc_ss_data->pcc_lock);
1319 return ret;
1320 }
1321 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1322
1323 /**
1324 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1325 * Continuous Performance Control package EnableRegister field.
1326 * @cpu: CPU for which to enable CPPC register.
1327 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1328 *
1329 * Return: 0 for success, -ERRNO or -EIO otherwise.
1330 */
cppc_set_enable(int cpu,bool enable)1331 int cppc_set_enable(int cpu, bool enable)
1332 {
1333 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1334 struct cpc_register_resource *enable_reg;
1335 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1336 struct cppc_pcc_data *pcc_ss_data = NULL;
1337 int ret = -EINVAL;
1338
1339 if (!cpc_desc) {
1340 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1341 return -EINVAL;
1342 }
1343
1344 enable_reg = &cpc_desc->cpc_regs[ENABLE];
1345
1346 if (CPC_IN_PCC(enable_reg)) {
1347
1348 if (pcc_ss_id < 0)
1349 return -EIO;
1350
1351 ret = cpc_write(cpu, enable_reg, enable);
1352 if (ret)
1353 return ret;
1354
1355 pcc_ss_data = pcc_data[pcc_ss_id];
1356
1357 down_write(&pcc_ss_data->pcc_lock);
1358 /* after writing CPC, transfer the ownership of PCC to platfrom */
1359 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1360 up_write(&pcc_ss_data->pcc_lock);
1361 return ret;
1362 }
1363
1364 return cpc_write(cpu, enable_reg, enable);
1365 }
1366 EXPORT_SYMBOL_GPL(cppc_set_enable);
1367
1368 /**
1369 * cppc_set_perf - Set a CPU's performance controls.
1370 * @cpu: CPU for which to set performance controls.
1371 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1372 *
1373 * Return: 0 for success, -ERRNO otherwise.
1374 */
cppc_set_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls)1375 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1376 {
1377 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1378 struct cpc_register_resource *desired_reg;
1379 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1380 struct cppc_pcc_data *pcc_ss_data = NULL;
1381 int ret = 0;
1382
1383 if (!cpc_desc) {
1384 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1385 return -ENODEV;
1386 }
1387
1388 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1389
1390 /*
1391 * This is Phase-I where we want to write to CPC registers
1392 * -> We want all CPUs to be able to execute this phase in parallel
1393 *
1394 * Since read_lock can be acquired by multiple CPUs simultaneously we
1395 * achieve that goal here
1396 */
1397 if (CPC_IN_PCC(desired_reg)) {
1398 if (pcc_ss_id < 0) {
1399 pr_debug("Invalid pcc_ss_id\n");
1400 return -ENODEV;
1401 }
1402 pcc_ss_data = pcc_data[pcc_ss_id];
1403 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1404 if (pcc_ss_data->platform_owns_pcc) {
1405 ret = check_pcc_chan(pcc_ss_id, false);
1406 if (ret) {
1407 up_read(&pcc_ss_data->pcc_lock);
1408 return ret;
1409 }
1410 }
1411 /*
1412 * Update the pending_write to make sure a PCC CMD_READ will not
1413 * arrive and steal the channel during the switch to write lock
1414 */
1415 pcc_ss_data->pending_pcc_write_cmd = true;
1416 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1417 cpc_desc->write_cmd_status = 0;
1418 }
1419
1420 /*
1421 * Skip writing MIN/MAX until Linux knows how to come up with
1422 * useful values.
1423 */
1424 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1425
1426 if (CPC_IN_PCC(desired_reg))
1427 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1428 /*
1429 * This is Phase-II where we transfer the ownership of PCC to Platform
1430 *
1431 * Short Summary: Basically if we think of a group of cppc_set_perf
1432 * requests that happened in short overlapping interval. The last CPU to
1433 * come out of Phase-I will enter Phase-II and ring the doorbell.
1434 *
1435 * We have the following requirements for Phase-II:
1436 * 1. We want to execute Phase-II only when there are no CPUs
1437 * currently executing in Phase-I
1438 * 2. Once we start Phase-II we want to avoid all other CPUs from
1439 * entering Phase-I.
1440 * 3. We want only one CPU among all those who went through Phase-I
1441 * to run phase-II
1442 *
1443 * If write_trylock fails to get the lock and doesn't transfer the
1444 * PCC ownership to the platform, then one of the following will be TRUE
1445 * 1. There is at-least one CPU in Phase-I which will later execute
1446 * write_trylock, so the CPUs in Phase-I will be responsible for
1447 * executing the Phase-II.
1448 * 2. Some other CPU has beaten this CPU to successfully execute the
1449 * write_trylock and has already acquired the write_lock. We know for a
1450 * fact it (other CPU acquiring the write_lock) couldn't have happened
1451 * before this CPU's Phase-I as we held the read_lock.
1452 * 3. Some other CPU executing pcc CMD_READ has stolen the
1453 * down_write, in which case, send_pcc_cmd will check for pending
1454 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1455 * So this CPU can be certain that its request will be delivered
1456 * So in all cases, this CPU knows that its request will be delivered
1457 * by another CPU and can return
1458 *
1459 * After getting the down_write we still need to check for
1460 * pending_pcc_write_cmd to take care of the following scenario
1461 * The thread running this code could be scheduled out between
1462 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1463 * could have delivered the request to Platform by triggering the
1464 * doorbell and transferred the ownership of PCC to platform. So this
1465 * avoids triggering an unnecessary doorbell and more importantly before
1466 * triggering the doorbell it makes sure that the PCC channel ownership
1467 * is still with OSPM.
1468 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1469 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1470 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1471 * case during a CMD_READ and if there are pending writes it delivers
1472 * the write command before servicing the read command
1473 */
1474 if (CPC_IN_PCC(desired_reg)) {
1475 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1476 /* Update only if there are pending write commands */
1477 if (pcc_ss_data->pending_pcc_write_cmd)
1478 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1479 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1480 } else
1481 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1482 wait_event(pcc_ss_data->pcc_write_wait_q,
1483 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1484
1485 /* send_pcc_cmd updates the status in case of failure */
1486 ret = cpc_desc->write_cmd_status;
1487 }
1488 return ret;
1489 }
1490 EXPORT_SYMBOL_GPL(cppc_set_perf);
1491
1492 /**
1493 * cppc_get_transition_latency - returns frequency transition latency in ns
1494 *
1495 * ACPI CPPC does not explicitly specify how a platform can specify the
1496 * transition latency for performance change requests. The closest we have
1497 * is the timing information from the PCCT tables which provides the info
1498 * on the number and frequency of PCC commands the platform can handle.
1499 *
1500 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
1501 * then assume there is no latency.
1502 */
cppc_get_transition_latency(int cpu_num)1503 unsigned int cppc_get_transition_latency(int cpu_num)
1504 {
1505 /*
1506 * Expected transition latency is based on the PCCT timing values
1507 * Below are definition from ACPI spec:
1508 * pcc_nominal- Expected latency to process a command, in microseconds
1509 * pcc_mpar - The maximum number of periodic requests that the subspace
1510 * channel can support, reported in commands per minute. 0
1511 * indicates no limitation.
1512 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1513 * completion of a command before issuing the next command,
1514 * in microseconds.
1515 */
1516 unsigned int latency_ns = 0;
1517 struct cpc_desc *cpc_desc;
1518 struct cpc_register_resource *desired_reg;
1519 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1520 struct cppc_pcc_data *pcc_ss_data;
1521
1522 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1523 if (!cpc_desc)
1524 return CPUFREQ_ETERNAL;
1525
1526 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1527 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
1528 return 0;
1529 else if (!CPC_IN_PCC(desired_reg))
1530 return CPUFREQ_ETERNAL;
1531
1532 if (pcc_ss_id < 0)
1533 return CPUFREQ_ETERNAL;
1534
1535 pcc_ss_data = pcc_data[pcc_ss_id];
1536 if (pcc_ss_data->pcc_mpar)
1537 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1538
1539 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1540 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1541
1542 return latency_ns;
1543 }
1544 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1545