1########################################################################
2# Implement fast SHA-512 with AVX instructions. (x86_64)
3#
4# Copyright (C) 2013 Intel Corporation.
5#
6# Authors:
7#     James Guilford <james.guilford@intel.com>
8#     Kirk Yap <kirk.s.yap@intel.com>
9#     David Cote <david.m.cote@intel.com>
10#     Tim Chen <tim.c.chen@linux.intel.com>
11#
12# This software is available to you under a choice of one of two
13# licenses.  You may choose to be licensed under the terms of the GNU
14# General Public License (GPL) Version 2, available from the file
15# COPYING in the main directory of this source tree, or the
16# OpenIB.org BSD license below:
17#
18#     Redistribution and use in source and binary forms, with or
19#     without modification, are permitted provided that the following
20#     conditions are met:
21#
22#      - Redistributions of source code must retain the above
23#        copyright notice, this list of conditions and the following
24#        disclaimer.
25#
26#      - Redistributions in binary form must reproduce the above
27#        copyright notice, this list of conditions and the following
28#        disclaimer in the documentation and/or other materials
29#        provided with the distribution.
30#
31# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
35# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
36# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
37# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38# SOFTWARE.
39#
40########################################################################
41#
42# This code is described in an Intel White-Paper:
43# "Fast SHA-512 Implementations on Intel Architecture Processors"
44#
45# To find it, surf to http://www.intel.com/p/en_US/embedded
46# and search for that title.
47#
48########################################################################
49
50#include <linux/linkage.h>
51
52.text
53
54# Virtual Registers
55# ARG1
56digest	= %rdi
57# ARG2
58msg	= %rsi
59# ARG3
60msglen	= %rdx
61T1	= %rcx
62T2	= %r8
63a_64	= %r9
64b_64	= %r10
65c_64	= %r11
66d_64	= %r12
67e_64	= %r13
68f_64	= %r14
69g_64	= %r15
70h_64	= %rbx
71tmp0	= %rax
72
73# Local variables (stack frame)
74
75# Message Schedule
76W_SIZE = 80*8
77# W[t] + K[t] | W[t+1] + K[t+1]
78WK_SIZE = 2*8
79
80frame_W = 0
81frame_WK = frame_W + W_SIZE
82frame_size = frame_WK + WK_SIZE
83
84# Useful QWORD "arrays" for simpler memory references
85# MSG, DIGEST, K_t, W_t are arrays
86# WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
87
88# Input message (arg1)
89#define MSG(i)    8*i(msg)
90
91# Output Digest (arg2)
92#define DIGEST(i) 8*i(digest)
93
94# SHA Constants (static mem)
95#define K_t(i)    8*i+K512(%rip)
96
97# Message Schedule (stack frame)
98#define W_t(i)    8*i+frame_W(%rsp)
99
100# W[t]+K[t] (stack frame)
101#define WK_2(i)   8*((i%2))+frame_WK(%rsp)
102
103.macro RotateState
104	# Rotate symbols a..h right
105	TMP   = h_64
106	h_64  = g_64
107	g_64  = f_64
108	f_64  = e_64
109	e_64  = d_64
110	d_64  = c_64
111	c_64  = b_64
112	b_64  = a_64
113	a_64  = TMP
114.endm
115
116.macro RORQ p1 p2
117	# shld is faster than ror on Sandybridge
118	shld	$(64-\p2), \p1, \p1
119.endm
120
121.macro SHA512_Round rnd
122	# Compute Round %%t
123	mov     f_64, T1          # T1 = f
124	mov     e_64, tmp0        # tmp = e
125	xor     g_64, T1          # T1 = f ^ g
126	RORQ    tmp0, 23   # 41    # tmp = e ror 23
127	and     e_64, T1          # T1 = (f ^ g) & e
128	xor     e_64, tmp0        # tmp = (e ror 23) ^ e
129	xor     g_64, T1          # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
130	idx = \rnd
131	add     WK_2(idx), T1     # W[t] + K[t] from message scheduler
132	RORQ    tmp0, 4   # 18    # tmp = ((e ror 23) ^ e) ror 4
133	xor     e_64, tmp0        # tmp = (((e ror 23) ^ e) ror 4) ^ e
134	mov     a_64, T2          # T2 = a
135	add     h_64, T1          # T1 = CH(e,f,g) + W[t] + K[t] + h
136	RORQ    tmp0, 14  # 14    # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
137	add     tmp0, T1          # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
138	mov     a_64, tmp0        # tmp = a
139	xor     c_64, T2          # T2 = a ^ c
140	and     c_64, tmp0        # tmp = a & c
141	and     b_64, T2          # T2 = (a ^ c) & b
142	xor     tmp0, T2          # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
143	mov     a_64, tmp0        # tmp = a
144	RORQ    tmp0, 5  # 39     # tmp = a ror 5
145	xor     a_64, tmp0        # tmp = (a ror 5) ^ a
146	add     T1, d_64          # e(next_state) = d + T1
147	RORQ    tmp0, 6  # 34     # tmp = ((a ror 5) ^ a) ror 6
148	xor     a_64, tmp0        # tmp = (((a ror 5) ^ a) ror 6) ^ a
149	lea     (T1, T2), h_64    # a(next_state) = T1 + Maj(a,b,c)
150	RORQ    tmp0, 28  # 28    # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
151	add     tmp0, h_64        # a(next_state) = T1 + Maj(a,b,c) S0(a)
152	RotateState
153.endm
154
155.macro SHA512_2Sched_2Round_avx rnd
156	# Compute rounds t-2 and t-1
157	# Compute message schedule QWORDS t and t+1
158
159	#   Two rounds are computed based on the values for K[t-2]+W[t-2] and
160	# K[t-1]+W[t-1] which were previously stored at WK_2 by the message
161	# scheduler.
162	#   The two new schedule QWORDS are stored at [W_t(t)] and [W_t(t+1)].
163	# They are then added to their respective SHA512 constants at
164	# [K_t(t)] and [K_t(t+1)] and stored at dqword [WK_2(t)]
165	#   For brievity, the comments following vectored instructions only refer to
166	# the first of a pair of QWORDS.
167	# Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]}
168	#   The computation of the message schedule and the rounds are tightly
169	# stitched to take advantage of instruction-level parallelism.
170
171	idx = \rnd - 2
172	vmovdqa	W_t(idx), %xmm4		# XMM4 = W[t-2]
173	idx = \rnd - 15
174	vmovdqu	W_t(idx), %xmm5		# XMM5 = W[t-15]
175	mov	f_64, T1
176	vpsrlq	$61, %xmm4, %xmm0	# XMM0 = W[t-2]>>61
177	mov	e_64, tmp0
178	vpsrlq	$1, %xmm5, %xmm6	# XMM6 = W[t-15]>>1
179	xor	g_64, T1
180	RORQ	tmp0, 23 # 41
181	vpsrlq	$19, %xmm4, %xmm1	# XMM1 = W[t-2]>>19
182	and	e_64, T1
183	xor	e_64, tmp0
184	vpxor	%xmm1, %xmm0, %xmm0	# XMM0 = W[t-2]>>61 ^ W[t-2]>>19
185	xor	g_64, T1
186	idx = \rnd
187	add	WK_2(idx), T1#
188	vpsrlq	$8, %xmm5, %xmm7	# XMM7 = W[t-15]>>8
189	RORQ	tmp0, 4 # 18
190	vpsrlq	$6, %xmm4, %xmm2	# XMM2 = W[t-2]>>6
191	xor	e_64, tmp0
192	mov	a_64, T2
193	add	h_64, T1
194	vpxor	%xmm7, %xmm6, %xmm6	# XMM6 = W[t-15]>>1 ^ W[t-15]>>8
195	RORQ	tmp0, 14 # 14
196	add	tmp0, T1
197	vpsrlq	$7, %xmm5, %xmm8	# XMM8 = W[t-15]>>7
198	mov	a_64, tmp0
199	xor	c_64, T2
200	vpsllq	$(64-61), %xmm4, %xmm3  # XMM3 = W[t-2]<<3
201	and	c_64, tmp0
202	and	b_64, T2
203	vpxor	%xmm3, %xmm2, %xmm2	# XMM2 = W[t-2]>>6 ^ W[t-2]<<3
204	xor	tmp0, T2
205	mov	a_64, tmp0
206	vpsllq	$(64-1), %xmm5, %xmm9	# XMM9 = W[t-15]<<63
207	RORQ	tmp0, 5 # 39
208	vpxor	%xmm9, %xmm8, %xmm8	# XMM8 = W[t-15]>>7 ^ W[t-15]<<63
209	xor	a_64, tmp0
210	add	T1, d_64
211	RORQ	tmp0, 6 # 34
212	xor	a_64, tmp0
213	vpxor	%xmm8, %xmm6, %xmm6	# XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^
214					#  W[t-15]>>7 ^ W[t-15]<<63
215	lea	(T1, T2), h_64
216	RORQ	tmp0, 28 # 28
217	vpsllq	$(64-19), %xmm4, %xmm4  # XMM4 = W[t-2]<<25
218	add	tmp0, h_64
219	RotateState
220	vpxor	%xmm4, %xmm0, %xmm0     # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^
221					#        W[t-2]<<25
222	mov	f_64, T1
223	vpxor	%xmm2, %xmm0, %xmm0     # XMM0 = s1(W[t-2])
224	mov	e_64, tmp0
225	xor	g_64, T1
226	idx = \rnd - 16
227	vpaddq	W_t(idx), %xmm0, %xmm0  # XMM0 = s1(W[t-2]) + W[t-16]
228	idx = \rnd - 7
229	vmovdqu	W_t(idx), %xmm1		# XMM1 = W[t-7]
230	RORQ	tmp0, 23 # 41
231	and	e_64, T1
232	xor	e_64, tmp0
233	xor	g_64, T1
234	vpsllq	$(64-8), %xmm5, %xmm5   # XMM5 = W[t-15]<<56
235	idx = \rnd + 1
236	add	WK_2(idx), T1
237	vpxor	%xmm5, %xmm6, %xmm6     # XMM6 = s0(W[t-15])
238	RORQ	tmp0, 4 # 18
239	vpaddq	%xmm6, %xmm0, %xmm0     # XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15])
240	xor	e_64, tmp0
241	vpaddq	%xmm1, %xmm0, %xmm0     # XMM0 = W[t] = s1(W[t-2]) + W[t-7] +
242					#               s0(W[t-15]) + W[t-16]
243	mov	a_64, T2
244	add	h_64, T1
245	RORQ	tmp0, 14 # 14
246	add	tmp0, T1
247	idx = \rnd
248	vmovdqa	%xmm0, W_t(idx)		# Store W[t]
249	vpaddq	K_t(idx), %xmm0, %xmm0  # Compute W[t]+K[t]
250	vmovdqa	%xmm0, WK_2(idx)	# Store W[t]+K[t] for next rounds
251	mov	a_64, tmp0
252	xor	c_64, T2
253	and	c_64, tmp0
254	and	b_64, T2
255	xor	tmp0, T2
256	mov	a_64, tmp0
257	RORQ	tmp0, 5 # 39
258	xor	a_64, tmp0
259	add	T1, d_64
260	RORQ	tmp0, 6 # 34
261	xor	a_64, tmp0
262	lea	(T1, T2), h_64
263	RORQ	tmp0, 28 # 28
264	add	tmp0, h_64
265	RotateState
266.endm
267
268########################################################################
269# void sha512_transform_avx(sha512_state *state, const u8 *data, int blocks)
270# Purpose: Updates the SHA512 digest stored at "state" with the message
271# stored in "data".
272# The size of the message pointed to by "data" must be an integer multiple
273# of SHA512 message blocks.
274# "blocks" is the message length in SHA512 blocks
275########################################################################
276SYM_FUNC_START(sha512_transform_avx)
277	test msglen, msglen
278	je nowork
279
280	# Save GPRs
281	push	%rbx
282	push	%r12
283	push	%r13
284	push	%r14
285	push	%r15
286
287	# Allocate Stack Space
288	push	%rbp
289	mov	%rsp, %rbp
290	sub     $frame_size, %rsp
291	and	$~(0x20 - 1), %rsp
292
293updateblock:
294
295	# Load state variables
296	mov     DIGEST(0), a_64
297	mov     DIGEST(1), b_64
298	mov     DIGEST(2), c_64
299	mov     DIGEST(3), d_64
300	mov     DIGEST(4), e_64
301	mov     DIGEST(5), f_64
302	mov     DIGEST(6), g_64
303	mov     DIGEST(7), h_64
304
305	t = 0
306	.rept 80/2 + 1
307	# (80 rounds) / (2 rounds/iteration) + (1 iteration)
308	# +1 iteration because the scheduler leads hashing by 1 iteration
309		.if t < 2
310			# BSWAP 2 QWORDS
311			vmovdqa  XMM_QWORD_BSWAP(%rip), %xmm1
312			vmovdqu  MSG(t), %xmm0
313			vpshufb  %xmm1, %xmm0, %xmm0    # BSWAP
314			vmovdqa  %xmm0, W_t(t) # Store Scheduled Pair
315			vpaddq   K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
316			vmovdqa  %xmm0, WK_2(t) # Store into WK for rounds
317		.elseif t < 16
318			# BSWAP 2 QWORDS# Compute 2 Rounds
319			vmovdqu  MSG(t), %xmm0
320			vpshufb  %xmm1, %xmm0, %xmm0    # BSWAP
321			SHA512_Round t-2    # Round t-2
322			vmovdqa  %xmm0, W_t(t) # Store Scheduled Pair
323			vpaddq   K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
324			SHA512_Round t-1    # Round t-1
325			vmovdqa  %xmm0, WK_2(t)# Store W[t]+K[t] into WK
326		.elseif t < 79
327			# Schedule 2 QWORDS# Compute 2 Rounds
328			SHA512_2Sched_2Round_avx t
329		.else
330			# Compute 2 Rounds
331			SHA512_Round t-2
332			SHA512_Round t-1
333		.endif
334		t = t+2
335	.endr
336
337	# Update digest
338	add     a_64, DIGEST(0)
339	add     b_64, DIGEST(1)
340	add     c_64, DIGEST(2)
341	add     d_64, DIGEST(3)
342	add     e_64, DIGEST(4)
343	add     f_64, DIGEST(5)
344	add     g_64, DIGEST(6)
345	add     h_64, DIGEST(7)
346
347	# Advance to next message block
348	add     $16*8, msg
349	dec     msglen
350	jnz     updateblock
351
352	# Restore Stack Pointer
353	mov	%rbp, %rsp
354	pop	%rbp
355
356	# Restore GPRs
357	pop	%r15
358	pop	%r14
359	pop	%r13
360	pop	%r12
361	pop	%rbx
362
363nowork:
364	RET
365SYM_FUNC_END(sha512_transform_avx)
366
367########################################################################
368### Binary Data
369
370.section	.rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16
371.align 16
372# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
373XMM_QWORD_BSWAP:
374	.octa 0x08090a0b0c0d0e0f0001020304050607
375
376# Mergeable 640-byte rodata section. This allows linker to merge the table
377# with other, exactly the same 640-byte fragment of another rodata section
378# (if such section exists).
379.section	.rodata.cst640.K512, "aM", @progbits, 640
380.align 64
381# K[t] used in SHA512 hashing
382K512:
383	.quad 0x428a2f98d728ae22,0x7137449123ef65cd
384	.quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
385	.quad 0x3956c25bf348b538,0x59f111f1b605d019
386	.quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
387	.quad 0xd807aa98a3030242,0x12835b0145706fbe
388	.quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
389	.quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
390	.quad 0x9bdc06a725c71235,0xc19bf174cf692694
391	.quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
392	.quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
393	.quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
394	.quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
395	.quad 0x983e5152ee66dfab,0xa831c66d2db43210
396	.quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
397	.quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
398	.quad 0x06ca6351e003826f,0x142929670a0e6e70
399	.quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
400	.quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
401	.quad 0x650a73548baf63de,0x766a0abb3c77b2a8
402	.quad 0x81c2c92e47edaee6,0x92722c851482353b
403	.quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
404	.quad 0xc24b8b70d0f89791,0xc76c51a30654be30
405	.quad 0xd192e819d6ef5218,0xd69906245565a910
406	.quad 0xf40e35855771202a,0x106aa07032bbd1b8
407	.quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
408	.quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
409	.quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
410	.quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
411	.quad 0x748f82ee5defb2fc,0x78a5636f43172f60
412	.quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
413	.quad 0x90befffa23631e28,0xa4506cebde82bde9
414	.quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
415	.quad 0xca273eceea26619c,0xd186b8c721c0c207
416	.quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
417	.quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
418	.quad 0x113f9804bef90dae,0x1b710b35131c471b
419	.quad 0x28db77f523047d84,0x32caab7b40c72493
420	.quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
421	.quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
422	.quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
423