1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * PowerNV setup code.
4 *
5 * Copyright 2011 IBM Corp.
6 */
7
8 #undef DEBUG
9
10 #include <linux/cpu.h>
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/tty.h>
15 #include <linux/reboot.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/seq_file.h>
21 #include <linux/of.h>
22 #include <linux/of_fdt.h>
23 #include <linux/interrupt.h>
24 #include <linux/bug.h>
25 #include <linux/pci.h>
26 #include <linux/cpufreq.h>
27 #include <linux/memblock.h>
28
29 #include <asm/machdep.h>
30 #include <asm/firmware.h>
31 #include <asm/xics.h>
32 #include <asm/xive.h>
33 #include <asm/opal.h>
34 #include <asm/kexec.h>
35 #include <asm/smp.h>
36 #include <asm/tm.h>
37 #include <asm/setup.h>
38 #include <asm/security_features.h>
39
40 #include "powernv.h"
41
42
fw_feature_is(const char * state,const char * name,struct device_node * fw_features)43 static bool __init fw_feature_is(const char *state, const char *name,
44 struct device_node *fw_features)
45 {
46 struct device_node *np;
47 bool rc = false;
48
49 np = of_get_child_by_name(fw_features, name);
50 if (np) {
51 rc = of_property_read_bool(np, state);
52 of_node_put(np);
53 }
54
55 return rc;
56 }
57
init_fw_feat_flags(struct device_node * np)58 static void __init init_fw_feat_flags(struct device_node *np)
59 {
60 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
61 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
62
63 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
64 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
65
66 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
67 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
68
69 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
70 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
71
72 if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
73 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
74
75 if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
76 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
77
78 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
79 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
80
81 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
82 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
83
84 /*
85 * The features below are enabled by default, so we instead look to see
86 * if firmware has *disabled* them, and clear them if so.
87 */
88 if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
89 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
90
91 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
92 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
93
94 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
95 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
96
97 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
98 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
99
100 if (fw_feature_is("enabled", "no-need-l1d-flush-msr-pr-1-to-0", np))
101 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
102
103 if (fw_feature_is("enabled", "no-need-l1d-flush-kernel-on-user-access", np))
104 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
105
106 if (fw_feature_is("enabled", "no-need-store-drain-on-priv-state-switch", np))
107 security_ftr_clear(SEC_FTR_STF_BARRIER);
108 }
109
pnv_setup_security_mitigations(void)110 static void __init pnv_setup_security_mitigations(void)
111 {
112 struct device_node *np, *fw_features;
113 enum l1d_flush_type type;
114 bool enable;
115
116 /* Default to fallback in case fw-features are not available */
117 type = L1D_FLUSH_FALLBACK;
118
119 np = of_find_node_by_name(NULL, "ibm,opal");
120 fw_features = of_get_child_by_name(np, "fw-features");
121 of_node_put(np);
122
123 if (fw_features) {
124 init_fw_feat_flags(fw_features);
125 of_node_put(fw_features);
126
127 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
128 type = L1D_FLUSH_MTTRIG;
129
130 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
131 type = L1D_FLUSH_ORI;
132 }
133
134 /*
135 * The issues addressed by the entry and uaccess flush don't affect P7
136 * or P8, so on bare metal disable them explicitly in case firmware does
137 * not include the features to disable them. POWER9 and newer processors
138 * should have the appropriate firmware flags.
139 */
140 if (pvr_version_is(PVR_POWER7) || pvr_version_is(PVR_POWER7p) ||
141 pvr_version_is(PVR_POWER8E) || pvr_version_is(PVR_POWER8NVL) ||
142 pvr_version_is(PVR_POWER8)) {
143 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
144 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
145 }
146
147 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
148 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \
149 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
150
151 setup_rfi_flush(type, enable);
152 setup_count_cache_flush();
153
154 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
155 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
156 setup_entry_flush(enable);
157
158 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
159 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
160 setup_uaccess_flush(enable);
161
162 setup_stf_barrier();
163 }
164
pnv_check_guarded_cores(void)165 static void __init pnv_check_guarded_cores(void)
166 {
167 struct device_node *dn;
168 int bad_count = 0;
169
170 for_each_node_by_type(dn, "cpu") {
171 if (of_property_match_string(dn, "status", "bad") >= 0)
172 bad_count++;
173 }
174
175 if (bad_count) {
176 printk(" _ _______________\n");
177 pr_cont(" | | / \\\n");
178 pr_cont(" | | | WARNING! |\n");
179 pr_cont(" | | | |\n");
180 pr_cont(" | | | It looks like |\n");
181 pr_cont(" |_| | you have %*d |\n", 3, bad_count);
182 pr_cont(" _ | guarded cores |\n");
183 pr_cont(" (_) \\_______________/\n");
184 }
185 }
186
pnv_setup_arch(void)187 static void __init pnv_setup_arch(void)
188 {
189 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
190
191 pnv_setup_security_mitigations();
192
193 /* Initialize SMP */
194 pnv_smp_init();
195
196 /* Setup RTC and NVRAM callbacks */
197 if (firmware_has_feature(FW_FEATURE_OPAL))
198 opal_nvram_init();
199
200 /* Enable NAP mode */
201 powersave_nap = 1;
202
203 pnv_check_guarded_cores();
204
205 /* XXX PMCS */
206
207 pnv_rng_init();
208 }
209
pnv_init(void)210 static void __init pnv_init(void)
211 {
212 /*
213 * Initialize the LPC bus now so that legacy serial
214 * ports can be found on it
215 */
216 opal_lpc_init();
217
218 #ifdef CONFIG_HVC_OPAL
219 if (firmware_has_feature(FW_FEATURE_OPAL))
220 hvc_opal_init_early();
221 else
222 #endif
223 add_preferred_console("hvc", 0, NULL);
224
225 #ifdef CONFIG_PPC_64S_HASH_MMU
226 if (!radix_enabled()) {
227 size_t size = sizeof(struct slb_entry) * mmu_slb_size;
228 int i;
229
230 /* Allocate per cpu area to save old slb contents during MCE */
231 for_each_possible_cpu(i) {
232 paca_ptrs[i]->mce_faulty_slbs =
233 memblock_alloc_node(size,
234 __alignof__(struct slb_entry),
235 cpu_to_node(i));
236 }
237 }
238 #endif
239 }
240
pnv_init_IRQ(void)241 static void __init pnv_init_IRQ(void)
242 {
243 /* Try using a XIVE if available, otherwise use a XICS */
244 if (!xive_native_init())
245 xics_init();
246
247 WARN_ON(!ppc_md.get_irq);
248 }
249
pnv_show_cpuinfo(struct seq_file * m)250 static void pnv_show_cpuinfo(struct seq_file *m)
251 {
252 struct device_node *root;
253 const char *model = "";
254
255 root = of_find_node_by_path("/");
256 if (root)
257 model = of_get_property(root, "model", NULL);
258 seq_printf(m, "machine\t\t: PowerNV %s\n", model);
259 if (firmware_has_feature(FW_FEATURE_OPAL))
260 seq_printf(m, "firmware\t: OPAL\n");
261 else
262 seq_printf(m, "firmware\t: BML\n");
263 of_node_put(root);
264 if (radix_enabled())
265 seq_printf(m, "MMU\t\t: Radix\n");
266 else
267 seq_printf(m, "MMU\t\t: Hash\n");
268 }
269
pnv_prepare_going_down(void)270 static void pnv_prepare_going_down(void)
271 {
272 /*
273 * Disable all notifiers from OPAL, we can't
274 * service interrupts anymore anyway
275 */
276 opal_event_shutdown();
277
278 /* Print flash update message if one is scheduled. */
279 opal_flash_update_print_message();
280
281 smp_send_stop();
282
283 hard_irq_disable();
284 }
285
pnv_restart(char * cmd)286 static void __noreturn pnv_restart(char *cmd)
287 {
288 long rc;
289
290 pnv_prepare_going_down();
291
292 do {
293 if (!cmd || !strlen(cmd))
294 rc = opal_cec_reboot();
295 else if (strcmp(cmd, "full") == 0)
296 rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL);
297 else if (strcmp(cmd, "mpipl") == 0)
298 rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL);
299 else if (strcmp(cmd, "error") == 0)
300 rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL);
301 else if (strcmp(cmd, "fast") == 0)
302 rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL);
303 else
304 rc = OPAL_UNSUPPORTED;
305
306 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
307 /* Opal is busy wait for some time and retry */
308 opal_poll_events(NULL);
309 mdelay(10);
310
311 } else if (cmd && rc) {
312 /* Unknown error while issuing reboot */
313 if (rc == OPAL_UNSUPPORTED)
314 pr_err("Unsupported '%s' reboot.\n", cmd);
315 else
316 pr_err("Unable to issue '%s' reboot. Err=%ld\n",
317 cmd, rc);
318 pr_info("Forcing a cec-reboot\n");
319 cmd = NULL;
320 rc = OPAL_BUSY;
321
322 } else if (rc != OPAL_SUCCESS) {
323 /* Unknown error while issuing cec-reboot */
324 pr_err("Unable to reboot. Err=%ld\n", rc);
325 }
326
327 } while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT);
328
329 for (;;)
330 opal_poll_events(NULL);
331 }
332
pnv_power_off(void)333 static void __noreturn pnv_power_off(void)
334 {
335 long rc = OPAL_BUSY;
336
337 pnv_prepare_going_down();
338
339 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
340 rc = opal_cec_power_down(0);
341 if (rc == OPAL_BUSY_EVENT)
342 opal_poll_events(NULL);
343 else
344 mdelay(10);
345 }
346 for (;;)
347 opal_poll_events(NULL);
348 }
349
pnv_halt(void)350 static void __noreturn pnv_halt(void)
351 {
352 pnv_power_off();
353 }
354
pnv_progress(char * s,unsigned short hex)355 static void pnv_progress(char *s, unsigned short hex)
356 {
357 }
358
pnv_shutdown(void)359 static void pnv_shutdown(void)
360 {
361 /* Let the PCI code clear up IODA tables */
362 pnv_pci_shutdown();
363
364 /*
365 * Stop OPAL activity: Unregister all OPAL interrupts so they
366 * don't fire up while we kexec and make sure all potentially
367 * DMA'ing ops are complete (such as dump retrieval).
368 */
369 opal_shutdown();
370 }
371
372 #ifdef CONFIG_KEXEC_CORE
pnv_kexec_wait_secondaries_down(void)373 static void pnv_kexec_wait_secondaries_down(void)
374 {
375 int my_cpu, i, notified = -1;
376
377 my_cpu = get_cpu();
378
379 for_each_online_cpu(i) {
380 uint8_t status;
381 int64_t rc, timeout = 1000;
382
383 if (i == my_cpu)
384 continue;
385
386 for (;;) {
387 rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
388 &status);
389 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
390 break;
391 barrier();
392 if (i != notified) {
393 printk(KERN_INFO "kexec: waiting for cpu %d "
394 "(physical %d) to enter OPAL\n",
395 i, paca_ptrs[i]->hw_cpu_id);
396 notified = i;
397 }
398
399 /*
400 * On crash secondaries might be unreachable or hung,
401 * so timeout if we've waited too long
402 * */
403 mdelay(1);
404 if (timeout-- == 0) {
405 printk(KERN_ERR "kexec: timed out waiting for "
406 "cpu %d (physical %d) to enter OPAL\n",
407 i, paca_ptrs[i]->hw_cpu_id);
408 break;
409 }
410 }
411 }
412 }
413
pnv_kexec_cpu_down(int crash_shutdown,int secondary)414 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
415 {
416 u64 reinit_flags;
417
418 if (xive_enabled())
419 xive_teardown_cpu();
420 else
421 xics_kexec_teardown_cpu(secondary);
422
423 /* On OPAL, we return all CPUs to firmware */
424 if (!firmware_has_feature(FW_FEATURE_OPAL))
425 return;
426
427 if (secondary) {
428 /* Return secondary CPUs to firmware on OPAL v3 */
429 mb();
430 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
431 mb();
432
433 /* Return the CPU to OPAL */
434 opal_return_cpu();
435 } else {
436 /* Primary waits for the secondaries to have reached OPAL */
437 pnv_kexec_wait_secondaries_down();
438
439 /* Switch XIVE back to emulation mode */
440 if (xive_enabled())
441 xive_shutdown();
442
443 /*
444 * We might be running as little-endian - now that interrupts
445 * are disabled, reset the HILE bit to big-endian so we don't
446 * take interrupts in the wrong endian later
447 *
448 * We reinit to enable both radix and hash on P9 to ensure
449 * the mode used by the next kernel is always supported.
450 */
451 reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
452 if (cpu_has_feature(CPU_FTR_ARCH_300))
453 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
454 OPAL_REINIT_CPUS_MMU_HASH;
455 opal_reinit_cpus(reinit_flags);
456 }
457 }
458 #endif /* CONFIG_KEXEC_CORE */
459
460 #ifdef CONFIG_MEMORY_HOTPLUG
pnv_memory_block_size(void)461 static unsigned long pnv_memory_block_size(void)
462 {
463 /*
464 * We map the kernel linear region with 1GB large pages on radix. For
465 * memory hot unplug to work our memory block size must be at least
466 * this size.
467 */
468 if (radix_enabled())
469 return radix_mem_block_size;
470 else
471 return 256UL * 1024 * 1024;
472 }
473 #endif
474
pnv_setup_machdep_opal(void)475 static void __init pnv_setup_machdep_opal(void)
476 {
477 ppc_md.get_boot_time = opal_get_boot_time;
478 ppc_md.restart = pnv_restart;
479 pm_power_off = pnv_power_off;
480 ppc_md.halt = pnv_halt;
481 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
482 ppc_md.machine_check_exception = opal_machine_check;
483 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
484 if (opal_check_token(OPAL_HANDLE_HMI2))
485 ppc_md.hmi_exception_early = opal_hmi_exception_early2;
486 else
487 ppc_md.hmi_exception_early = opal_hmi_exception_early;
488 ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
489 }
490
pnv_probe(void)491 static int __init pnv_probe(void)
492 {
493 if (!of_machine_is_compatible("ibm,powernv"))
494 return 0;
495
496 if (firmware_has_feature(FW_FEATURE_OPAL))
497 pnv_setup_machdep_opal();
498
499 pr_debug("PowerNV detected !\n");
500
501 pnv_init();
502
503 return 1;
504 }
505
506 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
pnv_tm_init(void)507 void __init pnv_tm_init(void)
508 {
509 if (!firmware_has_feature(FW_FEATURE_OPAL) ||
510 !pvr_version_is(PVR_POWER9) ||
511 early_cpu_has_feature(CPU_FTR_TM))
512 return;
513
514 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
515 return;
516
517 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
518 cur_cpu_spec->cpu_features |= CPU_FTR_TM;
519 /* Make sure "normal" HTM is off (it should be) */
520 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
521 /* Turn on no suspend mode, and HTM no SC */
522 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
523 PPC_FEATURE2_HTM_NOSC;
524 tm_suspend_disabled = true;
525 }
526 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
527
528 /*
529 * Returns the cpu frequency for 'cpu' in Hz. This is used by
530 * /proc/cpuinfo
531 */
pnv_get_proc_freq(unsigned int cpu)532 static unsigned long pnv_get_proc_freq(unsigned int cpu)
533 {
534 unsigned long ret_freq;
535
536 ret_freq = cpufreq_get(cpu) * 1000ul;
537
538 /*
539 * If the backend cpufreq driver does not exist,
540 * then fallback to old way of reporting the clockrate.
541 */
542 if (!ret_freq)
543 ret_freq = ppc_proc_freq;
544 return ret_freq;
545 }
546
pnv_machine_check_early(struct pt_regs * regs)547 static long pnv_machine_check_early(struct pt_regs *regs)
548 {
549 long handled = 0;
550
551 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
552 handled = cur_cpu_spec->machine_check_early(regs);
553
554 return handled;
555 }
556
define_machine(powernv)557 define_machine(powernv) {
558 .name = "PowerNV",
559 .probe = pnv_probe,
560 .setup_arch = pnv_setup_arch,
561 .init_IRQ = pnv_init_IRQ,
562 .show_cpuinfo = pnv_show_cpuinfo,
563 .get_proc_freq = pnv_get_proc_freq,
564 .discover_phbs = pnv_pci_init,
565 .progress = pnv_progress,
566 .machine_shutdown = pnv_shutdown,
567 .power_save = NULL,
568 .calibrate_decr = generic_calibrate_decr,
569 .machine_check_early = pnv_machine_check_early,
570 #ifdef CONFIG_KEXEC_CORE
571 .kexec_cpu_down = pnv_kexec_cpu_down,
572 #endif
573 #ifdef CONFIG_MEMORY_HOTPLUG
574 .memory_block_size = pnv_memory_block_size,
575 #endif
576 };
577