1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * This file contains the routines for initializing the MMU
4 * on the 4xx series of chips.
5 * -- paulus
6 *
7 * Derived from arch/ppc/mm/init.c:
8 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 *
10 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
11 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
12 * Copyright (C) 1996 Paul Mackerras
13 *
14 * Derived from "arch/i386/mm/init.c"
15 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 */
17
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/ptrace.h>
25 #include <linux/mman.h>
26 #include <linux/mm.h>
27 #include <linux/swap.h>
28 #include <linux/stddef.h>
29 #include <linux/vmalloc.h>
30 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/highmem.h>
33 #include <linux/memblock.h>
34
35 #include <asm/io.h>
36 #include <asm/mmu_context.h>
37 #include <asm/mmu.h>
38 #include <linux/uaccess.h>
39 #include <asm/smp.h>
40 #include <asm/bootx.h>
41 #include <asm/machdep.h>
42 #include <asm/setup.h>
43
44 #include <mm/mmu_decl.h>
45
46 extern int __map_without_ltlbs;
47 /*
48 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
49 */
MMU_init_hw(void)50 void __init MMU_init_hw(void)
51 {
52 /*
53 * The Zone Protection Register (ZPR) defines how protection will
54 * be applied to every page which is a member of a given zone. At
55 * present, we utilize only two of the 4xx's zones.
56 * The zone index bits (of ZSEL) in the PTE are used for software
57 * indicators, except the LSB. For user access, zone 1 is used,
58 * for kernel access, zone 0 is used. We set all but zone 1
59 * to zero, allowing only kernel access as indicated in the PTE.
60 * For zone 1, we set a 01 binary (a value of 10 will not work)
61 * to allow user access as indicated in the PTE. This also allows
62 * kernel access as indicated in the PTE.
63 */
64
65 mtspr(SPRN_ZPR, 0x10000000);
66
67 flush_instruction_cache();
68
69 /*
70 * Set up the real-mode cache parameters for the exception vector
71 * handlers (which are run in real-mode).
72 */
73
74 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
75
76 /*
77 * Cache instruction and data space where the exception
78 * vectors and the kernel live in real-mode.
79 */
80
81 mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */
82 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */
83 }
84
85 #define LARGE_PAGE_SIZE_16M (1<<24)
86 #define LARGE_PAGE_SIZE_4M (1<<22)
87
mmu_mapin_ram(unsigned long base,unsigned long top)88 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
89 {
90 unsigned long v, s, mapped;
91 phys_addr_t p;
92
93 v = KERNELBASE;
94 p = 0;
95 s = total_lowmem;
96
97 if (__map_without_ltlbs)
98 return 0;
99
100 while (s >= LARGE_PAGE_SIZE_16M) {
101 pmd_t *pmdp;
102 unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
103
104 pmdp = pmd_off_k(v);
105 *pmdp++ = __pmd(val);
106 *pmdp++ = __pmd(val);
107 *pmdp++ = __pmd(val);
108 *pmdp++ = __pmd(val);
109
110 v += LARGE_PAGE_SIZE_16M;
111 p += LARGE_PAGE_SIZE_16M;
112 s -= LARGE_PAGE_SIZE_16M;
113 }
114
115 while (s >= LARGE_PAGE_SIZE_4M) {
116 pmd_t *pmdp;
117 unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
118
119 pmdp = pmd_off_k(v);
120 *pmdp = __pmd(val);
121
122 v += LARGE_PAGE_SIZE_4M;
123 p += LARGE_PAGE_SIZE_4M;
124 s -= LARGE_PAGE_SIZE_4M;
125 }
126
127 mapped = total_lowmem - s;
128
129 /* If the size of RAM is not an exact power of two, we may not
130 * have covered RAM in its entirety with 16 and 4 MiB
131 * pages. Consequently, restrict the top end of RAM currently
132 * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
133 * coverage with normal-sized pages (or other reasons) do not
134 * attempt to allocate outside the allowed range.
135 */
136 memblock_set_current_limit(mapped);
137
138 return mapped;
139 }
140
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)141 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
142 phys_addr_t first_memblock_size)
143 {
144 /* We don't currently support the first MEMBLOCK not mapping 0
145 * physical on those processors
146 */
147 BUG_ON(first_memblock_base != 0);
148
149 /* 40x can only access 16MB at the moment (see head_40x.S) */
150 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
151 }
152