1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
4 #ifdef __KERNEL__
5
6 #define ARCH_HAS_IOREMAP_WC
7 #ifdef CONFIG_PPC32
8 #define ARCH_HAS_IOREMAP_WT
9 #endif
10
11 /*
12 */
13
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
18
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
21 /*
22 * has legacy ISA devices ?
23 */
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
25 #endif
26
27 #include <linux/device.h>
28 #include <linux/compiler.h>
29 #include <linux/mm.h>
30 #include <asm/page.h>
31 #include <asm/byteorder.h>
32 #include <asm/synch.h>
33 #include <asm/delay.h>
34 #include <asm/mmiowb.h>
35 #include <asm/mmu.h>
36 #include <asm/ppc_asm.h>
37
38 #define SIO_CONFIG_RA 0x398
39 #define SIO_CONFIG_RD 0x399
40
41 /* 32 bits uses slightly different variables for the various IO
42 * bases. Most of this file only uses _IO_BASE though which we
43 * define properly based on the platform
44 */
45 #ifndef CONFIG_PCI
46 #define _IO_BASE 0
47 #define _ISA_MEM_BASE 0
48 #define PCI_DRAM_OFFSET 0
49 #elif defined(CONFIG_PPC32)
50 #define _IO_BASE isa_io_base
51 #define _ISA_MEM_BASE isa_mem_base
52 #define PCI_DRAM_OFFSET pci_dram_offset
53 #else
54 #define _IO_BASE pci_io_base
55 #define _ISA_MEM_BASE isa_mem_base
56 #define PCI_DRAM_OFFSET 0
57 #endif
58
59 extern unsigned long isa_io_base;
60 extern unsigned long pci_io_base;
61 extern unsigned long pci_dram_offset;
62
63 extern resource_size_t isa_mem_base;
64
65 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
66 * is not set or addresses cannot be translated to MMIO. This is typically
67 * set when the platform supports "special" PIO accesses via a non memory
68 * mapped mechanism, and allows things like the early udbg UART code to
69 * function.
70 */
71 extern bool isa_io_special;
72
73 #ifdef CONFIG_PPC32
74 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
75 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
76 #endif
77 #endif
78
79 /*
80 *
81 * Low level MMIO accessors
82 *
83 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
84 * specific and thus shouldn't be used in generic code. The accessors
85 * provided here are:
86 *
87 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
88 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
89 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
90 *
91 * Those operate directly on a kernel virtual address. Note that the prototype
92 * for the out_* accessors has the arguments in opposite order from the usual
93 * linux PCI accessors. Unlike those, they take the address first and the value
94 * next.
95 *
96 * Note: I might drop the _ns suffix on the stream operations soon as it is
97 * simply normal for stream operations to not swap in the first place.
98 *
99 */
100
101 #define DEF_MMIO_IN_X(name, size, insn) \
102 static inline u##size name(const volatile u##size __iomem *addr) \
103 { \
104 u##size ret; \
105 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
106 : "=r" (ret) : "Z" (*addr) : "memory"); \
107 return ret; \
108 }
109
110 #define DEF_MMIO_OUT_X(name, size, insn) \
111 static inline void name(volatile u##size __iomem *addr, u##size val) \
112 { \
113 __asm__ __volatile__("sync;"#insn" %1,%y0" \
114 : "=Z" (*addr) : "r" (val) : "memory"); \
115 mmiowb_set_pending(); \
116 }
117
118 #define DEF_MMIO_IN_D(name, size, insn) \
119 static inline u##size name(const volatile u##size __iomem *addr) \
120 { \
121 u##size ret; \
122 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
123 : "=r" (ret) : "m<>" (*addr) : "memory"); \
124 return ret; \
125 }
126
127 #define DEF_MMIO_OUT_D(name, size, insn) \
128 static inline void name(volatile u##size __iomem *addr, u##size val) \
129 { \
130 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
131 : "=m<>" (*addr) : "r" (val) : "memory"); \
132 mmiowb_set_pending(); \
133 }
134
135 DEF_MMIO_IN_D(in_8, 8, lbz);
136 DEF_MMIO_OUT_D(out_8, 8, stb);
137
138 #ifdef __BIG_ENDIAN__
139 DEF_MMIO_IN_D(in_be16, 16, lhz);
140 DEF_MMIO_IN_D(in_be32, 32, lwz);
141 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
142 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
143
144 DEF_MMIO_OUT_D(out_be16, 16, sth);
145 DEF_MMIO_OUT_D(out_be32, 32, stw);
146 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
147 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
148 #else
149 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
150 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
151 DEF_MMIO_IN_D(in_le16, 16, lhz);
152 DEF_MMIO_IN_D(in_le32, 32, lwz);
153
154 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
155 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
156 DEF_MMIO_OUT_D(out_le16, 16, sth);
157 DEF_MMIO_OUT_D(out_le32, 32, stw);
158
159 #endif /* __BIG_ENDIAN */
160
161 #ifdef __powerpc64__
162
163 #ifdef __BIG_ENDIAN__
164 DEF_MMIO_OUT_D(out_be64, 64, std);
165 DEF_MMIO_IN_D(in_be64, 64, ld);
166
167 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)168 static inline u64 in_le64(const volatile u64 __iomem *addr)
169 {
170 return swab64(in_be64(addr));
171 }
172
out_le64(volatile u64 __iomem * addr,u64 val)173 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
174 {
175 out_be64(addr, swab64(val));
176 }
177 #else
178 DEF_MMIO_OUT_D(out_le64, 64, std);
179 DEF_MMIO_IN_D(in_le64, 64, ld);
180
181 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)182 static inline u64 in_be64(const volatile u64 __iomem *addr)
183 {
184 return swab64(in_le64(addr));
185 }
186
out_be64(volatile u64 __iomem * addr,u64 val)187 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
188 {
189 out_le64(addr, swab64(val));
190 }
191
192 #endif
193 #endif /* __powerpc64__ */
194
195 /*
196 * Low level IO stream instructions are defined out of line for now
197 */
198 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
199 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
200 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
201 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
202 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
203 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
204
205 /* The _ns naming is historical and will be removed. For now, just #define
206 * the non _ns equivalent names
207 */
208 #define _insw _insw_ns
209 #define _insl _insl_ns
210 #define _outsw _outsw_ns
211 #define _outsl _outsl_ns
212
213
214 /*
215 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
216 */
217
218 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
219 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
220 unsigned long n);
221 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
222 unsigned long n);
223
224 /*
225 *
226 * PCI and standard ISA accessors
227 *
228 * Those are globally defined linux accessors for devices on PCI or ISA
229 * busses. They follow the Linux defined semantics. The current implementation
230 * for PowerPC is as close as possible to the x86 version of these, and thus
231 * provides fairly heavy weight barriers for the non-raw versions
232 *
233 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
234 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
235 * own implementation of some or all of the accessors.
236 */
237
238 /*
239 * Include the EEH definitions when EEH is enabled only so they don't get
240 * in the way when building for 32 bits
241 */
242 #ifdef CONFIG_EEH
243 #include <asm/eeh.h>
244 #endif
245
246 /* Shortcut to the MMIO argument pointer */
247 #define PCI_IO_ADDR volatile void __iomem *
248
249 /* Indirect IO address tokens:
250 *
251 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
252 * on all MMIOs. (Note that this is all 64 bits only for now)
253 *
254 * To help platforms who may need to differentiate MMIO addresses in
255 * their hooks, a bitfield is reserved for use by the platform near the
256 * top of MMIO addresses (not PIO, those have to cope the hard way).
257 *
258 * The highest address in the kernel virtual space are:
259 *
260 * d0003fffffffffff # with Hash MMU
261 * c00fffffffffffff # with Radix MMU
262 *
263 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
264 * that can be used for the field.
265 *
266 * The direct IO mapping operations will then mask off those bits
267 * before doing the actual access, though that only happen when
268 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
269 * mechanism
270 *
271 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
272 * all PIO functions call through a hook.
273 */
274
275 #ifdef CONFIG_PPC_INDIRECT_MMIO
276 #define PCI_IO_IND_TOKEN_SHIFT 52
277 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
278 #define PCI_FIX_ADDR(addr) \
279 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
280 #define PCI_GET_ADDR_TOKEN(addr) \
281 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
282 PCI_IO_IND_TOKEN_SHIFT)
283 #define PCI_SET_ADDR_TOKEN(addr, token) \
284 do { \
285 unsigned long __a = (unsigned long)(addr); \
286 __a &= ~PCI_IO_IND_TOKEN_MASK; \
287 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
288 (addr) = (void __iomem *)__a; \
289 } while(0)
290 #else
291 #define PCI_FIX_ADDR(addr) (addr)
292 #endif
293
294
295 /*
296 * Non ordered and non-swapping "raw" accessors
297 */
298
__raw_readb(const volatile void __iomem * addr)299 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
300 {
301 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
302 }
303 #define __raw_readb __raw_readb
304
__raw_readw(const volatile void __iomem * addr)305 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
306 {
307 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
308 }
309 #define __raw_readw __raw_readw
310
__raw_readl(const volatile void __iomem * addr)311 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
312 {
313 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
314 }
315 #define __raw_readl __raw_readl
316
__raw_writeb(unsigned char v,volatile void __iomem * addr)317 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
318 {
319 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
320 }
321 #define __raw_writeb __raw_writeb
322
__raw_writew(unsigned short v,volatile void __iomem * addr)323 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
324 {
325 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
326 }
327 #define __raw_writew __raw_writew
328
__raw_writel(unsigned int v,volatile void __iomem * addr)329 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
330 {
331 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
332 }
333 #define __raw_writel __raw_writel
334
335 #ifdef __powerpc64__
__raw_readq(const volatile void __iomem * addr)336 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
337 {
338 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
339 }
340 #define __raw_readq __raw_readq
341
__raw_writeq(unsigned long v,volatile void __iomem * addr)342 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
343 {
344 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
345 }
346 #define __raw_writeq __raw_writeq
347
__raw_writeq_be(unsigned long v,volatile void __iomem * addr)348 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
349 {
350 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
351 }
352 #define __raw_writeq_be __raw_writeq_be
353
354 /*
355 * Real mode versions of the above. Those instructions are only supposed
356 * to be used in hypervisor real mode as per the architecture spec.
357 */
__raw_rm_writeb(u8 val,volatile void __iomem * paddr)358 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
359 {
360 __asm__ __volatile__(".machine push; \
361 .machine power6; \
362 stbcix %0,0,%1; \
363 .machine pop;"
364 : : "r" (val), "r" (paddr) : "memory");
365 }
366
__raw_rm_writew(u16 val,volatile void __iomem * paddr)367 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
368 {
369 __asm__ __volatile__(".machine push; \
370 .machine power6; \
371 sthcix %0,0,%1; \
372 .machine pop;"
373 : : "r" (val), "r" (paddr) : "memory");
374 }
375
__raw_rm_writel(u32 val,volatile void __iomem * paddr)376 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
377 {
378 __asm__ __volatile__(".machine push; \
379 .machine power6; \
380 stwcix %0,0,%1; \
381 .machine pop;"
382 : : "r" (val), "r" (paddr) : "memory");
383 }
384
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)385 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
386 {
387 __asm__ __volatile__(".machine push; \
388 .machine power6; \
389 stdcix %0,0,%1; \
390 .machine pop;"
391 : : "r" (val), "r" (paddr) : "memory");
392 }
393
__raw_rm_writeq_be(u64 val,volatile void __iomem * paddr)394 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
395 {
396 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
397 }
398
__raw_rm_readb(volatile void __iomem * paddr)399 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
400 {
401 u8 ret;
402 __asm__ __volatile__(".machine push; \
403 .machine power6; \
404 lbzcix %0,0, %1; \
405 .machine pop;"
406 : "=r" (ret) : "r" (paddr) : "memory");
407 return ret;
408 }
409
__raw_rm_readw(volatile void __iomem * paddr)410 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
411 {
412 u16 ret;
413 __asm__ __volatile__(".machine push; \
414 .machine power6; \
415 lhzcix %0,0, %1; \
416 .machine pop;"
417 : "=r" (ret) : "r" (paddr) : "memory");
418 return ret;
419 }
420
__raw_rm_readl(volatile void __iomem * paddr)421 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
422 {
423 u32 ret;
424 __asm__ __volatile__(".machine push; \
425 .machine power6; \
426 lwzcix %0,0, %1; \
427 .machine pop;"
428 : "=r" (ret) : "r" (paddr) : "memory");
429 return ret;
430 }
431
__raw_rm_readq(volatile void __iomem * paddr)432 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
433 {
434 u64 ret;
435 __asm__ __volatile__(".machine push; \
436 .machine power6; \
437 ldcix %0,0, %1; \
438 .machine pop;"
439 : "=r" (ret) : "r" (paddr) : "memory");
440 return ret;
441 }
442 #endif /* __powerpc64__ */
443
444 /*
445 *
446 * PCI PIO and MMIO accessors.
447 *
448 *
449 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
450 * machine checks (which they occasionally do when probing non existing
451 * IO ports on some platforms, like PowerMac and 8xx).
452 * I always found it to be of dubious reliability and I am tempted to get
453 * rid of it one of these days. So if you think it's important to keep it,
454 * please voice up asap. We never had it for 64 bits and I do not intend
455 * to port it over
456 */
457
458 #ifdef CONFIG_PPC32
459
460 #define __do_in_asm(name, op) \
461 static inline unsigned int name(unsigned int port) \
462 { \
463 unsigned int x; \
464 __asm__ __volatile__( \
465 "sync\n" \
466 "0:" op " %0,0,%1\n" \
467 "1: twi 0,%0,0\n" \
468 "2: isync\n" \
469 "3: nop\n" \
470 "4:\n" \
471 ".section .fixup,\"ax\"\n" \
472 "5: li %0,-1\n" \
473 " b 4b\n" \
474 ".previous\n" \
475 EX_TABLE(0b, 5b) \
476 EX_TABLE(1b, 5b) \
477 EX_TABLE(2b, 5b) \
478 EX_TABLE(3b, 5b) \
479 : "=&r" (x) \
480 : "r" (port + _IO_BASE) \
481 : "memory"); \
482 return x; \
483 }
484
485 #define __do_out_asm(name, op) \
486 static inline void name(unsigned int val, unsigned int port) \
487 { \
488 __asm__ __volatile__( \
489 "sync\n" \
490 "0:" op " %0,0,%1\n" \
491 "1: sync\n" \
492 "2:\n" \
493 EX_TABLE(0b, 2b) \
494 EX_TABLE(1b, 2b) \
495 : : "r" (val), "r" (port + _IO_BASE) \
496 : "memory"); \
497 }
498
499 __do_in_asm(_rec_inb, "lbzx")
500 __do_in_asm(_rec_inw, "lhbrx")
501 __do_in_asm(_rec_inl, "lwbrx")
502 __do_out_asm(_rec_outb, "stbx")
503 __do_out_asm(_rec_outw, "sthbrx")
504 __do_out_asm(_rec_outl, "stwbrx")
505
506 #endif /* CONFIG_PPC32 */
507
508 /* The "__do_*" operations below provide the actual "base" implementation
509 * for each of the defined accessors. Some of them use the out_* functions
510 * directly, some of them still use EEH, though we might change that in the
511 * future. Those macros below provide the necessary argument swapping and
512 * handling of the IO base for PIO.
513 *
514 * They are themselves used by the macros that define the actual accessors
515 * and can be used by the hooks if any.
516 *
517 * Note that PIO operations are always defined in terms of their corresonding
518 * MMIO operations. That allows platforms like iSeries who want to modify the
519 * behaviour of both to only hook on the MMIO version and get both. It's also
520 * possible to hook directly at the toplevel PIO operation if they have to
521 * be handled differently
522 */
523 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
524 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
525 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
526 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
527 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
528 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
529 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
530
531 #ifdef CONFIG_EEH
532 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
533 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
534 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
535 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
536 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
537 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
538 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
539 #else /* CONFIG_EEH */
540 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
541 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
542 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
543 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
544 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
545 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
546 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
547 #endif /* !defined(CONFIG_EEH) */
548
549 #ifdef CONFIG_PPC32
550 #define __do_outb(val, port) _rec_outb(val, port)
551 #define __do_outw(val, port) _rec_outw(val, port)
552 #define __do_outl(val, port) _rec_outl(val, port)
553 #define __do_inb(port) _rec_inb(port)
554 #define __do_inw(port) _rec_inw(port)
555 #define __do_inl(port) _rec_inl(port)
556 #else /* CONFIG_PPC32 */
557 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
558 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
559 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
560 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
561 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
562 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
563 #endif /* !CONFIG_PPC32 */
564
565 #ifdef CONFIG_EEH
566 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
567 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
568 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
569 #else /* CONFIG_EEH */
570 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
571 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
572 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
573 #endif /* !CONFIG_EEH */
574 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
575 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
576 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
577
578 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
579 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
580 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
581 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
582 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
583 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
584
585 #define __do_memset_io(addr, c, n) \
586 _memset_io(PCI_FIX_ADDR(addr), c, n)
587 #define __do_memcpy_toio(dst, src, n) \
588 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
589
590 #ifdef CONFIG_EEH
591 #define __do_memcpy_fromio(dst, src, n) \
592 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
593 #else /* CONFIG_EEH */
594 #define __do_memcpy_fromio(dst, src, n) \
595 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
596 #endif /* !CONFIG_EEH */
597
598 #ifdef CONFIG_PPC_INDIRECT_PIO
599 #define DEF_PCI_HOOK_pio(x) x
600 #else
601 #define DEF_PCI_HOOK_pio(x) NULL
602 #endif
603
604 #ifdef CONFIG_PPC_INDIRECT_MMIO
605 #define DEF_PCI_HOOK_mem(x) x
606 #else
607 #define DEF_PCI_HOOK_mem(x) NULL
608 #endif
609
610 /* Structure containing all the hooks */
611 extern struct ppc_pci_io {
612
613 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
614 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
615
616 #include <asm/io-defs.h>
617
618 #undef DEF_PCI_AC_RET
619 #undef DEF_PCI_AC_NORET
620
621 } ppc_pci_io;
622
623 /* The inline wrappers */
624 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
625 static inline ret name at \
626 { \
627 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
628 return ppc_pci_io.name al; \
629 return __do_##name al; \
630 }
631
632 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
633 static inline void name at \
634 { \
635 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
636 ppc_pci_io.name al; \
637 else \
638 __do_##name al; \
639 }
640
641 #include <asm/io-defs.h>
642
643 #undef DEF_PCI_AC_RET
644 #undef DEF_PCI_AC_NORET
645
646 /* Some drivers check for the presence of readq & writeq with
647 * a #ifdef, so we make them happy here.
648 */
649 #define readb readb
650 #define readw readw
651 #define readl readl
652 #define writeb writeb
653 #define writew writew
654 #define writel writel
655 #define readsb readsb
656 #define readsw readsw
657 #define readsl readsl
658 #define writesb writesb
659 #define writesw writesw
660 #define writesl writesl
661 #define inb inb
662 #define inw inw
663 #define inl inl
664 #define outb outb
665 #define outw outw
666 #define outl outl
667 #define insb insb
668 #define insw insw
669 #define insl insl
670 #define outsb outsb
671 #define outsw outsw
672 #define outsl outsl
673 #ifdef __powerpc64__
674 #define readq readq
675 #define writeq writeq
676 #endif
677 #define memset_io memset_io
678 #define memcpy_fromio memcpy_fromio
679 #define memcpy_toio memcpy_toio
680
681 /*
682 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
683 * access
684 */
685 #define xlate_dev_mem_ptr(p) __va(p)
686
687 /*
688 * We don't do relaxed operations yet, at least not with this semantic
689 */
690 #define readb_relaxed(addr) readb(addr)
691 #define readw_relaxed(addr) readw(addr)
692 #define readl_relaxed(addr) readl(addr)
693 #define readq_relaxed(addr) readq(addr)
694 #define writeb_relaxed(v, addr) writeb(v, addr)
695 #define writew_relaxed(v, addr) writew(v, addr)
696 #define writel_relaxed(v, addr) writel(v, addr)
697 #define writeq_relaxed(v, addr) writeq(v, addr)
698
699 #ifdef CONFIG_GENERIC_IOMAP
700 #include <asm-generic/iomap.h>
701 #else
702 /*
703 * Here comes the implementation of the IOMAP interfaces.
704 */
ioread16be(const void __iomem * addr)705 static inline unsigned int ioread16be(const void __iomem *addr)
706 {
707 return readw_be(addr);
708 }
709 #define ioread16be ioread16be
710
ioread32be(const void __iomem * addr)711 static inline unsigned int ioread32be(const void __iomem *addr)
712 {
713 return readl_be(addr);
714 }
715 #define ioread32be ioread32be
716
717 #ifdef __powerpc64__
ioread64_lo_hi(const void __iomem * addr)718 static inline u64 ioread64_lo_hi(const void __iomem *addr)
719 {
720 return readq(addr);
721 }
722 #define ioread64_lo_hi ioread64_lo_hi
723
ioread64_hi_lo(const void __iomem * addr)724 static inline u64 ioread64_hi_lo(const void __iomem *addr)
725 {
726 return readq(addr);
727 }
728 #define ioread64_hi_lo ioread64_hi_lo
729
ioread64be(const void __iomem * addr)730 static inline u64 ioread64be(const void __iomem *addr)
731 {
732 return readq_be(addr);
733 }
734 #define ioread64be ioread64be
735
ioread64be_lo_hi(const void __iomem * addr)736 static inline u64 ioread64be_lo_hi(const void __iomem *addr)
737 {
738 return readq_be(addr);
739 }
740 #define ioread64be_lo_hi ioread64be_lo_hi
741
ioread64be_hi_lo(const void __iomem * addr)742 static inline u64 ioread64be_hi_lo(const void __iomem *addr)
743 {
744 return readq_be(addr);
745 }
746 #define ioread64be_hi_lo ioread64be_hi_lo
747 #endif /* __powerpc64__ */
748
iowrite16be(u16 val,void __iomem * addr)749 static inline void iowrite16be(u16 val, void __iomem *addr)
750 {
751 writew_be(val, addr);
752 }
753 #define iowrite16be iowrite16be
754
iowrite32be(u32 val,void __iomem * addr)755 static inline void iowrite32be(u32 val, void __iomem *addr)
756 {
757 writel_be(val, addr);
758 }
759 #define iowrite32be iowrite32be
760
761 #ifdef __powerpc64__
iowrite64_lo_hi(u64 val,void __iomem * addr)762 static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
763 {
764 writeq(val, addr);
765 }
766 #define iowrite64_lo_hi iowrite64_lo_hi
767
iowrite64_hi_lo(u64 val,void __iomem * addr)768 static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
769 {
770 writeq(val, addr);
771 }
772 #define iowrite64_hi_lo iowrite64_hi_lo
773
iowrite64be(u64 val,void __iomem * addr)774 static inline void iowrite64be(u64 val, void __iomem *addr)
775 {
776 writeq_be(val, addr);
777 }
778 #define iowrite64be iowrite64be
779
iowrite64be_lo_hi(u64 val,void __iomem * addr)780 static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
781 {
782 writeq_be(val, addr);
783 }
784 #define iowrite64be_lo_hi iowrite64be_lo_hi
785
iowrite64be_hi_lo(u64 val,void __iomem * addr)786 static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
787 {
788 writeq_be(val, addr);
789 }
790 #define iowrite64be_hi_lo iowrite64be_hi_lo
791 #endif /* __powerpc64__ */
792
793 struct pci_dev;
794 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
795 #define pci_iounmap pci_iounmap
796 void __iomem *ioport_map(unsigned long port, unsigned int len);
797 #define ioport_map ioport_map
798 #endif
799
iosync(void)800 static inline void iosync(void)
801 {
802 __asm__ __volatile__ ("sync" : : : "memory");
803 }
804
805 /* Enforce in-order execution of data I/O.
806 * No distinction between read/write on PPC; use eieio for all three.
807 * Those are fairly week though. They don't provide a barrier between
808 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
809 * they only provide barriers between 2 __raw MMIO operations and
810 * possibly break write combining.
811 */
812 #define iobarrier_rw() eieio()
813 #define iobarrier_r() eieio()
814 #define iobarrier_w() eieio()
815
816
817 /*
818 * output pause versions need a delay at least for the
819 * w83c105 ide controller in a p610.
820 */
821 #define inb_p(port) inb(port)
822 #define outb_p(val, port) (udelay(1), outb((val), (port)))
823 #define inw_p(port) inw(port)
824 #define outw_p(val, port) (udelay(1), outw((val), (port)))
825 #define inl_p(port) inl(port)
826 #define outl_p(val, port) (udelay(1), outl((val), (port)))
827
828
829 #define IO_SPACE_LIMIT ~(0UL)
830
831 /**
832 * ioremap - map bus memory into CPU space
833 * @address: bus address of the memory
834 * @size: size of the resource to map
835 *
836 * ioremap performs a platform specific sequence of operations to
837 * make bus memory CPU accessible via the readb/readw/readl/writeb/
838 * writew/writel functions and the other mmio helpers. The returned
839 * address is not guaranteed to be usable directly as a virtual
840 * address.
841 *
842 * We provide a few variations of it:
843 *
844 * * ioremap is the standard one and provides non-cacheable guarded mappings
845 * and can be hooked by the platform via ppc_md
846 *
847 * * ioremap_prot allows to specify the page flags as an argument and can
848 * also be hooked by the platform via ppc_md.
849 *
850 * * ioremap_wc enables write combining
851 *
852 * * ioremap_wt enables write through
853 *
854 * * ioremap_coherent maps coherent cached memory
855 *
856 * * iounmap undoes such a mapping and can be hooked
857 *
858 * * __ioremap_caller is the same as above but takes an explicit caller
859 * reference rather than using __builtin_return_address(0)
860 *
861 */
862 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
863 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
864 unsigned long flags);
865 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
866 #define ioremap_wc ioremap_wc
867
868 #ifdef CONFIG_PPC32
869 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
870 #define ioremap_wt ioremap_wt
871 #endif
872
873 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
874 #define ioremap_uc(addr, size) ioremap((addr), (size))
875 #define ioremap_cache(addr, size) \
876 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
877
878 extern void iounmap(volatile void __iomem *addr);
879
880 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
881
882 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
883 unsigned long size, pgprot_t prot);
884 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
885 pgprot_t prot, void *caller);
886
887 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
888 pgprot_t prot, void *caller);
889
890 /*
891 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
892 * which needs some additional definitions here. They basically allow PIO
893 * space overall to be 1GB. This will work as long as we never try to use
894 * iomap to map MMIO below 1GB which should be fine on ppc64
895 */
896 #define HAVE_ARCH_PIO_SIZE 1
897 #define PIO_OFFSET 0x00000000UL
898 #define PIO_MASK (FULL_IO_SIZE - 1)
899 #define PIO_RESERVED (FULL_IO_SIZE)
900
901 #define mmio_read16be(addr) readw_be(addr)
902 #define mmio_read32be(addr) readl_be(addr)
903 #define mmio_read64be(addr) readq_be(addr)
904 #define mmio_write16be(val, addr) writew_be(val, addr)
905 #define mmio_write32be(val, addr) writel_be(val, addr)
906 #define mmio_write64be(val, addr) writeq_be(val, addr)
907 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
908 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
909 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
910 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
911 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
912 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
913
914 /**
915 * virt_to_phys - map virtual addresses to physical
916 * @address: address to remap
917 *
918 * The returned physical address is the physical (CPU) mapping for
919 * the memory address given. It is only valid to use this function on
920 * addresses directly mapped or allocated via kmalloc.
921 *
922 * This function does not give bus mappings for DMA transfers. In
923 * almost all conceivable cases a device driver should not be using
924 * this function
925 */
virt_to_phys(volatile void * address)926 static inline unsigned long virt_to_phys(volatile void * address)
927 {
928 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
929
930 return __pa((unsigned long)address);
931 }
932 #define virt_to_phys virt_to_phys
933
934 /**
935 * phys_to_virt - map physical address to virtual
936 * @address: address to remap
937 *
938 * The returned virtual address is a current CPU mapping for
939 * the memory address given. It is only valid to use this function on
940 * addresses that have a kernel mapping
941 *
942 * This function does not handle bus mappings for DMA transfers. In
943 * almost all conceivable cases a device driver should not be using
944 * this function
945 */
phys_to_virt(unsigned long address)946 static inline void * phys_to_virt(unsigned long address)
947 {
948 return (void *)__va(address);
949 }
950 #define phys_to_virt phys_to_virt
951
952 /*
953 * Change "struct page" to physical address.
954 */
page_to_phys(struct page * page)955 static inline phys_addr_t page_to_phys(struct page *page)
956 {
957 unsigned long pfn = page_to_pfn(page);
958
959 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
960
961 return PFN_PHYS(pfn);
962 }
963
964 /*
965 * 32 bits still uses virt_to_bus() for it's implementation of DMA
966 * mappings se we have to keep it defined here. We also have some old
967 * drivers (shame shame shame) that use bus_to_virt() and haven't been
968 * fixed yet so I need to define it here.
969 */
970 #ifdef CONFIG_PPC32
971
virt_to_bus(volatile void * address)972 static inline unsigned long virt_to_bus(volatile void * address)
973 {
974 if (address == NULL)
975 return 0;
976 return __pa(address) + PCI_DRAM_OFFSET;
977 }
978 #define virt_to_bus virt_to_bus
979
bus_to_virt(unsigned long address)980 static inline void * bus_to_virt(unsigned long address)
981 {
982 if (address == 0)
983 return NULL;
984 return __va(address - PCI_DRAM_OFFSET);
985 }
986 #define bus_to_virt bus_to_virt
987
988 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
989
990 #endif /* CONFIG_PPC32 */
991
992 /* access ports */
993 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
994 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
995
996 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
997 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
998
999 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
1000 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
1001
1002 /* Clear and set bits in one shot. These macros can be used to clear and
1003 * set multiple bits in a register using a single read-modify-write. These
1004 * macros can also be used to set a multiple-bit bit pattern using a mask,
1005 * by specifying the mask in the 'clear' parameter and the new bit pattern
1006 * in the 'set' parameter.
1007 */
1008
1009 #define clrsetbits(type, addr, clear, set) \
1010 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
1011
1012 #ifdef __powerpc64__
1013 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
1014 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
1015 #endif
1016
1017 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
1018 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
1019
1020 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
1021 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
1022
1023 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
1024
1025 #include <asm-generic/io.h>
1026
1027 #endif /* __KERNEL__ */
1028
1029 #endif /* _ASM_POWERPC_IO_H */
1030