1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 1995 Waldorf GmbH
7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
10  *	Author: Maciej W. Rozycki <macro@mips.com>
11  */
12 #ifndef _ASM_IO_H
13 #define _ASM_IO_H
14 
15 #define ARCH_HAS_IOREMAP_WC
16 
17 #include <linux/compiler.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/irqflags.h>
21 
22 #include <asm/addrspace.h>
23 #include <asm/barrier.h>
24 #include <asm/bug.h>
25 #include <asm/byteorder.h>
26 #include <asm/cpu.h>
27 #include <asm/cpu-features.h>
28 #include <asm-generic/iomap.h>
29 #include <asm/page.h>
30 #include <asm/pgtable-bits.h>
31 #include <asm/processor.h>
32 #include <asm/string.h>
33 #include <mangle-port.h>
34 
35 /*
36  * Raw operations are never swapped in software.  OTOH values that raw
37  * operations are working on may or may not have been swapped by the bus
38  * hardware.  An example use would be for flash memory that's used for
39  * execute in place.
40  */
41 # define __raw_ioswabb(a, x)	(x)
42 # define __raw_ioswabw(a, x)	(x)
43 # define __raw_ioswabl(a, x)	(x)
44 # define __raw_ioswabq(a, x)	(x)
45 # define ____raw_ioswabq(a, x)	(x)
46 
47 # define __relaxed_ioswabb ioswabb
48 # define __relaxed_ioswabw ioswabw
49 # define __relaxed_ioswabl ioswabl
50 # define __relaxed_ioswabq ioswabq
51 
52 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
53 
54 /*
55  * On MIPS I/O ports are memory mapped, so we access them using normal
56  * load/store instructions. mips_io_port_base is the virtual address to
57  * which all ports are being mapped.  For sake of efficiency some code
58  * assumes that this is an address that can be loaded with a single lui
59  * instruction, so the lower 16 bits must be zero.  Should be true on
60  * any sane architecture; generic code does not use this assumption.
61  */
62 extern unsigned long mips_io_port_base;
63 
set_io_port_base(unsigned long base)64 static inline void set_io_port_base(unsigned long base)
65 {
66 	mips_io_port_base = base;
67 }
68 
69 /*
70  * Provide the necessary definitions for generic iomap. We make use of
71  * mips_io_port_base for iomap(), but we don't reserve any low addresses for
72  * use with I/O ports.
73  */
74 
75 #define HAVE_ARCH_PIO_SIZE
76 #define PIO_OFFSET	mips_io_port_base
77 #define PIO_MASK	IO_SPACE_LIMIT
78 #define PIO_RESERVED	0x0UL
79 
80 /*
81  * Enforce in-order execution of data I/O.  In the MIPS architecture
82  * these are equivalent to corresponding platform-specific memory
83  * barriers defined in <asm/barrier.h>.  API pinched from PowerPC,
84  * with sync additionally defined.
85  */
86 #define iobarrier_rw() mb()
87 #define iobarrier_r() rmb()
88 #define iobarrier_w() wmb()
89 #define iobarrier_sync() iob()
90 
91 /*
92  *     virt_to_phys    -       map virtual addresses to physical
93  *     @address: address to remap
94  *
95  *     The returned physical address is the physical (CPU) mapping for
96  *     the memory address given. It is only valid to use this function on
97  *     addresses directly mapped or allocated via kmalloc.
98  *
99  *     This function does not give bus mappings for DMA transfers. In
100  *     almost all conceivable cases a device driver should not be using
101  *     this function
102  */
__virt_to_phys_nodebug(volatile const void * address)103 static inline unsigned long __virt_to_phys_nodebug(volatile const void *address)
104 {
105 	return __pa(address);
106 }
107 
108 #ifdef CONFIG_DEBUG_VIRTUAL
109 extern phys_addr_t __virt_to_phys(volatile const void *x);
110 #else
111 #define __virt_to_phys(x)	__virt_to_phys_nodebug(x)
112 #endif
113 
114 #define virt_to_phys virt_to_phys
virt_to_phys(const volatile void * x)115 static inline phys_addr_t virt_to_phys(const volatile void *x)
116 {
117 	return __virt_to_phys(x);
118 }
119 
120 /*
121  *     phys_to_virt    -       map physical address to virtual
122  *     @address: address to remap
123  *
124  *     The returned virtual address is a current CPU mapping for
125  *     the memory address given. It is only valid to use this function on
126  *     addresses that have a kernel mapping
127  *
128  *     This function does not handle bus mappings for DMA transfers. In
129  *     almost all conceivable cases a device driver should not be using
130  *     this function
131  */
phys_to_virt(unsigned long address)132 static inline void * phys_to_virt(unsigned long address)
133 {
134 	return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
135 }
136 
137 /*
138  * ISA I/O bus memory addresses are 1:1 with the physical address.
139  */
isa_virt_to_bus(volatile void * address)140 static inline unsigned long isa_virt_to_bus(volatile void *address)
141 {
142 	return virt_to_phys(address);
143 }
144 
isa_bus_to_virt(unsigned long address)145 static inline void *isa_bus_to_virt(unsigned long address)
146 {
147 	return phys_to_virt(address);
148 }
149 
150 /*
151  * However PCI ones are not necessarily 1:1 and therefore these interfaces
152  * are forbidden in portable PCI drivers.
153  *
154  * Allow them for x86 for legacy drivers, though.
155  */
156 #define virt_to_bus virt_to_phys
157 #define bus_to_virt phys_to_virt
158 
159 /*
160  * Change "struct page" to physical address.
161  */
162 #define page_to_phys(page)	((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
163 
164 void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
165 		unsigned long prot_val);
166 void iounmap(const volatile void __iomem *addr);
167 
168 /*
169  * ioremap     -   map bus memory into CPU space
170  * @offset:    bus address of the memory
171  * @size:      size of the resource to map
172  *
173  * ioremap performs a platform specific sequence of operations to
174  * make bus memory CPU accessible via the readb/readw/readl/writeb/
175  * writew/writel functions and the other mmio helpers. The returned
176  * address is not guaranteed to be usable directly as a virtual
177  * address.
178  */
179 #define ioremap(offset, size)						\
180 	ioremap_prot((offset), (size), _CACHE_UNCACHED)
181 #define ioremap_uc		ioremap
182 
183 /*
184  * ioremap_cache -	map bus memory into CPU space
185  * @offset:	    bus address of the memory
186  * @size:	    size of the resource to map
187  *
188  * ioremap_cache performs a platform specific sequence of operations to
189  * make bus memory CPU accessible via the readb/readw/readl/writeb/
190  * writew/writel functions and the other mmio helpers. The returned
191  * address is not guaranteed to be usable directly as a virtual
192  * address.
193  *
194  * This version of ioremap ensures that the memory is marked cachable by
195  * the CPU.  Also enables full write-combining.	 Useful for some
196  * memory-like regions on I/O busses.
197  */
198 #define ioremap_cache(offset, size)					\
199 	ioremap_prot((offset), (size), _page_cachable_default)
200 
201 /*
202  * ioremap_wc     -   map bus memory into CPU space
203  * @offset:    bus address of the memory
204  * @size:      size of the resource to map
205  *
206  * ioremap_wc performs a platform specific sequence of operations to
207  * make bus memory CPU accessible via the readb/readw/readl/writeb/
208  * writew/writel functions and the other mmio helpers. The returned
209  * address is not guaranteed to be usable directly as a virtual
210  * address.
211  *
212  * This version of ioremap ensures that the memory is marked uncachable
213  * but accelerated by means of write-combining feature. It is specifically
214  * useful for PCIe prefetchable windows, which may vastly improve a
215  * communications performance. If it was determined on boot stage, what
216  * CPU CCA doesn't support UCA, the method shall fall-back to the
217  * _CACHE_UNCACHED option (see cpu_probe() method).
218  */
219 #define ioremap_wc(offset, size)					\
220 	ioremap_prot((offset), (size), boot_cpu_data.writecombine)
221 
222 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
223 #define war_io_reorder_wmb()		wmb()
224 #else
225 #define war_io_reorder_wmb()		barrier()
226 #endif
227 
228 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq)	\
229 									\
230 static inline void pfx##write##bwlq(type val,				\
231 				    volatile void __iomem *mem)		\
232 {									\
233 	volatile type *__mem;						\
234 	type __val;							\
235 									\
236 	if (barrier)							\
237 		iobarrier_rw();						\
238 	else								\
239 		war_io_reorder_wmb();					\
240 									\
241 	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
242 									\
243 	__val = pfx##ioswab##bwlq(__mem, val);				\
244 									\
245 	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
246 		*__mem = __val;						\
247 	else if (cpu_has_64bits) {					\
248 		unsigned long __flags;					\
249 		type __tmp;						\
250 									\
251 		if (irq)						\
252 			local_irq_save(__flags);			\
253 		__asm__ __volatile__(					\
254 			".set	push"		"\t\t# __writeq""\n\t"	\
255 			".set	arch=r4000"			"\n\t"	\
256 			"dsll32 %L0, %L0, 0"			"\n\t"	\
257 			"dsrl32 %L0, %L0, 0"			"\n\t"	\
258 			"dsll32 %M0, %M0, 0"			"\n\t"	\
259 			"or	%L0, %L0, %M0"			"\n\t"	\
260 			"sd	%L0, %2"			"\n\t"	\
261 			".set	pop"				"\n"	\
262 			: "=r" (__tmp)					\
263 			: "0" (__val), "m" (*__mem));			\
264 		if (irq)						\
265 			local_irq_restore(__flags);			\
266 	} else								\
267 		BUG();							\
268 }									\
269 									\
270 static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
271 {									\
272 	volatile type *__mem;						\
273 	type __val;							\
274 									\
275 	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
276 									\
277 	if (barrier)							\
278 		iobarrier_rw();						\
279 									\
280 	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
281 		__val = *__mem;						\
282 	else if (cpu_has_64bits) {					\
283 		unsigned long __flags;					\
284 									\
285 		if (irq)						\
286 			local_irq_save(__flags);			\
287 		__asm__ __volatile__(					\
288 			".set	push"		"\t\t# __readq" "\n\t"	\
289 			".set	arch=r4000"			"\n\t"	\
290 			"ld	%L0, %1"			"\n\t"	\
291 			"dsra32 %M0, %L0, 0"			"\n\t"	\
292 			"sll	%L0, %L0, 0"			"\n\t"	\
293 			".set	pop"				"\n"	\
294 			: "=r" (__val)					\
295 			: "m" (*__mem));				\
296 		if (irq)						\
297 			local_irq_restore(__flags);			\
298 	} else {							\
299 		__val = 0;						\
300 		BUG();							\
301 	}								\
302 									\
303 	/* prevent prefetching of coherent DMA data prematurely */	\
304 	if (!relax)							\
305 		rmb();							\
306 	return pfx##ioswab##bwlq(__mem, __val);				\
307 }
308 
309 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p)	\
310 									\
311 static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
312 {									\
313 	volatile type *__addr;						\
314 	type __val;							\
315 									\
316 	if (barrier)							\
317 		iobarrier_rw();						\
318 	else								\
319 		war_io_reorder_wmb();					\
320 									\
321 	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
322 									\
323 	__val = pfx##ioswab##bwlq(__addr, val);				\
324 									\
325 	/* Really, we want this to be atomic */				\
326 	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
327 									\
328 	*__addr = __val;						\
329 }									\
330 									\
331 static inline type pfx##in##bwlq##p(unsigned long port)			\
332 {									\
333 	volatile type *__addr;						\
334 	type __val;							\
335 									\
336 	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
337 									\
338 	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
339 									\
340 	if (barrier)							\
341 		iobarrier_rw();						\
342 									\
343 	__val = *__addr;						\
344 									\
345 	/* prevent prefetching of coherent DMA data prematurely */	\
346 	if (!relax)							\
347 		rmb();							\
348 	return pfx##ioswab##bwlq(__addr, __val);			\
349 }
350 
351 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax)			\
352 									\
353 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
354 
355 #define BUILDIO_MEM(bwlq, type)						\
356 									\
357 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0)				\
358 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1)				\
359 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0)				\
360 __BUILD_MEMORY_PFX(, bwlq, type, 0)
361 
BUILDIO_MEM(b,u8)362 BUILDIO_MEM(b, u8)
363 BUILDIO_MEM(w, u16)
364 BUILDIO_MEM(l, u32)
365 #ifdef CONFIG_64BIT
366 BUILDIO_MEM(q, u64)
367 #else
368 __BUILD_MEMORY_PFX(__raw_, q, u64, 0)
369 __BUILD_MEMORY_PFX(__mem_, q, u64, 0)
370 #endif
371 
372 #define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
373 	__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,)			\
374 	__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
375 
376 #define BUILDIO_IOPORT(bwlq, type)					\
377 	__BUILD_IOPORT_PFX(, bwlq, type)				\
378 	__BUILD_IOPORT_PFX(__mem_, bwlq, type)
379 
380 BUILDIO_IOPORT(b, u8)
381 BUILDIO_IOPORT(w, u16)
382 BUILDIO_IOPORT(l, u32)
383 #ifdef CONFIG_64BIT
384 BUILDIO_IOPORT(q, u64)
385 #endif
386 
387 #define __BUILDIO(bwlq, type)						\
388 									\
389 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
390 
391 __BUILDIO(q, u64)
392 
393 #define readb_relaxed			__relaxed_readb
394 #define readw_relaxed			__relaxed_readw
395 #define readl_relaxed			__relaxed_readl
396 #ifdef CONFIG_64BIT
397 #define readq_relaxed			__relaxed_readq
398 #endif
399 
400 #define writeb_relaxed			__relaxed_writeb
401 #define writew_relaxed			__relaxed_writew
402 #define writel_relaxed			__relaxed_writel
403 #ifdef CONFIG_64BIT
404 #define writeq_relaxed			__relaxed_writeq
405 #endif
406 
407 #define readb_be(addr)							\
408 	__raw_readb((__force unsigned *)(addr))
409 #define readw_be(addr)							\
410 	be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
411 #define readl_be(addr)							\
412 	be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
413 #define readq_be(addr)							\
414 	be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
415 
416 #define writeb_be(val, addr)						\
417 	__raw_writeb((val), (__force unsigned *)(addr))
418 #define writew_be(val, addr)						\
419 	__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
420 #define writel_be(val, addr)						\
421 	__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
422 #define writeq_be(val, addr)						\
423 	__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
424 
425 /*
426  * Some code tests for these symbols
427  */
428 #ifdef CONFIG_64BIT
429 #define readq				readq
430 #define writeq				writeq
431 #endif
432 
433 #define __BUILD_MEMORY_STRING(bwlq, type)				\
434 									\
435 static inline void writes##bwlq(volatile void __iomem *mem,		\
436 				const void *addr, unsigned int count)	\
437 {									\
438 	const volatile type *__addr = addr;				\
439 									\
440 	while (count--) {						\
441 		__mem_write##bwlq(*__addr, mem);			\
442 		__addr++;						\
443 	}								\
444 }									\
445 									\
446 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
447 			       unsigned int count)			\
448 {									\
449 	volatile type *__addr = addr;					\
450 									\
451 	while (count--) {						\
452 		*__addr = __mem_read##bwlq(mem);			\
453 		__addr++;						\
454 	}								\
455 }
456 
457 #define __BUILD_IOPORT_STRING(bwlq, type)				\
458 									\
459 static inline void outs##bwlq(unsigned long port, const void *addr,	\
460 			      unsigned int count)			\
461 {									\
462 	const volatile type *__addr = addr;				\
463 									\
464 	while (count--) {						\
465 		__mem_out##bwlq(*__addr, port);				\
466 		__addr++;						\
467 	}								\
468 }									\
469 									\
470 static inline void ins##bwlq(unsigned long port, void *addr,		\
471 			     unsigned int count)			\
472 {									\
473 	volatile type *__addr = addr;					\
474 									\
475 	while (count--) {						\
476 		*__addr = __mem_in##bwlq(port);				\
477 		__addr++;						\
478 	}								\
479 }
480 
481 #define BUILDSTRING(bwlq, type)						\
482 									\
483 __BUILD_MEMORY_STRING(bwlq, type)					\
484 __BUILD_IOPORT_STRING(bwlq, type)
485 
486 BUILDSTRING(b, u8)
487 BUILDSTRING(w, u16)
488 BUILDSTRING(l, u32)
489 #ifdef CONFIG_64BIT
490 BUILDSTRING(q, u64)
491 #endif
492 
493 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
494 {
495 	memset((void __force *) addr, val, count);
496 }
memcpy_fromio(void * dst,const volatile void __iomem * src,int count)497 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
498 {
499 	memcpy(dst, (void __force *) src, count);
500 }
memcpy_toio(volatile void __iomem * dst,const void * src,int count)501 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
502 {
503 	memcpy((void __force *) dst, src, count);
504 }
505 
506 /*
507  * The caches on some architectures aren't dma-coherent and have need to
508  * handle this in software.  There are three types of operations that
509  * can be applied to dma buffers.
510  *
511  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
512  *    writing the content of the caches back to memory, if necessary.
513  *    The function also invalidates the affected part of the caches as
514  *    necessary before DMA transfers from outside to memory.
515  *  - dma_cache_wback(start, size) makes caches and coherent by
516  *    writing the content of the caches back to memory, if necessary.
517  *    The function also invalidates the affected part of the caches as
518  *    necessary before DMA transfers from outside to memory.
519  *  - dma_cache_inv(start, size) invalidates the affected parts of the
520  *    caches.  Dirty lines of the caches may be written back or simply
521  *    be discarded.  This operation is necessary before dma operations
522  *    to the memory.
523  *
524  * This API used to be exported; it now is for arch code internal use only.
525  */
526 #ifdef CONFIG_DMA_NONCOHERENT
527 
528 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
529 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
530 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
531 
532 #define dma_cache_wback_inv(start, size)	_dma_cache_wback_inv(start, size)
533 #define dma_cache_wback(start, size)		_dma_cache_wback(start, size)
534 #define dma_cache_inv(start, size)		_dma_cache_inv(start, size)
535 
536 #else /* Sane hardware */
537 
538 #define dma_cache_wback_inv(start,size) \
539 	do { (void) (start); (void) (size); } while (0)
540 #define dma_cache_wback(start,size)	\
541 	do { (void) (start); (void) (size); } while (0)
542 #define dma_cache_inv(start,size)	\
543 	do { (void) (start); (void) (size); } while (0)
544 
545 #endif /* CONFIG_DMA_NONCOHERENT */
546 
547 /*
548  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
549  * Avoid interrupt mucking, just adjust the address for 4-byte access.
550  * Assume the addresses are 8-byte aligned.
551  */
552 #ifdef __MIPSEB__
553 #define __CSR_32_ADJUST 4
554 #else
555 #define __CSR_32_ADJUST 0
556 #endif
557 
558 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
559 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
560 
561 /*
562  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
563  * access
564  */
565 #define xlate_dev_mem_ptr(p)	__va(p)
566 
567 void __ioread64_copy(void *to, const void __iomem *from, size_t count);
568 
569 #endif /* _ASM_IO_H */
570