1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,apr.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 clock-output-names = "xo_board"; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <32764>; 33 clock-output-names = "sleep_clk"; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 cpu-idle-states = <&CPU_SLEEP_0>; 47 capacity-dmips-mhz = <1024>; 48 clocks = <&kryocc 0>; 49 operating-points-v2 = <&cluster0_opp>; 50 #cooling-cells = <2>; 51 next-level-cache = <&L2_0>; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 CPU1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "qcom,kryo"; 61 reg = <0x0 0x1>; 62 enable-method = "psci"; 63 cpu-idle-states = <&CPU_SLEEP_0>; 64 capacity-dmips-mhz = <1024>; 65 clocks = <&kryocc 0>; 66 operating-points-v2 = <&cluster0_opp>; 67 #cooling-cells = <2>; 68 next-level-cache = <&L2_0>; 69 }; 70 71 CPU2: cpu@100 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo"; 74 reg = <0x0 0x100>; 75 enable-method = "psci"; 76 cpu-idle-states = <&CPU_SLEEP_0>; 77 capacity-dmips-mhz = <1024>; 78 clocks = <&kryocc 1>; 79 operating-points-v2 = <&cluster1_opp>; 80 #cooling-cells = <2>; 81 next-level-cache = <&L2_1>; 82 L2_1: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 }; 86 }; 87 88 CPU3: cpu@101 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo"; 91 reg = <0x0 0x101>; 92 enable-method = "psci"; 93 cpu-idle-states = <&CPU_SLEEP_0>; 94 capacity-dmips-mhz = <1024>; 95 clocks = <&kryocc 1>; 96 operating-points-v2 = <&cluster1_opp>; 97 #cooling-cells = <2>; 98 next-level-cache = <&L2_1>; 99 }; 100 101 cpu-map { 102 cluster0 { 103 core0 { 104 cpu = <&CPU0>; 105 }; 106 107 core1 { 108 cpu = <&CPU1>; 109 }; 110 }; 111 112 cluster1 { 113 core0 { 114 cpu = <&CPU2>; 115 }; 116 117 core1 { 118 cpu = <&CPU3>; 119 }; 120 }; 121 }; 122 123 idle-states { 124 entry-method = "psci"; 125 126 CPU_SLEEP_0: cpu-sleep-0 { 127 compatible = "arm,idle-state"; 128 idle-state-name = "standalone-power-collapse"; 129 arm,psci-suspend-param = <0x00000004>; 130 entry-latency-us = <130>; 131 exit-latency-us = <80>; 132 min-residency-us = <300>; 133 }; 134 }; 135 }; 136 137 cluster0_opp: opp-table-cluster0 { 138 compatible = "operating-points-v2-kryo-cpu"; 139 nvmem-cells = <&speedbin_efuse>; 140 opp-shared; 141 142 /* Nominal fmax for now */ 143 opp-307200000 { 144 opp-hz = /bits/ 64 <307200000>; 145 opp-supported-hw = <0x77>; 146 clock-latency-ns = <200000>; 147 }; 148 opp-422400000 { 149 opp-hz = /bits/ 64 <422400000>; 150 opp-supported-hw = <0x77>; 151 clock-latency-ns = <200000>; 152 }; 153 opp-480000000 { 154 opp-hz = /bits/ 64 <480000000>; 155 opp-supported-hw = <0x77>; 156 clock-latency-ns = <200000>; 157 }; 158 opp-556800000 { 159 opp-hz = /bits/ 64 <556800000>; 160 opp-supported-hw = <0x77>; 161 clock-latency-ns = <200000>; 162 }; 163 opp-652800000 { 164 opp-hz = /bits/ 64 <652800000>; 165 opp-supported-hw = <0x77>; 166 clock-latency-ns = <200000>; 167 }; 168 opp-729600000 { 169 opp-hz = /bits/ 64 <729600000>; 170 opp-supported-hw = <0x77>; 171 clock-latency-ns = <200000>; 172 }; 173 opp-844800000 { 174 opp-hz = /bits/ 64 <844800000>; 175 opp-supported-hw = <0x77>; 176 clock-latency-ns = <200000>; 177 }; 178 opp-960000000 { 179 opp-hz = /bits/ 64 <960000000>; 180 opp-supported-hw = <0x77>; 181 clock-latency-ns = <200000>; 182 }; 183 opp-1036800000 { 184 opp-hz = /bits/ 64 <1036800000>; 185 opp-supported-hw = <0x77>; 186 clock-latency-ns = <200000>; 187 }; 188 opp-1113600000 { 189 opp-hz = /bits/ 64 <1113600000>; 190 opp-supported-hw = <0x77>; 191 clock-latency-ns = <200000>; 192 }; 193 opp-1190400000 { 194 opp-hz = /bits/ 64 <1190400000>; 195 opp-supported-hw = <0x77>; 196 clock-latency-ns = <200000>; 197 }; 198 opp-1228800000 { 199 opp-hz = /bits/ 64 <1228800000>; 200 opp-supported-hw = <0x77>; 201 clock-latency-ns = <200000>; 202 }; 203 opp-1324800000 { 204 opp-hz = /bits/ 64 <1324800000>; 205 opp-supported-hw = <0x77>; 206 clock-latency-ns = <200000>; 207 }; 208 opp-1401600000 { 209 opp-hz = /bits/ 64 <1401600000>; 210 opp-supported-hw = <0x77>; 211 clock-latency-ns = <200000>; 212 }; 213 opp-1478400000 { 214 opp-hz = /bits/ 64 <1478400000>; 215 opp-supported-hw = <0x77>; 216 clock-latency-ns = <200000>; 217 }; 218 opp-1593600000 { 219 opp-hz = /bits/ 64 <1593600000>; 220 opp-supported-hw = <0x77>; 221 clock-latency-ns = <200000>; 222 }; 223 }; 224 225 cluster1_opp: opp-table-cluster1 { 226 compatible = "operating-points-v2-kryo-cpu"; 227 nvmem-cells = <&speedbin_efuse>; 228 opp-shared; 229 230 /* Nominal fmax for now */ 231 opp-307200000 { 232 opp-hz = /bits/ 64 <307200000>; 233 opp-supported-hw = <0x77>; 234 clock-latency-ns = <200000>; 235 }; 236 opp-403200000 { 237 opp-hz = /bits/ 64 <403200000>; 238 opp-supported-hw = <0x77>; 239 clock-latency-ns = <200000>; 240 }; 241 opp-480000000 { 242 opp-hz = /bits/ 64 <480000000>; 243 opp-supported-hw = <0x77>; 244 clock-latency-ns = <200000>; 245 }; 246 opp-556800000 { 247 opp-hz = /bits/ 64 <556800000>; 248 opp-supported-hw = <0x77>; 249 clock-latency-ns = <200000>; 250 }; 251 opp-652800000 { 252 opp-hz = /bits/ 64 <652800000>; 253 opp-supported-hw = <0x77>; 254 clock-latency-ns = <200000>; 255 }; 256 opp-729600000 { 257 opp-hz = /bits/ 64 <729600000>; 258 opp-supported-hw = <0x77>; 259 clock-latency-ns = <200000>; 260 }; 261 opp-806400000 { 262 opp-hz = /bits/ 64 <806400000>; 263 opp-supported-hw = <0x77>; 264 clock-latency-ns = <200000>; 265 }; 266 opp-883200000 { 267 opp-hz = /bits/ 64 <883200000>; 268 opp-supported-hw = <0x77>; 269 clock-latency-ns = <200000>; 270 }; 271 opp-940800000 { 272 opp-hz = /bits/ 64 <940800000>; 273 opp-supported-hw = <0x77>; 274 clock-latency-ns = <200000>; 275 }; 276 opp-1036800000 { 277 opp-hz = /bits/ 64 <1036800000>; 278 opp-supported-hw = <0x77>; 279 clock-latency-ns = <200000>; 280 }; 281 opp-1113600000 { 282 opp-hz = /bits/ 64 <1113600000>; 283 opp-supported-hw = <0x77>; 284 clock-latency-ns = <200000>; 285 }; 286 opp-1190400000 { 287 opp-hz = /bits/ 64 <1190400000>; 288 opp-supported-hw = <0x77>; 289 clock-latency-ns = <200000>; 290 }; 291 opp-1248000000 { 292 opp-hz = /bits/ 64 <1248000000>; 293 opp-supported-hw = <0x77>; 294 clock-latency-ns = <200000>; 295 }; 296 opp-1324800000 { 297 opp-hz = /bits/ 64 <1324800000>; 298 opp-supported-hw = <0x77>; 299 clock-latency-ns = <200000>; 300 }; 301 opp-1401600000 { 302 opp-hz = /bits/ 64 <1401600000>; 303 opp-supported-hw = <0x77>; 304 clock-latency-ns = <200000>; 305 }; 306 opp-1478400000 { 307 opp-hz = /bits/ 64 <1478400000>; 308 opp-supported-hw = <0x77>; 309 clock-latency-ns = <200000>; 310 }; 311 opp-1555200000 { 312 opp-hz = /bits/ 64 <1555200000>; 313 opp-supported-hw = <0x77>; 314 clock-latency-ns = <200000>; 315 }; 316 opp-1632000000 { 317 opp-hz = /bits/ 64 <1632000000>; 318 opp-supported-hw = <0x77>; 319 clock-latency-ns = <200000>; 320 }; 321 opp-1708800000 { 322 opp-hz = /bits/ 64 <1708800000>; 323 opp-supported-hw = <0x77>; 324 clock-latency-ns = <200000>; 325 }; 326 opp-1785600000 { 327 opp-hz = /bits/ 64 <1785600000>; 328 opp-supported-hw = <0x77>; 329 clock-latency-ns = <200000>; 330 }; 331 opp-1824000000 { 332 opp-hz = /bits/ 64 <1824000000>; 333 opp-supported-hw = <0x77>; 334 clock-latency-ns = <200000>; 335 }; 336 opp-1920000000 { 337 opp-hz = /bits/ 64 <1920000000>; 338 opp-supported-hw = <0x77>; 339 clock-latency-ns = <200000>; 340 }; 341 opp-1996800000 { 342 opp-hz = /bits/ 64 <1996800000>; 343 opp-supported-hw = <0x77>; 344 clock-latency-ns = <200000>; 345 }; 346 opp-2073600000 { 347 opp-hz = /bits/ 64 <2073600000>; 348 opp-supported-hw = <0x77>; 349 clock-latency-ns = <200000>; 350 }; 351 opp-2150400000 { 352 opp-hz = /bits/ 64 <2150400000>; 353 opp-supported-hw = <0x77>; 354 clock-latency-ns = <200000>; 355 }; 356 }; 357 358 firmware { 359 scm { 360 compatible = "qcom,scm-msm8996"; 361 qcom,dload-mode = <&tcsr 0x13000>; 362 }; 363 }; 364 365 tcsr_mutex: hwlock { 366 compatible = "qcom,tcsr-mutex"; 367 syscon = <&tcsr_mutex_regs 0 0x1000>; 368 #hwlock-cells = <1>; 369 }; 370 371 memory@80000000 { 372 device_type = "memory"; 373 /* We expect the bootloader to fill in the reg */ 374 reg = <0x0 0x80000000 0x0 0x0>; 375 }; 376 377 psci { 378 compatible = "arm,psci-1.0"; 379 method = "smc"; 380 }; 381 382 reserved-memory { 383 #address-cells = <2>; 384 #size-cells = <2>; 385 ranges; 386 387 hyp_mem: memory@85800000 { 388 reg = <0x0 0x85800000 0x0 0x600000>; 389 no-map; 390 }; 391 392 xbl_mem: memory@85e00000 { 393 reg = <0x0 0x85e00000 0x0 0x200000>; 394 no-map; 395 }; 396 397 smem_mem: smem-mem@86000000 { 398 reg = <0x0 0x86000000 0x0 0x200000>; 399 no-map; 400 }; 401 402 tz_mem: memory@86200000 { 403 reg = <0x0 0x86200000 0x0 0x2600000>; 404 no-map; 405 }; 406 407 rmtfs_mem: rmtfs { 408 compatible = "qcom,rmtfs-mem"; 409 410 size = <0x0 0x200000>; 411 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 412 no-map; 413 414 qcom,client-id = <1>; 415 qcom,vmid = <15>; 416 }; 417 418 mpss_mem: mpss@88800000 { 419 reg = <0x0 0x88800000 0x0 0x6200000>; 420 no-map; 421 }; 422 423 adsp_mem: adsp@8ea00000 { 424 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 425 no-map; 426 }; 427 428 slpi_mem: slpi@90500000 { 429 reg = <0x0 0x90500000 0x0 0xa00000>; 430 no-map; 431 }; 432 433 gpu_mem: gpu@90f00000 { 434 compatible = "shared-dma-pool"; 435 reg = <0x0 0x90f00000 0x0 0x100000>; 436 no-map; 437 }; 438 439 venus_mem: venus@91000000 { 440 reg = <0x0 0x91000000 0x0 0x500000>; 441 no-map; 442 }; 443 444 mba_mem: mba@91500000 { 445 reg = <0x0 0x91500000 0x0 0x200000>; 446 no-map; 447 }; 448 }; 449 450 rpm-glink { 451 compatible = "qcom,glink-rpm"; 452 453 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 454 455 qcom,rpm-msg-ram = <&rpm_msg_ram>; 456 457 mboxes = <&apcs_glb 0>; 458 459 rpm_requests: rpm-requests { 460 compatible = "qcom,rpm-msm8996"; 461 qcom,glink-channels = "rpm_requests"; 462 463 rpmcc: qcom,rpmcc { 464 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 465 #clock-cells = <1>; 466 }; 467 468 rpmpd: power-controller { 469 compatible = "qcom,msm8996-rpmpd"; 470 #power-domain-cells = <1>; 471 operating-points-v2 = <&rpmpd_opp_table>; 472 473 rpmpd_opp_table: opp-table { 474 compatible = "operating-points-v2"; 475 476 rpmpd_opp1: opp1 { 477 opp-level = <1>; 478 }; 479 480 rpmpd_opp2: opp2 { 481 opp-level = <2>; 482 }; 483 484 rpmpd_opp3: opp3 { 485 opp-level = <3>; 486 }; 487 488 rpmpd_opp4: opp4 { 489 opp-level = <4>; 490 }; 491 492 rpmpd_opp5: opp5 { 493 opp-level = <5>; 494 }; 495 496 rpmpd_opp6: opp6 { 497 opp-level = <6>; 498 }; 499 }; 500 }; 501 }; 502 }; 503 504 smem { 505 compatible = "qcom,smem"; 506 memory-region = <&smem_mem>; 507 hwlocks = <&tcsr_mutex 3>; 508 }; 509 510 smp2p-adsp { 511 compatible = "qcom,smp2p"; 512 qcom,smem = <443>, <429>; 513 514 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 515 516 mboxes = <&apcs_glb 10>; 517 518 qcom,local-pid = <0>; 519 qcom,remote-pid = <2>; 520 521 adsp_smp2p_out: master-kernel { 522 qcom,entry-name = "master-kernel"; 523 #qcom,smem-state-cells = <1>; 524 }; 525 526 adsp_smp2p_in: slave-kernel { 527 qcom,entry-name = "slave-kernel"; 528 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 }; 532 }; 533 534 smp2p-mpss { 535 compatible = "qcom,smp2p"; 536 qcom,smem = <435>, <428>; 537 538 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 539 540 mboxes = <&apcs_glb 14>; 541 542 qcom,local-pid = <0>; 543 qcom,remote-pid = <1>; 544 545 mpss_smp2p_out: master-kernel { 546 qcom,entry-name = "master-kernel"; 547 #qcom,smem-state-cells = <1>; 548 }; 549 550 mpss_smp2p_in: slave-kernel { 551 qcom,entry-name = "slave-kernel"; 552 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 }; 556 }; 557 558 smp2p-slpi { 559 compatible = "qcom,smp2p"; 560 qcom,smem = <481>, <430>; 561 562 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 563 564 mboxes = <&apcs_glb 26>; 565 566 qcom,local-pid = <0>; 567 qcom,remote-pid = <3>; 568 569 slpi_smp2p_out: master-kernel { 570 qcom,entry-name = "master-kernel"; 571 #qcom,smem-state-cells = <1>; 572 }; 573 574 slpi_smp2p_in: slave-kernel { 575 qcom,entry-name = "slave-kernel"; 576 577 interrupt-controller; 578 #interrupt-cells = <2>; 579 }; 580 }; 581 582 soc: soc { 583 #address-cells = <1>; 584 #size-cells = <1>; 585 ranges = <0 0 0 0xffffffff>; 586 compatible = "simple-bus"; 587 588 pcie_phy: phy@34000 { 589 compatible = "qcom,msm8996-qmp-pcie-phy"; 590 reg = <0x00034000 0x488>; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges; 594 595 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 596 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 597 <&gcc GCC_PCIE_CLKREF_CLK>; 598 clock-names = "aux", "cfg_ahb", "ref"; 599 600 resets = <&gcc GCC_PCIE_PHY_BCR>, 601 <&gcc GCC_PCIE_PHY_COM_BCR>, 602 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 603 reset-names = "phy", "common", "cfg"; 604 status = "disabled"; 605 606 pciephy_0: phy@35000 { 607 reg = <0x00035000 0x130>, 608 <0x00035200 0x200>, 609 <0x00035400 0x1dc>; 610 #phy-cells = <0>; 611 612 #clock-cells = <0>; 613 clock-output-names = "pcie_0_pipe_clk_src"; 614 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 615 clock-names = "pipe0"; 616 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 617 reset-names = "lane0"; 618 }; 619 620 pciephy_1: phy@36000 { 621 reg = <0x00036000 0x130>, 622 <0x00036200 0x200>, 623 <0x00036400 0x1dc>; 624 #phy-cells = <0>; 625 626 #clock-cells = <0>; 627 clock-output-names = "pcie_1_pipe_clk_src"; 628 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 629 clock-names = "pipe1"; 630 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 631 reset-names = "lane1"; 632 }; 633 634 pciephy_2: phy@37000 { 635 reg = <0x00037000 0x130>, 636 <0x00037200 0x200>, 637 <0x00037400 0x1dc>; 638 #phy-cells = <0>; 639 640 #clock-cells = <0>; 641 clock-output-names = "pcie_2_pipe_clk_src"; 642 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 643 clock-names = "pipe2"; 644 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 645 reset-names = "lane2"; 646 }; 647 }; 648 649 rpm_msg_ram: sram@68000 { 650 compatible = "qcom,rpm-msg-ram"; 651 reg = <0x00068000 0x6000>; 652 }; 653 654 qfprom@74000 { 655 compatible = "qcom,qfprom"; 656 reg = <0x00074000 0x8ff>; 657 #address-cells = <1>; 658 #size-cells = <1>; 659 660 qusb2p_hstx_trim: hstx_trim@24e { 661 reg = <0x24e 0x2>; 662 bits = <5 4>; 663 }; 664 665 qusb2s_hstx_trim: hstx_trim@24f { 666 reg = <0x24f 0x1>; 667 bits = <1 4>; 668 }; 669 670 speedbin_efuse: speedbin@133 { 671 reg = <0x133 0x1>; 672 bits = <5 3>; 673 }; 674 }; 675 676 rng: rng@83000 { 677 compatible = "qcom,prng-ee"; 678 reg = <0x00083000 0x1000>; 679 clocks = <&gcc GCC_PRNG_AHB_CLK>; 680 clock-names = "core"; 681 }; 682 683 gcc: clock-controller@300000 { 684 compatible = "qcom,gcc-msm8996"; 685 #clock-cells = <1>; 686 #reset-cells = <1>; 687 #power-domain-cells = <1>; 688 reg = <0x00300000 0x90000>; 689 690 clocks = <&rpmcc RPM_SMD_BB_CLK1>, 691 <&rpmcc RPM_SMD_LN_BB_CLK>, 692 <&sleep_clk>; 693 clock-names = "cxo", "cxo2", "sleep_clk"; 694 }; 695 696 tsens0: thermal-sensor@4a9000 { 697 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 698 reg = <0x004a9000 0x1000>, /* TM */ 699 <0x004a8000 0x1000>; /* SROT */ 700 #qcom,sensors = <13>; 701 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "uplow", "critical"; 704 #thermal-sensor-cells = <1>; 705 }; 706 707 tsens1: thermal-sensor@4ad000 { 708 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 709 reg = <0x004ad000 0x1000>, /* TM */ 710 <0x004ac000 0x1000>; /* SROT */ 711 #qcom,sensors = <8>; 712 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "uplow", "critical"; 715 #thermal-sensor-cells = <1>; 716 }; 717 718 cryptobam: dma-controller@644000 { 719 compatible = "qcom,bam-v1.7.0"; 720 reg = <0x00644000 0x24000>; 721 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&gcc GCC_CE1_CLK>; 723 clock-names = "bam_clk"; 724 #dma-cells = <1>; 725 qcom,ee = <0>; 726 qcom,controlled-remotely; 727 }; 728 729 crypto: crypto@67a000 { 730 compatible = "qcom,crypto-v5.4"; 731 reg = <0x0067a000 0x6000>; 732 clocks = <&gcc GCC_CE1_AHB_CLK>, 733 <&gcc GCC_CE1_AXI_CLK>, 734 <&gcc GCC_CE1_CLK>; 735 clock-names = "iface", "bus", "core"; 736 dmas = <&cryptobam 6>, <&cryptobam 7>; 737 dma-names = "rx", "tx"; 738 }; 739 740 tcsr_mutex_regs: syscon@740000 { 741 compatible = "syscon"; 742 reg = <0x00740000 0x40000>; 743 }; 744 745 tcsr: syscon@7a0000 { 746 compatible = "qcom,tcsr-msm8996", "syscon"; 747 reg = <0x007a0000 0x18000>; 748 }; 749 750 mmcc: clock-controller@8c0000 { 751 compatible = "qcom,mmcc-msm8996"; 752 #clock-cells = <1>; 753 #reset-cells = <1>; 754 #power-domain-cells = <1>; 755 reg = <0x008c0000 0x40000>; 756 assigned-clocks = <&mmcc MMPLL9_PLL>, 757 <&mmcc MMPLL1_PLL>, 758 <&mmcc MMPLL3_PLL>, 759 <&mmcc MMPLL4_PLL>, 760 <&mmcc MMPLL5_PLL>; 761 assigned-clock-rates = <624000000>, 762 <810000000>, 763 <980000000>, 764 <960000000>, 765 <825000000>; 766 }; 767 768 mdss: mdss@900000 { 769 compatible = "qcom,mdss"; 770 771 reg = <0x00900000 0x1000>, 772 <0x009b0000 0x1040>, 773 <0x009b8000 0x1040>; 774 reg-names = "mdss_phys", 775 "vbif_phys", 776 "vbif_nrt_phys"; 777 778 power-domains = <&mmcc MDSS_GDSC>; 779 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 780 781 interrupt-controller; 782 #interrupt-cells = <1>; 783 784 clocks = <&mmcc MDSS_AHB_CLK>; 785 clock-names = "iface"; 786 787 #address-cells = <1>; 788 #size-cells = <1>; 789 ranges; 790 791 status = "disabled"; 792 793 mdp: mdp@901000 { 794 compatible = "qcom,mdp5"; 795 reg = <0x00901000 0x90000>; 796 reg-names = "mdp_phys"; 797 798 interrupt-parent = <&mdss>; 799 interrupts = <0>; 800 801 clocks = <&mmcc MDSS_AHB_CLK>, 802 <&mmcc MDSS_AXI_CLK>, 803 <&mmcc MDSS_MDP_CLK>, 804 <&mmcc SMMU_MDP_AXI_CLK>, 805 <&mmcc MDSS_VSYNC_CLK>; 806 clock-names = "iface", 807 "bus", 808 "core", 809 "iommu", 810 "vsync"; 811 812 iommus = <&mdp_smmu 0>; 813 814 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 815 <&mmcc MDSS_VSYNC_CLK>; 816 assigned-clock-rates = <300000000>, 817 <19200000>; 818 819 ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 port@0 { 824 reg = <0>; 825 mdp5_intf3_out: endpoint { 826 remote-endpoint = <&hdmi_in>; 827 }; 828 }; 829 830 port@1 { 831 reg = <1>; 832 mdp5_intf1_out: endpoint { 833 remote-endpoint = <&dsi0_in>; 834 }; 835 }; 836 }; 837 }; 838 839 dsi0: dsi@994000 { 840 compatible = "qcom,mdss-dsi-ctrl"; 841 reg = <0x00994000 0x400>; 842 reg-names = "dsi_ctrl"; 843 844 interrupt-parent = <&mdss>; 845 interrupts = <4>; 846 847 clocks = <&mmcc MDSS_MDP_CLK>, 848 <&mmcc MDSS_BYTE0_CLK>, 849 <&mmcc MDSS_AHB_CLK>, 850 <&mmcc MDSS_AXI_CLK>, 851 <&mmcc MMSS_MISC_AHB_CLK>, 852 <&mmcc MDSS_PCLK0_CLK>, 853 <&mmcc MDSS_ESC0_CLK>; 854 clock-names = "mdp_core", 855 "byte", 856 "iface", 857 "bus", 858 "core_mmss", 859 "pixel", 860 "core"; 861 862 phys = <&dsi0_phy>; 863 phy-names = "dsi"; 864 status = "disabled"; 865 866 #address-cells = <1>; 867 #size-cells = <0>; 868 869 ports { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 port@0 { 874 reg = <0>; 875 dsi0_in: endpoint { 876 remote-endpoint = <&mdp5_intf1_out>; 877 }; 878 }; 879 880 port@1 { 881 reg = <1>; 882 dsi0_out: endpoint { 883 }; 884 }; 885 }; 886 }; 887 888 dsi0_phy: dsi-phy@994400 { 889 compatible = "qcom,dsi-phy-14nm"; 890 reg = <0x00994400 0x100>, 891 <0x00994500 0x300>, 892 <0x00994800 0x188>; 893 reg-names = "dsi_phy", 894 "dsi_phy_lane", 895 "dsi_pll"; 896 897 #clock-cells = <1>; 898 #phy-cells = <0>; 899 900 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 901 clock-names = "iface", "ref"; 902 status = "disabled"; 903 }; 904 905 hdmi: hdmi-tx@9a0000 { 906 compatible = "qcom,hdmi-tx-8996"; 907 reg = <0x009a0000 0x50c>, 908 <0x00070000 0x6158>, 909 <0x009e0000 0xfff>; 910 reg-names = "core_physical", 911 "qfprom_physical", 912 "hdcp_physical"; 913 914 interrupt-parent = <&mdss>; 915 interrupts = <8>; 916 917 clocks = <&mmcc MDSS_MDP_CLK>, 918 <&mmcc MDSS_AHB_CLK>, 919 <&mmcc MDSS_HDMI_CLK>, 920 <&mmcc MDSS_HDMI_AHB_CLK>, 921 <&mmcc MDSS_EXTPCLK_CLK>; 922 clock-names = 923 "mdp_core", 924 "iface", 925 "core", 926 "alt_iface", 927 "extp"; 928 929 phys = <&hdmi_phy>; 930 phy-names = "hdmi_phy"; 931 #sound-dai-cells = <1>; 932 933 status = "disabled"; 934 935 ports { 936 #address-cells = <1>; 937 #size-cells = <0>; 938 939 port@0 { 940 reg = <0>; 941 hdmi_in: endpoint { 942 remote-endpoint = <&mdp5_intf3_out>; 943 }; 944 }; 945 }; 946 }; 947 948 hdmi_phy: hdmi-phy@9a0600 { 949 #phy-cells = <0>; 950 compatible = "qcom,hdmi-phy-8996"; 951 reg = <0x009a0600 0x1c4>, 952 <0x009a0a00 0x124>, 953 <0x009a0c00 0x124>, 954 <0x009a0e00 0x124>, 955 <0x009a1000 0x124>, 956 <0x009a1200 0x0c8>; 957 reg-names = "hdmi_pll", 958 "hdmi_tx_l0", 959 "hdmi_tx_l1", 960 "hdmi_tx_l2", 961 "hdmi_tx_l3", 962 "hdmi_phy"; 963 964 clocks = <&mmcc MDSS_AHB_CLK>, 965 <&gcc GCC_HDMI_CLKREF_CLK>; 966 clock-names = "iface", 967 "ref"; 968 969 status = "disabled"; 970 }; 971 }; 972 973 gpu: gpu@b00000 { 974 compatible = "qcom,adreno-530.2", "qcom,adreno"; 975 976 reg = <0x00b00000 0x3f000>; 977 reg-names = "kgsl_3d0_reg_memory"; 978 979 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 980 981 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 982 <&mmcc GPU_AHB_CLK>, 983 <&mmcc GPU_GX_RBBMTIMER_CLK>, 984 <&gcc GCC_BIMC_GFX_CLK>, 985 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 986 987 clock-names = "core", 988 "iface", 989 "rbbmtimer", 990 "mem", 991 "mem_iface"; 992 993 power-domains = <&mmcc GPU_GX_GDSC>; 994 iommus = <&adreno_smmu 0>; 995 996 nvmem-cells = <&speedbin_efuse>; 997 nvmem-cell-names = "speed_bin"; 998 999 operating-points-v2 = <&gpu_opp_table>; 1000 1001 status = "disabled"; 1002 1003 #cooling-cells = <2>; 1004 1005 gpu_opp_table: opp-table { 1006 compatible ="operating-points-v2"; 1007 1008 /* 1009 * 624Mhz and 560Mhz are only available on speed 1010 * bin (1 << 0). All the rest are available on 1011 * all bins of the hardware 1012 */ 1013 opp-624000000 { 1014 opp-hz = /bits/ 64 <624000000>; 1015 opp-supported-hw = <0x01>; 1016 }; 1017 opp-560000000 { 1018 opp-hz = /bits/ 64 <560000000>; 1019 opp-supported-hw = <0x01>; 1020 }; 1021 opp-510000000 { 1022 opp-hz = /bits/ 64 <510000000>; 1023 opp-supported-hw = <0xFF>; 1024 }; 1025 opp-401800000 { 1026 opp-hz = /bits/ 64 <401800000>; 1027 opp-supported-hw = <0xFF>; 1028 }; 1029 opp-315000000 { 1030 opp-hz = /bits/ 64 <315000000>; 1031 opp-supported-hw = <0xFF>; 1032 }; 1033 opp-214000000 { 1034 opp-hz = /bits/ 64 <214000000>; 1035 opp-supported-hw = <0xFF>; 1036 }; 1037 opp-133000000 { 1038 opp-hz = /bits/ 64 <133000000>; 1039 opp-supported-hw = <0xFF>; 1040 }; 1041 }; 1042 1043 zap-shader { 1044 memory-region = <&gpu_mem>; 1045 }; 1046 }; 1047 1048 tlmm: pinctrl@1010000 { 1049 compatible = "qcom,msm8996-pinctrl"; 1050 reg = <0x01010000 0x300000>; 1051 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1052 gpio-controller; 1053 gpio-ranges = <&tlmm 0 0 150>; 1054 #gpio-cells = <2>; 1055 interrupt-controller; 1056 #interrupt-cells = <2>; 1057 1058 blsp1_spi1_default: blsp1-spi1-default { 1059 spi { 1060 pins = "gpio0", "gpio1", "gpio3"; 1061 function = "blsp_spi1"; 1062 drive-strength = <12>; 1063 bias-disable; 1064 }; 1065 1066 cs { 1067 pins = "gpio2"; 1068 function = "gpio"; 1069 drive-strength = <16>; 1070 bias-disable; 1071 output-high; 1072 }; 1073 }; 1074 1075 blsp1_spi1_sleep: blsp1-spi1-sleep { 1076 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1077 function = "gpio"; 1078 drive-strength = <2>; 1079 bias-pull-down; 1080 }; 1081 1082 blsp2_uart2_2pins_default: blsp2-uart1-2pins { 1083 pins = "gpio4", "gpio5"; 1084 function = "blsp_uart8"; 1085 drive-strength = <16>; 1086 bias-disable; 1087 }; 1088 1089 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { 1090 pins = "gpio4", "gpio5"; 1091 function = "gpio"; 1092 drive-strength = <2>; 1093 bias-disable; 1094 }; 1095 1096 blsp2_i2c2_default: blsp2-i2c2 { 1097 pins = "gpio6", "gpio7"; 1098 function = "blsp_i2c8"; 1099 drive-strength = <16>; 1100 bias-disable; 1101 }; 1102 1103 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1104 pins = "gpio6", "gpio7"; 1105 function = "gpio"; 1106 drive-strength = <2>; 1107 bias-disable; 1108 }; 1109 1110 cci0_default: cci0-default { 1111 pins = "gpio17", "gpio18"; 1112 function = "cci_i2c"; 1113 drive-strength = <16>; 1114 bias-disable; 1115 }; 1116 1117 camera0_state_on: 1118 camera_rear_default: camera-rear-default { 1119 camera0_mclk: mclk0 { 1120 pins = "gpio13"; 1121 function = "cam_mclk"; 1122 drive-strength = <16>; 1123 bias-disable; 1124 }; 1125 1126 camera0_rst: rst { 1127 pins = "gpio25"; 1128 function = "gpio"; 1129 drive-strength = <16>; 1130 bias-disable; 1131 }; 1132 1133 camera0_pwdn: pwdn { 1134 pins = "gpio26"; 1135 function = "gpio"; 1136 drive-strength = <16>; 1137 bias-disable; 1138 }; 1139 }; 1140 1141 cci1_default: cci1-default { 1142 pins = "gpio19", "gpio20"; 1143 function = "cci_i2c"; 1144 drive-strength = <16>; 1145 bias-disable; 1146 }; 1147 1148 camera1_state_on: 1149 camera_board_default: camera-board-default { 1150 mclk1 { 1151 pins = "gpio14"; 1152 function = "cam_mclk"; 1153 drive-strength = <16>; 1154 bias-disable; 1155 }; 1156 1157 pwdn { 1158 pins = "gpio98"; 1159 function = "gpio"; 1160 drive-strength = <16>; 1161 bias-disable; 1162 }; 1163 1164 rst { 1165 pins = "gpio104"; 1166 function = "gpio"; 1167 drive-strength = <16>; 1168 bias-disable; 1169 }; 1170 }; 1171 1172 camera2_state_on: 1173 camera_front_default: camera-front-default { 1174 camera2_mclk: mclk2 { 1175 pins = "gpio15"; 1176 function = "cam_mclk"; 1177 drive-strength = <16>; 1178 bias-disable; 1179 }; 1180 1181 camera2_rst: rst { 1182 pins = "gpio23"; 1183 function = "gpio"; 1184 drive-strength = <16>; 1185 bias-disable; 1186 }; 1187 1188 pwdn { 1189 pins = "gpio133"; 1190 function = "gpio"; 1191 drive-strength = <16>; 1192 bias-disable; 1193 }; 1194 }; 1195 1196 pcie0_state_on: pcie0-state-on { 1197 perst { 1198 pins = "gpio35"; 1199 function = "gpio"; 1200 drive-strength = <2>; 1201 bias-pull-down; 1202 }; 1203 1204 clkreq { 1205 pins = "gpio36"; 1206 function = "pci_e0"; 1207 drive-strength = <2>; 1208 bias-pull-up; 1209 }; 1210 1211 wake { 1212 pins = "gpio37"; 1213 function = "gpio"; 1214 drive-strength = <2>; 1215 bias-pull-up; 1216 }; 1217 }; 1218 1219 pcie0_state_off: pcie0-state-off { 1220 perst { 1221 pins = "gpio35"; 1222 function = "gpio"; 1223 drive-strength = <2>; 1224 bias-pull-down; 1225 }; 1226 1227 clkreq { 1228 pins = "gpio36"; 1229 function = "gpio"; 1230 drive-strength = <2>; 1231 bias-disable; 1232 }; 1233 1234 wake { 1235 pins = "gpio37"; 1236 function = "gpio"; 1237 drive-strength = <2>; 1238 bias-disable; 1239 }; 1240 }; 1241 1242 blsp1_uart2_default: blsp1-uart2-default { 1243 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1244 function = "blsp_uart2"; 1245 drive-strength = <16>; 1246 bias-disable; 1247 }; 1248 1249 blsp1_uart2_sleep: blsp1-uart2-sleep { 1250 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1251 function = "gpio"; 1252 drive-strength = <2>; 1253 bias-disable; 1254 }; 1255 1256 blsp1_i2c3_default: blsp1-i2c2-default { 1257 pins = "gpio47", "gpio48"; 1258 function = "blsp_i2c3"; 1259 drive-strength = <16>; 1260 bias-disable; 1261 }; 1262 1263 blsp1_i2c3_sleep: blsp1-i2c2-sleep { 1264 pins = "gpio47", "gpio48"; 1265 function = "gpio"; 1266 drive-strength = <2>; 1267 bias-disable; 1268 }; 1269 1270 blsp2_uart3_4pins_default: blsp2-uart2-4pins { 1271 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1272 function = "blsp_uart9"; 1273 drive-strength = <16>; 1274 bias-disable; 1275 }; 1276 1277 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { 1278 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1279 function = "blsp_uart9"; 1280 drive-strength = <2>; 1281 bias-disable; 1282 }; 1283 1284 blsp2_i2c3_default: blsp2-i2c3 { 1285 pins = "gpio51", "gpio52"; 1286 function = "blsp_i2c9"; 1287 drive-strength = <16>; 1288 bias-disable; 1289 }; 1290 1291 blsp2_i2c3_sleep: blsp2-i2c3-sleep { 1292 pins = "gpio51", "gpio52"; 1293 function = "gpio"; 1294 drive-strength = <2>; 1295 bias-disable; 1296 }; 1297 1298 wcd_intr_default: wcd-intr-default{ 1299 pins = "gpio54"; 1300 function = "gpio"; 1301 drive-strength = <2>; 1302 bias-pull-down; 1303 input-enable; 1304 }; 1305 1306 blsp2_i2c1_default: blsp2-i2c1 { 1307 pins = "gpio55", "gpio56"; 1308 function = "blsp_i2c7"; 1309 drive-strength = <16>; 1310 bias-disable; 1311 }; 1312 1313 blsp2_i2c1_sleep: blsp2-i2c0-sleep { 1314 pins = "gpio55", "gpio56"; 1315 function = "gpio"; 1316 drive-strength = <2>; 1317 bias-disable; 1318 }; 1319 1320 blsp2_i2c5_default: blsp2-i2c5 { 1321 pins = "gpio60", "gpio61"; 1322 function = "blsp_i2c11"; 1323 drive-strength = <2>; 1324 bias-disable; 1325 }; 1326 1327 /* Sleep state for BLSP2_I2C5 is missing.. */ 1328 1329 cdc_reset_active: cdc-reset-active { 1330 pins = "gpio64"; 1331 function = "gpio"; 1332 drive-strength = <16>; 1333 bias-pull-down; 1334 output-high; 1335 }; 1336 1337 cdc_reset_sleep: cdc-reset-sleep { 1338 pins = "gpio64"; 1339 function = "gpio"; 1340 drive-strength = <16>; 1341 bias-disable; 1342 output-low; 1343 }; 1344 1345 blsp2_spi6_default: blsp2-spi5-default { 1346 spi { 1347 pins = "gpio85", "gpio86", "gpio88"; 1348 function = "blsp_spi12"; 1349 drive-strength = <12>; 1350 bias-disable; 1351 }; 1352 1353 cs { 1354 pins = "gpio87"; 1355 function = "gpio"; 1356 drive-strength = <16>; 1357 bias-disable; 1358 output-high; 1359 }; 1360 }; 1361 1362 blsp2_spi6_sleep: blsp2-spi5-sleep { 1363 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1364 function = "gpio"; 1365 drive-strength = <2>; 1366 bias-pull-down; 1367 }; 1368 1369 blsp2_i2c6_default: blsp2-i2c6 { 1370 pins = "gpio87", "gpio88"; 1371 function = "blsp_i2c12"; 1372 drive-strength = <16>; 1373 bias-disable; 1374 }; 1375 1376 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1377 pins = "gpio87", "gpio88"; 1378 function = "gpio"; 1379 drive-strength = <2>; 1380 bias-disable; 1381 }; 1382 1383 pcie1_state_on: pcie1-state-on { 1384 perst { 1385 pins = "gpio130"; 1386 function = "gpio"; 1387 drive-strength = <2>; 1388 bias-pull-down; 1389 }; 1390 1391 clkreq { 1392 pins = "gpio131"; 1393 function = "pci_e1"; 1394 drive-strength = <2>; 1395 bias-pull-up; 1396 }; 1397 1398 wake { 1399 pins = "gpio132"; 1400 function = "gpio"; 1401 drive-strength = <2>; 1402 bias-pull-down; 1403 }; 1404 }; 1405 1406 pcie1_state_off: pcie1-state-off { 1407 /* Perst is missing? */ 1408 clkreq { 1409 pins = "gpio131"; 1410 function = "gpio"; 1411 drive-strength = <2>; 1412 bias-disable; 1413 }; 1414 1415 wake { 1416 pins = "gpio132"; 1417 function = "gpio"; 1418 drive-strength = <2>; 1419 bias-disable; 1420 }; 1421 }; 1422 1423 pcie2_state_on: pcie2-state-on { 1424 perst { 1425 pins = "gpio114"; 1426 function = "gpio"; 1427 drive-strength = <2>; 1428 bias-pull-down; 1429 }; 1430 1431 clkreq { 1432 pins = "gpio115"; 1433 function = "pci_e2"; 1434 drive-strength = <2>; 1435 bias-pull-up; 1436 }; 1437 1438 wake { 1439 pins = "gpio116"; 1440 function = "gpio"; 1441 drive-strength = <2>; 1442 bias-pull-down; 1443 }; 1444 }; 1445 1446 pcie2_state_off: pcie2-state-off { 1447 /* Perst is missing? */ 1448 clkreq { 1449 pins = "gpio115"; 1450 function = "gpio"; 1451 drive-strength = <2>; 1452 bias-disable; 1453 }; 1454 1455 wake { 1456 pins = "gpio116"; 1457 function = "gpio"; 1458 drive-strength = <2>; 1459 bias-disable; 1460 }; 1461 }; 1462 1463 sdc1_state_on: sdc1-state-on { 1464 clk { 1465 pins = "sdc1_clk"; 1466 bias-disable; 1467 drive-strength = <16>; 1468 }; 1469 1470 cmd { 1471 pins = "sdc1_cmd"; 1472 bias-pull-up; 1473 drive-strength = <10>; 1474 }; 1475 1476 data { 1477 pins = "sdc1_data"; 1478 bias-pull-up; 1479 drive-strength = <10>; 1480 }; 1481 1482 rclk { 1483 pins = "sdc1_rclk"; 1484 bias-pull-down; 1485 }; 1486 }; 1487 1488 sdc1_state_off: sdc1-state-off { 1489 clk { 1490 pins = "sdc1_clk"; 1491 bias-disable; 1492 drive-strength = <2>; 1493 }; 1494 1495 cmd { 1496 pins = "sdc1_cmd"; 1497 bias-pull-up; 1498 drive-strength = <2>; 1499 }; 1500 1501 data { 1502 pins = "sdc1_data"; 1503 bias-pull-up; 1504 drive-strength = <2>; 1505 }; 1506 1507 rclk { 1508 pins = "sdc1_rclk"; 1509 bias-pull-down; 1510 }; 1511 }; 1512 1513 sdc2_state_on: sdc2-clk-on { 1514 clk { 1515 pins = "sdc2_clk"; 1516 bias-disable; 1517 drive-strength = <16>; 1518 }; 1519 1520 cmd { 1521 pins = "sdc2_cmd"; 1522 bias-pull-up; 1523 drive-strength = <10>; 1524 }; 1525 1526 data { 1527 pins = "sdc2_data"; 1528 bias-pull-up; 1529 drive-strength = <10>; 1530 }; 1531 }; 1532 1533 sdc2_state_off: sdc2-clk-off { 1534 clk { 1535 pins = "sdc2_clk"; 1536 bias-disable; 1537 drive-strength = <2>; 1538 }; 1539 1540 cmd { 1541 pins = "sdc2_cmd"; 1542 bias-pull-up; 1543 drive-strength = <2>; 1544 }; 1545 1546 data { 1547 pins = "sdc2_data"; 1548 bias-pull-up; 1549 drive-strength = <2>; 1550 }; 1551 }; 1552 }; 1553 1554 sram@290000 { 1555 compatible = "qcom,rpm-stats"; 1556 reg = <0x00290000 0x10000>; 1557 }; 1558 1559 spmi_bus: spmi@400f000 { 1560 compatible = "qcom,spmi-pmic-arb"; 1561 reg = <0x0400f000 0x1000>, 1562 <0x04400000 0x800000>, 1563 <0x04c00000 0x800000>, 1564 <0x05800000 0x200000>, 1565 <0x0400a000 0x002100>; 1566 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1567 interrupt-names = "periph_irq"; 1568 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1569 qcom,ee = <0>; 1570 qcom,channel = <0>; 1571 #address-cells = <2>; 1572 #size-cells = <0>; 1573 interrupt-controller; 1574 #interrupt-cells = <4>; 1575 }; 1576 1577 agnoc@0 { 1578 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1579 compatible = "simple-pm-bus"; 1580 #address-cells = <1>; 1581 #size-cells = <1>; 1582 ranges; 1583 1584 pcie0: pcie@600000 { 1585 compatible = "qcom,pcie-msm8996"; 1586 status = "disabled"; 1587 power-domains = <&gcc PCIE0_GDSC>; 1588 bus-range = <0x00 0xff>; 1589 num-lanes = <1>; 1590 1591 reg = <0x00600000 0x2000>, 1592 <0x0c000000 0xf1d>, 1593 <0x0c000f20 0xa8>, 1594 <0x0c100000 0x100000>; 1595 reg-names = "parf", "dbi", "elbi","config"; 1596 1597 phys = <&pciephy_0>; 1598 phy-names = "pciephy"; 1599 1600 #address-cells = <3>; 1601 #size-cells = <2>; 1602 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1603 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1604 1605 device_type = "pci"; 1606 1607 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1608 interrupt-names = "msi"; 1609 #interrupt-cells = <1>; 1610 interrupt-map-mask = <0 0 0 0x7>; 1611 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1612 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1613 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1614 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1615 1616 pinctrl-names = "default", "sleep"; 1617 pinctrl-0 = <&pcie0_state_on>; 1618 pinctrl-1 = <&pcie0_state_off>; 1619 1620 linux,pci-domain = <0>; 1621 1622 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1623 <&gcc GCC_PCIE_0_AUX_CLK>, 1624 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1625 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1626 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1627 1628 clock-names = "pipe", 1629 "aux", 1630 "cfg", 1631 "bus_master", 1632 "bus_slave"; 1633 1634 }; 1635 1636 pcie1: pcie@608000 { 1637 compatible = "qcom,pcie-msm8996"; 1638 power-domains = <&gcc PCIE1_GDSC>; 1639 bus-range = <0x00 0xff>; 1640 num-lanes = <1>; 1641 1642 status = "disabled"; 1643 1644 reg = <0x00608000 0x2000>, 1645 <0x0d000000 0xf1d>, 1646 <0x0d000f20 0xa8>, 1647 <0x0d100000 0x100000>; 1648 1649 reg-names = "parf", "dbi", "elbi","config"; 1650 1651 phys = <&pciephy_1>; 1652 phy-names = "pciephy"; 1653 1654 #address-cells = <3>; 1655 #size-cells = <2>; 1656 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1657 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1658 1659 device_type = "pci"; 1660 1661 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1662 interrupt-names = "msi"; 1663 #interrupt-cells = <1>; 1664 interrupt-map-mask = <0 0 0 0x7>; 1665 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1666 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1667 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1668 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1669 1670 pinctrl-names = "default", "sleep"; 1671 pinctrl-0 = <&pcie1_state_on>; 1672 pinctrl-1 = <&pcie1_state_off>; 1673 1674 linux,pci-domain = <1>; 1675 1676 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1677 <&gcc GCC_PCIE_1_AUX_CLK>, 1678 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1679 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1680 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1681 1682 clock-names = "pipe", 1683 "aux", 1684 "cfg", 1685 "bus_master", 1686 "bus_slave"; 1687 }; 1688 1689 pcie2: pcie@610000 { 1690 compatible = "qcom,pcie-msm8996"; 1691 power-domains = <&gcc PCIE2_GDSC>; 1692 bus-range = <0x00 0xff>; 1693 num-lanes = <1>; 1694 status = "disabled"; 1695 reg = <0x00610000 0x2000>, 1696 <0x0e000000 0xf1d>, 1697 <0x0e000f20 0xa8>, 1698 <0x0e100000 0x100000>; 1699 1700 reg-names = "parf", "dbi", "elbi","config"; 1701 1702 phys = <&pciephy_2>; 1703 phy-names = "pciephy"; 1704 1705 #address-cells = <3>; 1706 #size-cells = <2>; 1707 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1708 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1709 1710 device_type = "pci"; 1711 1712 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1713 interrupt-names = "msi"; 1714 #interrupt-cells = <1>; 1715 interrupt-map-mask = <0 0 0 0x7>; 1716 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1717 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1718 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1719 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1720 1721 pinctrl-names = "default", "sleep"; 1722 pinctrl-0 = <&pcie2_state_on>; 1723 pinctrl-1 = <&pcie2_state_off>; 1724 1725 linux,pci-domain = <2>; 1726 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1727 <&gcc GCC_PCIE_2_AUX_CLK>, 1728 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1729 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1730 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1731 1732 clock-names = "pipe", 1733 "aux", 1734 "cfg", 1735 "bus_master", 1736 "bus_slave"; 1737 }; 1738 }; 1739 1740 ufshc: ufshc@624000 { 1741 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1742 "jedec,ufs-2.0"; 1743 reg = <0x00624000 0x2500>; 1744 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1745 1746 phys = <&ufsphy_lane>; 1747 phy-names = "ufsphy"; 1748 1749 power-domains = <&gcc UFS_GDSC>; 1750 1751 clock-names = 1752 "core_clk_src", 1753 "core_clk", 1754 "bus_clk", 1755 "bus_aggr_clk", 1756 "iface_clk", 1757 "core_clk_unipro_src", 1758 "core_clk_unipro", 1759 "core_clk_ice", 1760 "ref_clk", 1761 "tx_lane0_sync_clk", 1762 "rx_lane0_sync_clk"; 1763 clocks = 1764 <&gcc UFS_AXI_CLK_SRC>, 1765 <&gcc GCC_UFS_AXI_CLK>, 1766 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 1767 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 1768 <&gcc GCC_UFS_AHB_CLK>, 1769 <&gcc UFS_ICE_CORE_CLK_SRC>, 1770 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1771 <&gcc GCC_UFS_ICE_CORE_CLK>, 1772 <&rpmcc RPM_SMD_LN_BB_CLK>, 1773 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1774 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 1775 freq-table-hz = 1776 <100000000 200000000>, 1777 <0 0>, 1778 <0 0>, 1779 <0 0>, 1780 <0 0>, 1781 <150000000 300000000>, 1782 <0 0>, 1783 <0 0>, 1784 <0 0>, 1785 <0 0>, 1786 <0 0>; 1787 1788 lanes-per-direction = <1>; 1789 #reset-cells = <1>; 1790 status = "disabled"; 1791 1792 ufs_variant { 1793 compatible = "qcom,ufs_variant"; 1794 }; 1795 }; 1796 1797 ufsphy: phy@627000 { 1798 compatible = "qcom,msm8996-qmp-ufs-phy"; 1799 reg = <0x00627000 0x1c4>; 1800 #address-cells = <1>; 1801 #size-cells = <1>; 1802 ranges; 1803 1804 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 1805 clock-names = "ref"; 1806 1807 resets = <&ufshc 0>; 1808 reset-names = "ufsphy"; 1809 status = "disabled"; 1810 1811 ufsphy_lane: phy@627400 { 1812 reg = <0x627400 0x12c>, 1813 <0x627600 0x200>, 1814 <0x627c00 0x1b4>; 1815 #phy-cells = <0>; 1816 }; 1817 }; 1818 1819 camss: camss@a00000 { 1820 compatible = "qcom,msm8996-camss"; 1821 reg = <0x00a34000 0x1000>, 1822 <0x00a00030 0x4>, 1823 <0x00a35000 0x1000>, 1824 <0x00a00038 0x4>, 1825 <0x00a36000 0x1000>, 1826 <0x00a00040 0x4>, 1827 <0x00a30000 0x100>, 1828 <0x00a30400 0x100>, 1829 <0x00a30800 0x100>, 1830 <0x00a30c00 0x100>, 1831 <0x00a31000 0x500>, 1832 <0x00a00020 0x10>, 1833 <0x00a10000 0x1000>, 1834 <0x00a14000 0x1000>; 1835 reg-names = "csiphy0", 1836 "csiphy0_clk_mux", 1837 "csiphy1", 1838 "csiphy1_clk_mux", 1839 "csiphy2", 1840 "csiphy2_clk_mux", 1841 "csid0", 1842 "csid1", 1843 "csid2", 1844 "csid3", 1845 "ispif", 1846 "csi_clk_mux", 1847 "vfe0", 1848 "vfe1"; 1849 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1850 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1851 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1852 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1853 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1854 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1855 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1856 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1857 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1858 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1859 interrupt-names = "csiphy0", 1860 "csiphy1", 1861 "csiphy2", 1862 "csid0", 1863 "csid1", 1864 "csid2", 1865 "csid3", 1866 "ispif", 1867 "vfe0", 1868 "vfe1"; 1869 power-domains = <&mmcc VFE0_GDSC>, 1870 <&mmcc VFE1_GDSC>; 1871 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1872 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1873 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1874 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1875 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1876 <&mmcc CAMSS_CSI0_AHB_CLK>, 1877 <&mmcc CAMSS_CSI0_CLK>, 1878 <&mmcc CAMSS_CSI0PHY_CLK>, 1879 <&mmcc CAMSS_CSI0PIX_CLK>, 1880 <&mmcc CAMSS_CSI0RDI_CLK>, 1881 <&mmcc CAMSS_CSI1_AHB_CLK>, 1882 <&mmcc CAMSS_CSI1_CLK>, 1883 <&mmcc CAMSS_CSI1PHY_CLK>, 1884 <&mmcc CAMSS_CSI1PIX_CLK>, 1885 <&mmcc CAMSS_CSI1RDI_CLK>, 1886 <&mmcc CAMSS_CSI2_AHB_CLK>, 1887 <&mmcc CAMSS_CSI2_CLK>, 1888 <&mmcc CAMSS_CSI2PHY_CLK>, 1889 <&mmcc CAMSS_CSI2PIX_CLK>, 1890 <&mmcc CAMSS_CSI2RDI_CLK>, 1891 <&mmcc CAMSS_CSI3_AHB_CLK>, 1892 <&mmcc CAMSS_CSI3_CLK>, 1893 <&mmcc CAMSS_CSI3PHY_CLK>, 1894 <&mmcc CAMSS_CSI3PIX_CLK>, 1895 <&mmcc CAMSS_CSI3RDI_CLK>, 1896 <&mmcc CAMSS_AHB_CLK>, 1897 <&mmcc CAMSS_VFE0_CLK>, 1898 <&mmcc CAMSS_CSI_VFE0_CLK>, 1899 <&mmcc CAMSS_VFE0_AHB_CLK>, 1900 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1901 <&mmcc CAMSS_VFE1_CLK>, 1902 <&mmcc CAMSS_CSI_VFE1_CLK>, 1903 <&mmcc CAMSS_VFE1_AHB_CLK>, 1904 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1905 <&mmcc CAMSS_VFE_AHB_CLK>, 1906 <&mmcc CAMSS_VFE_AXI_CLK>; 1907 clock-names = "top_ahb", 1908 "ispif_ahb", 1909 "csiphy0_timer", 1910 "csiphy1_timer", 1911 "csiphy2_timer", 1912 "csi0_ahb", 1913 "csi0", 1914 "csi0_phy", 1915 "csi0_pix", 1916 "csi0_rdi", 1917 "csi1_ahb", 1918 "csi1", 1919 "csi1_phy", 1920 "csi1_pix", 1921 "csi1_rdi", 1922 "csi2_ahb", 1923 "csi2", 1924 "csi2_phy", 1925 "csi2_pix", 1926 "csi2_rdi", 1927 "csi3_ahb", 1928 "csi3", 1929 "csi3_phy", 1930 "csi3_pix", 1931 "csi3_rdi", 1932 "ahb", 1933 "vfe0", 1934 "csi_vfe0", 1935 "vfe0_ahb", 1936 "vfe0_stream", 1937 "vfe1", 1938 "csi_vfe1", 1939 "vfe1_ahb", 1940 "vfe1_stream", 1941 "vfe_ahb", 1942 "vfe_axi"; 1943 iommus = <&vfe_smmu 0>, 1944 <&vfe_smmu 1>, 1945 <&vfe_smmu 2>, 1946 <&vfe_smmu 3>; 1947 status = "disabled"; 1948 ports { 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 }; 1952 }; 1953 1954 cci: cci@a0c000 { 1955 compatible = "qcom,msm8996-cci"; 1956 #address-cells = <1>; 1957 #size-cells = <0>; 1958 reg = <0xa0c000 0x1000>; 1959 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1960 power-domains = <&mmcc CAMSS_GDSC>; 1961 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1962 <&mmcc CAMSS_CCI_AHB_CLK>, 1963 <&mmcc CAMSS_CCI_CLK>, 1964 <&mmcc CAMSS_AHB_CLK>; 1965 clock-names = "camss_top_ahb", 1966 "cci_ahb", 1967 "cci", 1968 "camss_ahb"; 1969 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1970 <&mmcc CAMSS_CCI_CLK>; 1971 assigned-clock-rates = <80000000>, <37500000>; 1972 pinctrl-names = "default"; 1973 pinctrl-0 = <&cci0_default &cci1_default>; 1974 status = "disabled"; 1975 1976 cci_i2c0: i2c-bus@0 { 1977 reg = <0>; 1978 clock-frequency = <400000>; 1979 #address-cells = <1>; 1980 #size-cells = <0>; 1981 }; 1982 1983 cci_i2c1: i2c-bus@1 { 1984 reg = <1>; 1985 clock-frequency = <400000>; 1986 #address-cells = <1>; 1987 #size-cells = <0>; 1988 }; 1989 }; 1990 1991 adreno_smmu: iommu@b40000 { 1992 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1993 reg = <0x00b40000 0x10000>; 1994 1995 #global-interrupts = <1>; 1996 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1999 #iommu-cells = <1>; 2000 2001 clocks = <&mmcc GPU_AHB_CLK>, 2002 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 2003 clock-names = "iface", "bus"; 2004 2005 power-domains = <&mmcc GPU_GDSC>; 2006 }; 2007 2008 venus: video-codec@c00000 { 2009 compatible = "qcom,msm8996-venus"; 2010 reg = <0x00c00000 0xff000>; 2011 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2012 power-domains = <&mmcc VENUS_GDSC>; 2013 clocks = <&mmcc VIDEO_CORE_CLK>, 2014 <&mmcc VIDEO_AHB_CLK>, 2015 <&mmcc VIDEO_AXI_CLK>, 2016 <&mmcc VIDEO_MAXI_CLK>; 2017 clock-names = "core", "iface", "bus", "mbus"; 2018 iommus = <&venus_smmu 0x00>, 2019 <&venus_smmu 0x01>, 2020 <&venus_smmu 0x0a>, 2021 <&venus_smmu 0x07>, 2022 <&venus_smmu 0x0e>, 2023 <&venus_smmu 0x0f>, 2024 <&venus_smmu 0x08>, 2025 <&venus_smmu 0x09>, 2026 <&venus_smmu 0x0b>, 2027 <&venus_smmu 0x0c>, 2028 <&venus_smmu 0x0d>, 2029 <&venus_smmu 0x10>, 2030 <&venus_smmu 0x11>, 2031 <&venus_smmu 0x21>, 2032 <&venus_smmu 0x28>, 2033 <&venus_smmu 0x29>, 2034 <&venus_smmu 0x2b>, 2035 <&venus_smmu 0x2c>, 2036 <&venus_smmu 0x2d>, 2037 <&venus_smmu 0x31>; 2038 memory-region = <&venus_mem>; 2039 status = "disabled"; 2040 2041 video-decoder { 2042 compatible = "venus-decoder"; 2043 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2044 clock-names = "core"; 2045 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2046 }; 2047 2048 video-encoder { 2049 compatible = "venus-encoder"; 2050 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2051 clock-names = "core"; 2052 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2053 }; 2054 }; 2055 2056 mdp_smmu: iommu@d00000 { 2057 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2058 reg = <0x00d00000 0x10000>; 2059 2060 #global-interrupts = <1>; 2061 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2064 #iommu-cells = <1>; 2065 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 2066 <&mmcc SMMU_MDP_AXI_CLK>; 2067 clock-names = "iface", "bus"; 2068 2069 power-domains = <&mmcc MDSS_GDSC>; 2070 }; 2071 2072 venus_smmu: iommu@d40000 { 2073 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2074 reg = <0x00d40000 0x20000>; 2075 #global-interrupts = <1>; 2076 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2084 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2085 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 2086 <&mmcc SMMU_VIDEO_AXI_CLK>; 2087 clock-names = "iface", "bus"; 2088 #iommu-cells = <1>; 2089 status = "okay"; 2090 }; 2091 2092 vfe_smmu: iommu@da0000 { 2093 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2094 reg = <0x00da0000 0x10000>; 2095 2096 #global-interrupts = <1>; 2097 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2100 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2101 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 2102 <&mmcc SMMU_VFE_AXI_CLK>; 2103 clock-names = "iface", 2104 "bus"; 2105 #iommu-cells = <1>; 2106 }; 2107 2108 lpass_q6_smmu: iommu@1600000 { 2109 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2110 reg = <0x01600000 0x20000>; 2111 #iommu-cells = <1>; 2112 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2113 2114 #global-interrupts = <1>; 2115 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2128 2129 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 2130 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 2131 clock-names = "iface", "bus"; 2132 }; 2133 2134 slpi_pil: remoteproc@1c00000 { 2135 compatible = "qcom,msm8996-slpi-pil"; 2136 reg = <0x01c00000 0x4000>; 2137 2138 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2139 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2140 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2141 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2142 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2143 interrupt-names = "wdog", 2144 "fatal", 2145 "ready", 2146 "handover", 2147 "stop-ack"; 2148 2149 clocks = <&xo_board>, 2150 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2151 clock-names = "xo", "aggre2"; 2152 2153 memory-region = <&slpi_mem>; 2154 2155 qcom,smem-states = <&slpi_smp2p_out 0>; 2156 qcom,smem-state-names = "stop"; 2157 2158 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2159 power-domain-names = "ssc_cx"; 2160 2161 status = "disabled"; 2162 2163 smd-edge { 2164 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2165 2166 label = "dsps"; 2167 mboxes = <&apcs_glb 25>; 2168 qcom,smd-edge = <3>; 2169 qcom,remote-pid = <3>; 2170 }; 2171 }; 2172 2173 mss_pil: remoteproc@2080000 { 2174 compatible = "qcom,msm8996-mss-pil"; 2175 reg = <0x2080000 0x100>, 2176 <0x2180000 0x020>; 2177 reg-names = "qdsp6", "rmb"; 2178 2179 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2180 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2181 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2182 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2183 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2184 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2185 interrupt-names = "wdog", "fatal", "ready", 2186 "handover", "stop-ack", 2187 "shutdown-ack"; 2188 2189 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2190 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2191 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2192 <&xo_board>, 2193 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2194 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2195 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2196 <&rpmcc RPM_SMD_PCNOC_CLK>, 2197 <&rpmcc RPM_SMD_QDSS_CLK>; 2198 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2199 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2200 2201 resets = <&gcc GCC_MSS_RESTART>; 2202 reset-names = "mss_restart"; 2203 2204 power-domains = <&rpmpd MSM8996_VDDCX>, 2205 <&rpmpd MSM8996_VDDMX>; 2206 power-domain-names = "cx", "mx"; 2207 2208 qcom,smem-states = <&mpss_smp2p_out 0>; 2209 qcom,smem-state-names = "stop"; 2210 2211 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2212 2213 status = "disabled"; 2214 2215 mba { 2216 memory-region = <&mba_mem>; 2217 }; 2218 2219 mpss { 2220 memory-region = <&mpss_mem>; 2221 }; 2222 2223 smd-edge { 2224 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2225 2226 label = "mpss"; 2227 mboxes = <&apcs_glb 12>; 2228 qcom,smd-edge = <0>; 2229 qcom,remote-pid = <1>; 2230 }; 2231 }; 2232 2233 stm@3002000 { 2234 compatible = "arm,coresight-stm", "arm,primecell"; 2235 reg = <0x3002000 0x1000>, 2236 <0x8280000 0x180000>; 2237 reg-names = "stm-base", "stm-stimulus-base"; 2238 2239 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2240 clock-names = "apb_pclk", "atclk"; 2241 2242 out-ports { 2243 port { 2244 stm_out: endpoint { 2245 remote-endpoint = 2246 <&funnel0_in>; 2247 }; 2248 }; 2249 }; 2250 }; 2251 2252 tpiu@3020000 { 2253 compatible = "arm,coresight-tpiu", "arm,primecell"; 2254 reg = <0x3020000 0x1000>; 2255 2256 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2257 clock-names = "apb_pclk", "atclk"; 2258 2259 in-ports { 2260 port { 2261 tpiu_in: endpoint { 2262 remote-endpoint = 2263 <&replicator_out1>; 2264 }; 2265 }; 2266 }; 2267 }; 2268 2269 funnel@3021000 { 2270 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2271 reg = <0x3021000 0x1000>; 2272 2273 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2274 clock-names = "apb_pclk", "atclk"; 2275 2276 in-ports { 2277 #address-cells = <1>; 2278 #size-cells = <0>; 2279 2280 port@7 { 2281 reg = <7>; 2282 funnel0_in: endpoint { 2283 remote-endpoint = 2284 <&stm_out>; 2285 }; 2286 }; 2287 }; 2288 2289 out-ports { 2290 port { 2291 funnel0_out: endpoint { 2292 remote-endpoint = 2293 <&merge_funnel_in0>; 2294 }; 2295 }; 2296 }; 2297 }; 2298 2299 funnel@3022000 { 2300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2301 reg = <0x3022000 0x1000>; 2302 2303 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2304 clock-names = "apb_pclk", "atclk"; 2305 2306 in-ports { 2307 #address-cells = <1>; 2308 #size-cells = <0>; 2309 2310 port@6 { 2311 reg = <6>; 2312 funnel1_in: endpoint { 2313 remote-endpoint = 2314 <&apss_merge_funnel_out>; 2315 }; 2316 }; 2317 }; 2318 2319 out-ports { 2320 port { 2321 funnel1_out: endpoint { 2322 remote-endpoint = 2323 <&merge_funnel_in1>; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 funnel@3023000 { 2330 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2331 reg = <0x3023000 0x1000>; 2332 2333 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2334 clock-names = "apb_pclk", "atclk"; 2335 2336 2337 out-ports { 2338 port { 2339 funnel2_out: endpoint { 2340 remote-endpoint = 2341 <&merge_funnel_in2>; 2342 }; 2343 }; 2344 }; 2345 }; 2346 2347 funnel@3025000 { 2348 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2349 reg = <0x3025000 0x1000>; 2350 2351 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2352 clock-names = "apb_pclk", "atclk"; 2353 2354 in-ports { 2355 #address-cells = <1>; 2356 #size-cells = <0>; 2357 2358 port@0 { 2359 reg = <0>; 2360 merge_funnel_in0: endpoint { 2361 remote-endpoint = 2362 <&funnel0_out>; 2363 }; 2364 }; 2365 2366 port@1 { 2367 reg = <1>; 2368 merge_funnel_in1: endpoint { 2369 remote-endpoint = 2370 <&funnel1_out>; 2371 }; 2372 }; 2373 2374 port@2 { 2375 reg = <2>; 2376 merge_funnel_in2: endpoint { 2377 remote-endpoint = 2378 <&funnel2_out>; 2379 }; 2380 }; 2381 }; 2382 2383 out-ports { 2384 port { 2385 merge_funnel_out: endpoint { 2386 remote-endpoint = 2387 <&etf_in>; 2388 }; 2389 }; 2390 }; 2391 }; 2392 2393 replicator@3026000 { 2394 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2395 reg = <0x3026000 0x1000>; 2396 2397 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2398 clock-names = "apb_pclk", "atclk"; 2399 2400 in-ports { 2401 port { 2402 replicator_in: endpoint { 2403 remote-endpoint = 2404 <&etf_out>; 2405 }; 2406 }; 2407 }; 2408 2409 out-ports { 2410 #address-cells = <1>; 2411 #size-cells = <0>; 2412 2413 port@0 { 2414 reg = <0>; 2415 replicator_out0: endpoint { 2416 remote-endpoint = 2417 <&etr_in>; 2418 }; 2419 }; 2420 2421 port@1 { 2422 reg = <1>; 2423 replicator_out1: endpoint { 2424 remote-endpoint = 2425 <&tpiu_in>; 2426 }; 2427 }; 2428 }; 2429 }; 2430 2431 etf@3027000 { 2432 compatible = "arm,coresight-tmc", "arm,primecell"; 2433 reg = <0x3027000 0x1000>; 2434 2435 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2436 clock-names = "apb_pclk", "atclk"; 2437 2438 in-ports { 2439 port { 2440 etf_in: endpoint { 2441 remote-endpoint = 2442 <&merge_funnel_out>; 2443 }; 2444 }; 2445 }; 2446 2447 out-ports { 2448 port { 2449 etf_out: endpoint { 2450 remote-endpoint = 2451 <&replicator_in>; 2452 }; 2453 }; 2454 }; 2455 }; 2456 2457 etr@3028000 { 2458 compatible = "arm,coresight-tmc", "arm,primecell"; 2459 reg = <0x3028000 0x1000>; 2460 2461 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2462 clock-names = "apb_pclk", "atclk"; 2463 arm,scatter-gather; 2464 2465 in-ports { 2466 port { 2467 etr_in: endpoint { 2468 remote-endpoint = 2469 <&replicator_out0>; 2470 }; 2471 }; 2472 }; 2473 }; 2474 2475 debug@3810000 { 2476 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2477 reg = <0x3810000 0x1000>; 2478 2479 clocks = <&rpmcc RPM_QDSS_CLK>; 2480 clock-names = "apb_pclk"; 2481 2482 cpu = <&CPU0>; 2483 }; 2484 2485 etm@3840000 { 2486 compatible = "arm,coresight-etm4x", "arm,primecell"; 2487 reg = <0x3840000 0x1000>; 2488 2489 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2490 clock-names = "apb_pclk", "atclk"; 2491 2492 cpu = <&CPU0>; 2493 2494 out-ports { 2495 port { 2496 etm0_out: endpoint { 2497 remote-endpoint = 2498 <&apss_funnel0_in0>; 2499 }; 2500 }; 2501 }; 2502 }; 2503 2504 debug@3910000 { 2505 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2506 reg = <0x3910000 0x1000>; 2507 2508 clocks = <&rpmcc RPM_QDSS_CLK>; 2509 clock-names = "apb_pclk"; 2510 2511 cpu = <&CPU1>; 2512 }; 2513 2514 etm@3940000 { 2515 compatible = "arm,coresight-etm4x", "arm,primecell"; 2516 reg = <0x3940000 0x1000>; 2517 2518 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2519 clock-names = "apb_pclk", "atclk"; 2520 2521 cpu = <&CPU1>; 2522 2523 out-ports { 2524 port { 2525 etm1_out: endpoint { 2526 remote-endpoint = 2527 <&apss_funnel0_in1>; 2528 }; 2529 }; 2530 }; 2531 }; 2532 2533 funnel@39b0000 { /* APSS Funnel 0 */ 2534 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2535 reg = <0x39b0000 0x1000>; 2536 2537 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2538 clock-names = "apb_pclk", "atclk"; 2539 2540 in-ports { 2541 #address-cells = <1>; 2542 #size-cells = <0>; 2543 2544 port@0 { 2545 reg = <0>; 2546 apss_funnel0_in0: endpoint { 2547 remote-endpoint = <&etm0_out>; 2548 }; 2549 }; 2550 2551 port@1 { 2552 reg = <1>; 2553 apss_funnel0_in1: endpoint { 2554 remote-endpoint = <&etm1_out>; 2555 }; 2556 }; 2557 }; 2558 2559 out-ports { 2560 port { 2561 apss_funnel0_out: endpoint { 2562 remote-endpoint = 2563 <&apss_merge_funnel_in0>; 2564 }; 2565 }; 2566 }; 2567 }; 2568 2569 debug@3a10000 { 2570 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2571 reg = <0x3a10000 0x1000>; 2572 2573 clocks = <&rpmcc RPM_QDSS_CLK>; 2574 clock-names = "apb_pclk"; 2575 2576 cpu = <&CPU2>; 2577 }; 2578 2579 etm@3a40000 { 2580 compatible = "arm,coresight-etm4x", "arm,primecell"; 2581 reg = <0x3a40000 0x1000>; 2582 2583 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2584 clock-names = "apb_pclk", "atclk"; 2585 2586 cpu = <&CPU2>; 2587 2588 out-ports { 2589 port { 2590 etm2_out: endpoint { 2591 remote-endpoint = 2592 <&apss_funnel1_in0>; 2593 }; 2594 }; 2595 }; 2596 }; 2597 2598 debug@3b10000 { 2599 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2600 reg = <0x3b10000 0x1000>; 2601 2602 clocks = <&rpmcc RPM_QDSS_CLK>; 2603 clock-names = "apb_pclk"; 2604 2605 cpu = <&CPU3>; 2606 }; 2607 2608 etm@3b40000 { 2609 compatible = "arm,coresight-etm4x", "arm,primecell"; 2610 reg = <0x3b40000 0x1000>; 2611 2612 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2613 clock-names = "apb_pclk", "atclk"; 2614 2615 cpu = <&CPU3>; 2616 2617 out-ports { 2618 port { 2619 etm3_out: endpoint { 2620 remote-endpoint = 2621 <&apss_funnel1_in1>; 2622 }; 2623 }; 2624 }; 2625 }; 2626 2627 funnel@3bb0000 { /* APSS Funnel 1 */ 2628 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2629 reg = <0x3bb0000 0x1000>; 2630 2631 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2632 clock-names = "apb_pclk", "atclk"; 2633 2634 in-ports { 2635 #address-cells = <1>; 2636 #size-cells = <0>; 2637 2638 port@0 { 2639 reg = <0>; 2640 apss_funnel1_in0: endpoint { 2641 remote-endpoint = <&etm2_out>; 2642 }; 2643 }; 2644 2645 port@1 { 2646 reg = <1>; 2647 apss_funnel1_in1: endpoint { 2648 remote-endpoint = <&etm3_out>; 2649 }; 2650 }; 2651 }; 2652 2653 out-ports { 2654 port { 2655 apss_funnel1_out: endpoint { 2656 remote-endpoint = 2657 <&apss_merge_funnel_in1>; 2658 }; 2659 }; 2660 }; 2661 }; 2662 2663 funnel@3bc0000 { 2664 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2665 reg = <0x3bc0000 0x1000>; 2666 2667 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2668 clock-names = "apb_pclk", "atclk"; 2669 2670 in-ports { 2671 #address-cells = <1>; 2672 #size-cells = <0>; 2673 2674 port@0 { 2675 reg = <0>; 2676 apss_merge_funnel_in0: endpoint { 2677 remote-endpoint = 2678 <&apss_funnel0_out>; 2679 }; 2680 }; 2681 2682 port@1 { 2683 reg = <1>; 2684 apss_merge_funnel_in1: endpoint { 2685 remote-endpoint = 2686 <&apss_funnel1_out>; 2687 }; 2688 }; 2689 }; 2690 2691 out-ports { 2692 port { 2693 apss_merge_funnel_out: endpoint { 2694 remote-endpoint = 2695 <&funnel1_in>; 2696 }; 2697 }; 2698 }; 2699 }; 2700 2701 kryocc: clock-controller@6400000 { 2702 compatible = "qcom,msm8996-apcc"; 2703 reg = <0x06400000 0x90000>; 2704 2705 clock-names = "xo"; 2706 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 2707 2708 #clock-cells = <1>; 2709 }; 2710 2711 usb3: usb@6af8800 { 2712 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2713 reg = <0x06af8800 0x400>; 2714 #address-cells = <1>; 2715 #size-cells = <1>; 2716 ranges; 2717 2718 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2720 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2721 2722 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2723 <&gcc GCC_USB30_MASTER_CLK>, 2724 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2725 <&gcc GCC_USB30_SLEEP_CLK>, 2726 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2727 clock-names = "cfg_noc", 2728 "core", 2729 "iface", 2730 "sleep", 2731 "mock_utmi"; 2732 2733 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2734 <&gcc GCC_USB30_MASTER_CLK>; 2735 assigned-clock-rates = <19200000>, <120000000>; 2736 2737 power-domains = <&gcc USB30_GDSC>; 2738 status = "disabled"; 2739 2740 usb3_dwc3: usb@6a00000 { 2741 compatible = "snps,dwc3"; 2742 reg = <0x06a00000 0xcc00>; 2743 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 2744 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 2745 phy-names = "usb2-phy", "usb3-phy"; 2746 snps,dis_u2_susphy_quirk; 2747 snps,dis_enblslpm_quirk; 2748 }; 2749 }; 2750 2751 usb3phy: phy@7410000 { 2752 compatible = "qcom,msm8996-qmp-usb3-phy"; 2753 reg = <0x07410000 0x1c4>; 2754 #address-cells = <1>; 2755 #size-cells = <1>; 2756 ranges; 2757 2758 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2759 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2760 <&gcc GCC_USB3_CLKREF_CLK>; 2761 clock-names = "aux", "cfg_ahb", "ref"; 2762 2763 resets = <&gcc GCC_USB3_PHY_BCR>, 2764 <&gcc GCC_USB3PHY_PHY_BCR>; 2765 reset-names = "phy", "common"; 2766 status = "disabled"; 2767 2768 ssusb_phy_0: phy@7410200 { 2769 reg = <0x07410200 0x200>, 2770 <0x07410400 0x130>, 2771 <0x07410600 0x1a8>; 2772 #phy-cells = <0>; 2773 2774 #clock-cells = <0>; 2775 clock-output-names = "usb3_phy_pipe_clk_src"; 2776 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2777 clock-names = "pipe0"; 2778 }; 2779 }; 2780 2781 hsusb_phy1: phy@7411000 { 2782 compatible = "qcom,msm8996-qusb2-phy"; 2783 reg = <0x07411000 0x180>; 2784 #phy-cells = <0>; 2785 2786 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2787 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2788 clock-names = "cfg_ahb", "ref"; 2789 2790 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2791 nvmem-cells = <&qusb2p_hstx_trim>; 2792 status = "disabled"; 2793 }; 2794 2795 hsusb_phy2: phy@7412000 { 2796 compatible = "qcom,msm8996-qusb2-phy"; 2797 reg = <0x07412000 0x180>; 2798 #phy-cells = <0>; 2799 2800 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2801 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 2802 clock-names = "cfg_ahb", "ref"; 2803 2804 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2805 nvmem-cells = <&qusb2s_hstx_trim>; 2806 status = "disabled"; 2807 }; 2808 2809 sdhc1: sdhci@7464900 { 2810 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 2811 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 2812 reg-names = "hc_mem", "core_mem"; 2813 2814 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2816 interrupt-names = "hc_irq", "pwr_irq"; 2817 2818 clock-names = "iface", "core", "xo"; 2819 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 2820 <&gcc GCC_SDCC1_APPS_CLK>, 2821 <&rpmcc RPM_SMD_BB_CLK1>; 2822 2823 pinctrl-names = "default", "sleep"; 2824 pinctrl-0 = <&sdc1_state_on>; 2825 pinctrl-1 = <&sdc1_state_off>; 2826 2827 bus-width = <8>; 2828 non-removable; 2829 status = "disabled"; 2830 }; 2831 2832 sdhc2: sdhci@74a4900 { 2833 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 2834 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 2835 reg-names = "hc_mem", "core_mem"; 2836 2837 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2839 interrupt-names = "hc_irq", "pwr_irq"; 2840 2841 clock-names = "iface", "core", "xo"; 2842 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2843 <&gcc GCC_SDCC2_APPS_CLK>, 2844 <&rpmcc RPM_SMD_BB_CLK1>; 2845 2846 pinctrl-names = "default", "sleep"; 2847 pinctrl-0 = <&sdc2_state_on>; 2848 pinctrl-1 = <&sdc2_state_off>; 2849 2850 bus-width = <4>; 2851 status = "disabled"; 2852 }; 2853 2854 blsp1_dma: dma-controller@7544000 { 2855 compatible = "qcom,bam-v1.7.0"; 2856 reg = <0x07544000 0x2b000>; 2857 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2858 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2859 clock-names = "bam_clk"; 2860 qcom,controlled-remotely; 2861 #dma-cells = <1>; 2862 qcom,ee = <0>; 2863 }; 2864 2865 blsp1_uart2: serial@7570000 { 2866 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2867 reg = <0x07570000 0x1000>; 2868 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2869 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 2870 <&gcc GCC_BLSP1_AHB_CLK>; 2871 clock-names = "core", "iface"; 2872 pinctrl-names = "default", "sleep"; 2873 pinctrl-0 = <&blsp1_uart2_default>; 2874 pinctrl-1 = <&blsp1_uart2_sleep>; 2875 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 2876 dma-names = "tx", "rx"; 2877 status = "disabled"; 2878 }; 2879 2880 blsp1_spi1: spi@7575000 { 2881 compatible = "qcom,spi-qup-v2.2.1"; 2882 reg = <0x07575000 0x600>; 2883 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2884 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2885 <&gcc GCC_BLSP1_AHB_CLK>; 2886 clock-names = "core", "iface"; 2887 pinctrl-names = "default", "sleep"; 2888 pinctrl-0 = <&blsp1_spi1_default>; 2889 pinctrl-1 = <&blsp1_spi1_sleep>; 2890 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2891 dma-names = "tx", "rx"; 2892 #address-cells = <1>; 2893 #size-cells = <0>; 2894 status = "disabled"; 2895 }; 2896 2897 blsp1_i2c3: i2c@7577000 { 2898 compatible = "qcom,i2c-qup-v2.2.1"; 2899 reg = <0x07577000 0x1000>; 2900 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2901 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2902 <&gcc GCC_BLSP1_AHB_CLK>; 2903 clock-names = "core", "iface"; 2904 pinctrl-names = "default", "sleep"; 2905 pinctrl-0 = <&blsp1_i2c3_default>; 2906 pinctrl-1 = <&blsp1_i2c3_sleep>; 2907 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2908 dma-names = "tx", "rx"; 2909 #address-cells = <1>; 2910 #size-cells = <0>; 2911 status = "disabled"; 2912 }; 2913 2914 blsp2_dma: dma-controller@7584000 { 2915 compatible = "qcom,bam-v1.7.0"; 2916 reg = <0x07584000 0x2b000>; 2917 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2918 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2919 clock-names = "bam_clk"; 2920 qcom,controlled-remotely; 2921 #dma-cells = <1>; 2922 qcom,ee = <0>; 2923 }; 2924 2925 blsp2_uart2: serial@75b0000 { 2926 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2927 reg = <0x075b0000 0x1000>; 2928 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2929 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2930 <&gcc GCC_BLSP2_AHB_CLK>; 2931 clock-names = "core", "iface"; 2932 status = "disabled"; 2933 }; 2934 2935 blsp2_uart3: serial@75b1000 { 2936 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2937 reg = <0x075b1000 0x1000>; 2938 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2939 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 2940 <&gcc GCC_BLSP2_AHB_CLK>; 2941 clock-names = "core", "iface"; 2942 status = "disabled"; 2943 }; 2944 2945 blsp2_i2c1: i2c@75b5000 { 2946 compatible = "qcom,i2c-qup-v2.2.1"; 2947 reg = <0x075b5000 0x1000>; 2948 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2949 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2950 <&gcc GCC_BLSP2_AHB_CLK>; 2951 clock-names = "core", "iface"; 2952 pinctrl-names = "default", "sleep"; 2953 pinctrl-0 = <&blsp2_i2c1_default>; 2954 pinctrl-1 = <&blsp2_i2c1_sleep>; 2955 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2956 dma-names = "tx", "rx"; 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 status = "disabled"; 2960 }; 2961 2962 blsp2_i2c2: i2c@75b6000 { 2963 compatible = "qcom,i2c-qup-v2.2.1"; 2964 reg = <0x075b6000 0x1000>; 2965 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2966 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2967 <&gcc GCC_BLSP2_AHB_CLK>; 2968 clock-names = "core", "iface"; 2969 pinctrl-names = "default", "sleep"; 2970 pinctrl-0 = <&blsp2_i2c2_default>; 2971 pinctrl-1 = <&blsp2_i2c2_sleep>; 2972 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2973 dma-names = "tx", "rx"; 2974 #address-cells = <1>; 2975 #size-cells = <0>; 2976 status = "disabled"; 2977 }; 2978 2979 blsp2_i2c3: i2c@75b7000 { 2980 compatible = "qcom,i2c-qup-v2.2.1"; 2981 reg = <0x075b7000 0x1000>; 2982 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2983 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2984 <&gcc GCC_BLSP2_AHB_CLK>; 2985 clock-names = "core", "iface"; 2986 clock-frequency = <400000>; 2987 pinctrl-names = "default", "sleep"; 2988 pinctrl-0 = <&blsp2_i2c3_default>; 2989 pinctrl-1 = <&blsp2_i2c3_sleep>; 2990 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2991 dma-names = "tx", "rx"; 2992 #address-cells = <1>; 2993 #size-cells = <0>; 2994 status = "disabled"; 2995 }; 2996 2997 blsp2_i2c5: i2c@75b9000 { 2998 compatible = "qcom,i2c-qup-v2.2.1"; 2999 reg = <0x75b9000 0x1000>; 3000 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3001 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3002 <&gcc GCC_BLSP2_AHB_CLK>; 3003 clock-names = "core", "iface"; 3004 pinctrl-names = "default"; 3005 pinctrl-0 = <&blsp2_i2c5_default>; 3006 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3007 dma-names = "tx", "rx"; 3008 #address-cells = <1>; 3009 #size-cells = <0>; 3010 status = "disabled"; 3011 }; 3012 3013 blsp2_i2c6: i2c@75ba000 { 3014 compatible = "qcom,i2c-qup-v2.2.1"; 3015 reg = <0x75ba000 0x1000>; 3016 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3017 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3018 <&gcc GCC_BLSP2_AHB_CLK>; 3019 clock-names = "core", "iface"; 3020 pinctrl-names = "default", "sleep"; 3021 pinctrl-0 = <&blsp2_i2c6_default>; 3022 pinctrl-1 = <&blsp2_i2c6_sleep>; 3023 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3024 dma-names = "tx", "rx"; 3025 #address-cells = <1>; 3026 #size-cells = <0>; 3027 status = "disabled"; 3028 }; 3029 3030 blsp2_spi6: spi@75ba000{ 3031 compatible = "qcom,spi-qup-v2.2.1"; 3032 reg = <0x075ba000 0x600>; 3033 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3034 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3035 <&gcc GCC_BLSP2_AHB_CLK>; 3036 clock-names = "core", "iface"; 3037 pinctrl-names = "default", "sleep"; 3038 pinctrl-0 = <&blsp2_spi6_default>; 3039 pinctrl-1 = <&blsp2_spi6_sleep>; 3040 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3041 dma-names = "tx", "rx"; 3042 #address-cells = <1>; 3043 #size-cells = <0>; 3044 status = "disabled"; 3045 }; 3046 3047 usb2: usb@76f8800 { 3048 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3049 reg = <0x076f8800 0x400>; 3050 #address-cells = <1>; 3051 #size-cells = <1>; 3052 ranges; 3053 3054 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3055 <&gcc GCC_USB20_MASTER_CLK>, 3056 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3057 <&gcc GCC_USB20_SLEEP_CLK>, 3058 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3059 clock-names = "cfg_noc", 3060 "core", 3061 "iface", 3062 "sleep", 3063 "mock_utmi"; 3064 3065 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3066 <&gcc GCC_USB20_MASTER_CLK>; 3067 assigned-clock-rates = <19200000>, <60000000>; 3068 3069 power-domains = <&gcc USB30_GDSC>; 3070 qcom,select-utmi-as-pipe-clk; 3071 status = "disabled"; 3072 3073 usb2_dwc3: usb@7600000 { 3074 compatible = "snps,dwc3"; 3075 reg = <0x07600000 0xcc00>; 3076 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3077 phys = <&hsusb_phy2>; 3078 phy-names = "usb2-phy"; 3079 maximum-speed = "high-speed"; 3080 snps,dis_u2_susphy_quirk; 3081 snps,dis_enblslpm_quirk; 3082 }; 3083 }; 3084 3085 slimbam: dma-controller@9184000 { 3086 compatible = "qcom,bam-v1.7.0"; 3087 qcom,controlled-remotely; 3088 reg = <0x09184000 0x32000>; 3089 num-channels = <31>; 3090 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3091 #dma-cells = <1>; 3092 qcom,ee = <1>; 3093 qcom,num-ees = <2>; 3094 }; 3095 3096 slim_msm: slim@91c0000 { 3097 compatible = "qcom,slim-ngd-v1.5.0"; 3098 reg = <0x091c0000 0x2C000>; 3099 reg-names = "ctrl"; 3100 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3101 dmas = <&slimbam 3>, <&slimbam 4>, 3102 <&slimbam 5>, <&slimbam 6>; 3103 dma-names = "rx", "tx", "tx2", "rx2"; 3104 #address-cells = <1>; 3105 #size-cells = <0>; 3106 ngd@1 { 3107 reg = <1>; 3108 #address-cells = <1>; 3109 #size-cells = <1>; 3110 3111 tasha_ifd: tas-ifd { 3112 compatible = "slim217,1a0"; 3113 reg = <0 0>; 3114 }; 3115 3116 wcd9335: codec@1{ 3117 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3118 pinctrl-names = "default"; 3119 3120 compatible = "slim217,1a0"; 3121 reg = <1 0>; 3122 3123 interrupt-parent = <&tlmm>; 3124 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3125 <53 IRQ_TYPE_LEVEL_HIGH>; 3126 interrupt-names = "intr1", "intr2"; 3127 interrupt-controller; 3128 #interrupt-cells = <1>; 3129 reset-gpios = <&tlmm 64 0>; 3130 3131 slim-ifc-dev = <&tasha_ifd>; 3132 3133 #sound-dai-cells = <1>; 3134 }; 3135 }; 3136 }; 3137 3138 adsp_pil: remoteproc@9300000 { 3139 compatible = "qcom,msm8996-adsp-pil"; 3140 reg = <0x09300000 0x80000>; 3141 3142 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3143 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3144 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3145 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3146 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3147 interrupt-names = "wdog", "fatal", "ready", 3148 "handover", "stop-ack"; 3149 3150 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 3151 clock-names = "xo"; 3152 3153 memory-region = <&adsp_mem>; 3154 3155 qcom,smem-states = <&adsp_smp2p_out 0>; 3156 qcom,smem-state-names = "stop"; 3157 3158 power-domains = <&rpmpd MSM8996_VDDCX>; 3159 power-domain-names = "cx"; 3160 3161 status = "disabled"; 3162 3163 smd-edge { 3164 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3165 3166 label = "lpass"; 3167 mboxes = <&apcs_glb 8>; 3168 qcom,smd-edge = <1>; 3169 qcom,remote-pid = <2>; 3170 #address-cells = <1>; 3171 #size-cells = <0>; 3172 apr { 3173 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3174 compatible = "qcom,apr-v2"; 3175 qcom,smd-channels = "apr_audio_svc"; 3176 qcom,domain = <APR_DOMAIN_ADSP>; 3177 #address-cells = <1>; 3178 #size-cells = <0>; 3179 3180 q6core { 3181 reg = <APR_SVC_ADSP_CORE>; 3182 compatible = "qcom,q6core"; 3183 }; 3184 3185 q6afe: q6afe { 3186 compatible = "qcom,q6afe"; 3187 reg = <APR_SVC_AFE>; 3188 q6afedai: dais { 3189 compatible = "qcom,q6afe-dais"; 3190 #address-cells = <1>; 3191 #size-cells = <0>; 3192 #sound-dai-cells = <1>; 3193 hdmi@1 { 3194 reg = <1>; 3195 }; 3196 }; 3197 }; 3198 3199 q6asm: q6asm { 3200 compatible = "qcom,q6asm"; 3201 reg = <APR_SVC_ASM>; 3202 q6asmdai: dais { 3203 compatible = "qcom,q6asm-dais"; 3204 #address-cells = <1>; 3205 #size-cells = <0>; 3206 #sound-dai-cells = <1>; 3207 iommus = <&lpass_q6_smmu 1>; 3208 }; 3209 }; 3210 3211 q6adm: q6adm { 3212 compatible = "qcom,q6adm"; 3213 reg = <APR_SVC_ADM>; 3214 q6routing: routing { 3215 compatible = "qcom,q6adm-routing"; 3216 #sound-dai-cells = <0>; 3217 }; 3218 }; 3219 }; 3220 3221 }; 3222 }; 3223 3224 apcs_glb: mailbox@9820000 { 3225 compatible = "qcom,msm8996-apcs-hmss-global"; 3226 reg = <0x09820000 0x1000>; 3227 3228 #mbox-cells = <1>; 3229 }; 3230 3231 timer@9840000 { 3232 #address-cells = <1>; 3233 #size-cells = <1>; 3234 ranges; 3235 compatible = "arm,armv7-timer-mem"; 3236 reg = <0x09840000 0x1000>; 3237 clock-frequency = <19200000>; 3238 3239 frame@9850000 { 3240 frame-number = <0>; 3241 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3243 reg = <0x09850000 0x1000>, 3244 <0x09860000 0x1000>; 3245 }; 3246 3247 frame@9870000 { 3248 frame-number = <1>; 3249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3250 reg = <0x09870000 0x1000>; 3251 status = "disabled"; 3252 }; 3253 3254 frame@9880000 { 3255 frame-number = <2>; 3256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3257 reg = <0x09880000 0x1000>; 3258 status = "disabled"; 3259 }; 3260 3261 frame@9890000 { 3262 frame-number = <3>; 3263 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3264 reg = <0x09890000 0x1000>; 3265 status = "disabled"; 3266 }; 3267 3268 frame@98a0000 { 3269 frame-number = <4>; 3270 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3271 reg = <0x098a0000 0x1000>; 3272 status = "disabled"; 3273 }; 3274 3275 frame@98b0000 { 3276 frame-number = <5>; 3277 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3278 reg = <0x098b0000 0x1000>; 3279 status = "disabled"; 3280 }; 3281 3282 frame@98c0000 { 3283 frame-number = <6>; 3284 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3285 reg = <0x098c0000 0x1000>; 3286 status = "disabled"; 3287 }; 3288 }; 3289 3290 saw3: syscon@9a10000 { 3291 compatible = "syscon"; 3292 reg = <0x09a10000 0x1000>; 3293 }; 3294 3295 intc: interrupt-controller@9bc0000 { 3296 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3297 #interrupt-cells = <3>; 3298 interrupt-controller; 3299 #redistributor-regions = <1>; 3300 redistributor-stride = <0x0 0x40000>; 3301 reg = <0x09bc0000 0x10000>, 3302 <0x09c00000 0x100000>; 3303 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3304 }; 3305 }; 3306 3307 sound: sound { 3308 }; 3309 3310 thermal-zones { 3311 cpu0-thermal { 3312 polling-delay-passive = <250>; 3313 polling-delay = <1000>; 3314 3315 thermal-sensors = <&tsens0 3>; 3316 3317 trips { 3318 cpu0_alert0: trip-point0 { 3319 temperature = <75000>; 3320 hysteresis = <2000>; 3321 type = "passive"; 3322 }; 3323 3324 cpu0_crit: cpu_crit { 3325 temperature = <110000>; 3326 hysteresis = <2000>; 3327 type = "critical"; 3328 }; 3329 }; 3330 }; 3331 3332 cpu1-thermal { 3333 polling-delay-passive = <250>; 3334 polling-delay = <1000>; 3335 3336 thermal-sensors = <&tsens0 5>; 3337 3338 trips { 3339 cpu1_alert0: trip-point0 { 3340 temperature = <75000>; 3341 hysteresis = <2000>; 3342 type = "passive"; 3343 }; 3344 3345 cpu1_crit: cpu_crit { 3346 temperature = <110000>; 3347 hysteresis = <2000>; 3348 type = "critical"; 3349 }; 3350 }; 3351 }; 3352 3353 cpu2-thermal { 3354 polling-delay-passive = <250>; 3355 polling-delay = <1000>; 3356 3357 thermal-sensors = <&tsens0 8>; 3358 3359 trips { 3360 cpu2_alert0: trip-point0 { 3361 temperature = <75000>; 3362 hysteresis = <2000>; 3363 type = "passive"; 3364 }; 3365 3366 cpu2_crit: cpu_crit { 3367 temperature = <110000>; 3368 hysteresis = <2000>; 3369 type = "critical"; 3370 }; 3371 }; 3372 }; 3373 3374 cpu3-thermal { 3375 polling-delay-passive = <250>; 3376 polling-delay = <1000>; 3377 3378 thermal-sensors = <&tsens0 10>; 3379 3380 trips { 3381 cpu3_alert0: trip-point0 { 3382 temperature = <75000>; 3383 hysteresis = <2000>; 3384 type = "passive"; 3385 }; 3386 3387 cpu3_crit: cpu_crit { 3388 temperature = <110000>; 3389 hysteresis = <2000>; 3390 type = "critical"; 3391 }; 3392 }; 3393 }; 3394 3395 gpu-top-thermal { 3396 polling-delay-passive = <250>; 3397 polling-delay = <1000>; 3398 3399 thermal-sensors = <&tsens1 6>; 3400 3401 trips { 3402 gpu1_alert0: trip-point0 { 3403 temperature = <90000>; 3404 hysteresis = <2000>; 3405 type = "passive"; 3406 }; 3407 }; 3408 3409 cooling-maps { 3410 map0 { 3411 trip = <&gpu1_alert0>; 3412 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3413 }; 3414 }; 3415 }; 3416 3417 gpu-bottom-thermal { 3418 polling-delay-passive = <250>; 3419 polling-delay = <1000>; 3420 3421 thermal-sensors = <&tsens1 7>; 3422 3423 trips { 3424 gpu2_alert0: trip-point0 { 3425 temperature = <90000>; 3426 hysteresis = <2000>; 3427 type = "passive"; 3428 }; 3429 }; 3430 3431 cooling-maps { 3432 map0 { 3433 trip = <&gpu2_alert0>; 3434 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3435 }; 3436 }; 3437 }; 3438 3439 m4m-thermal { 3440 polling-delay-passive = <250>; 3441 polling-delay = <1000>; 3442 3443 thermal-sensors = <&tsens0 1>; 3444 3445 trips { 3446 m4m_alert0: trip-point0 { 3447 temperature = <90000>; 3448 hysteresis = <2000>; 3449 type = "hot"; 3450 }; 3451 }; 3452 }; 3453 3454 l3-or-venus-thermal { 3455 polling-delay-passive = <250>; 3456 polling-delay = <1000>; 3457 3458 thermal-sensors = <&tsens0 2>; 3459 3460 trips { 3461 l3_or_venus_alert0: trip-point0 { 3462 temperature = <90000>; 3463 hysteresis = <2000>; 3464 type = "hot"; 3465 }; 3466 }; 3467 }; 3468 3469 cluster0-l2-thermal { 3470 polling-delay-passive = <250>; 3471 polling-delay = <1000>; 3472 3473 thermal-sensors = <&tsens0 7>; 3474 3475 trips { 3476 cluster0_l2_alert0: trip-point0 { 3477 temperature = <90000>; 3478 hysteresis = <2000>; 3479 type = "hot"; 3480 }; 3481 }; 3482 }; 3483 3484 cluster1-l2-thermal { 3485 polling-delay-passive = <250>; 3486 polling-delay = <1000>; 3487 3488 thermal-sensors = <&tsens0 12>; 3489 3490 trips { 3491 cluster1_l2_alert0: trip-point0 { 3492 temperature = <90000>; 3493 hysteresis = <2000>; 3494 type = "hot"; 3495 }; 3496 }; 3497 }; 3498 3499 camera-thermal { 3500 polling-delay-passive = <250>; 3501 polling-delay = <1000>; 3502 3503 thermal-sensors = <&tsens1 1>; 3504 3505 trips { 3506 camera_alert0: trip-point0 { 3507 temperature = <90000>; 3508 hysteresis = <2000>; 3509 type = "hot"; 3510 }; 3511 }; 3512 }; 3513 3514 q6-dsp-thermal { 3515 polling-delay-passive = <250>; 3516 polling-delay = <1000>; 3517 3518 thermal-sensors = <&tsens1 2>; 3519 3520 trips { 3521 q6_dsp_alert0: trip-point0 { 3522 temperature = <90000>; 3523 hysteresis = <2000>; 3524 type = "hot"; 3525 }; 3526 }; 3527 }; 3528 3529 mem-thermal { 3530 polling-delay-passive = <250>; 3531 polling-delay = <1000>; 3532 3533 thermal-sensors = <&tsens1 3>; 3534 3535 trips { 3536 mem_alert0: trip-point0 { 3537 temperature = <90000>; 3538 hysteresis = <2000>; 3539 type = "hot"; 3540 }; 3541 }; 3542 }; 3543 3544 modemtx-thermal { 3545 polling-delay-passive = <250>; 3546 polling-delay = <1000>; 3547 3548 thermal-sensors = <&tsens1 4>; 3549 3550 trips { 3551 modemtx_alert0: trip-point0 { 3552 temperature = <90000>; 3553 hysteresis = <2000>; 3554 type = "hot"; 3555 }; 3556 }; 3557 }; 3558 }; 3559 3560 timer { 3561 compatible = "arm,armv8-timer"; 3562 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3563 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3564 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3565 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3566 }; 3567}; 3568