1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra186-clock.h>
3#include <dt-bindings/gpio/tegra186-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/memory/tegra186-mc.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8#include <dt-bindings/power/tegra186-powergate.h>
9#include <dt-bindings/reset/tegra186-reset.h>
10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12/ {
13	compatible = "nvidia,tegra186";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	misc@100000 {
19		compatible = "nvidia,tegra186-misc";
20		reg = <0x0 0x00100000 0x0 0xf000>,
21		      <0x0 0x0010f000 0x0 0x1000>;
22	};
23
24	gpio: gpio@2200000 {
25		compatible = "nvidia,tegra186-gpio";
26		reg-names = "security", "gpio";
27		reg = <0x0 0x2200000 0x0 0x10000>,
28		      <0x0 0x2210000 0x0 0x10000>;
29		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
30			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35		#interrupt-cells = <2>;
36		interrupt-controller;
37		#gpio-cells = <2>;
38		gpio-controller;
39	};
40
41	ethernet@2490000 {
42		compatible = "nvidia,tegra186-eqos",
43			     "snps,dwc-qos-ethernet-4.10";
44		reg = <0x0 0x02490000 0x0 0x10000>;
45		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57			 <&bpmp TEGRA186_CLK_EQOS_RX>,
58			 <&bpmp TEGRA186_CLK_EQOS_TX>,
59			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61		resets = <&bpmp TEGRA186_RESET_EQOS>;
62		reset-names = "eqos";
63		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65		interconnect-names = "dma-mem", "write";
66		iommus = <&smmu TEGRA186_SID_EQOS>;
67		status = "disabled";
68
69		snps,write-requests = <1>;
70		snps,read-requests = <3>;
71		snps,burst-map = <0x7>;
72		snps,txpbl = <32>;
73		snps,rxpbl = <8>;
74	};
75
76	gpcdma: dma-controller@2600000 {
77		compatible = "nvidia,tegra186-gpcdma";
78		reg = <0x0 0x2600000 0x0 0x210000>;
79		resets = <&bpmp TEGRA186_RESET_GPCDMA>;
80		reset-names = "gpcdma";
81		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
85			     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
86			     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
87			     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
88			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
89			     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
90			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
91			     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
92			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
93			     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
94			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
95			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
96			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
97			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
98			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
99			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
100			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
101			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
102			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
103			     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
104			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
105			     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
106			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
107			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
108			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
109			     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
110			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
111			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
112		#dma-cells = <1>;
113		iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
114		dma-coherent;
115		status = "okay";
116	};
117
118	aconnect@2900000 {
119		compatible = "nvidia,tegra186-aconnect",
120			     "nvidia,tegra210-aconnect";
121		clocks = <&bpmp TEGRA186_CLK_APE>,
122			 <&bpmp TEGRA186_CLK_APB2APE>;
123		clock-names = "ape", "apb2ape";
124		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
125		#address-cells = <1>;
126		#size-cells = <1>;
127		ranges = <0x02900000 0x0 0x02900000 0x200000>;
128		status = "disabled";
129
130		adma: dma-controller@2930000 {
131			compatible = "nvidia,tegra186-adma";
132			reg = <0x02930000 0x20000>;
133			interrupt-parent = <&agic>;
134			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
136				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
137				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
138				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
139				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
140				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
141				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
142				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
143				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
144				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
145				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
146				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
147				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
148				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
149				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
150				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
151				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
152				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
153				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
154				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
155				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
156				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
157				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
158				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
159				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
160				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
161				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
162				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
163				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
164				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
165				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
166			#dma-cells = <1>;
167			clocks = <&bpmp TEGRA186_CLK_AHUB>;
168			clock-names = "d_audio";
169			status = "disabled";
170		};
171
172		agic: interrupt-controller@2a40000 {
173			compatible = "nvidia,tegra186-agic",
174				     "nvidia,tegra210-agic";
175			#interrupt-cells = <3>;
176			interrupt-controller;
177			reg = <0x02a41000 0x1000>,
178			      <0x02a42000 0x2000>;
179			interrupts = <GIC_SPI 145
180				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
181			clocks = <&bpmp TEGRA186_CLK_APE>;
182			clock-names = "clk";
183			status = "disabled";
184		};
185
186		tegra_ahub: ahub@2900800 {
187			compatible = "nvidia,tegra186-ahub";
188			reg = <0x02900800 0x800>;
189			clocks = <&bpmp TEGRA186_CLK_AHUB>;
190			clock-names = "ahub";
191			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
192			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
193			#address-cells = <1>;
194			#size-cells = <1>;
195			ranges = <0x02900800 0x02900800 0x11800>;
196			status = "disabled";
197
198			tegra_admaif: admaif@290f000 {
199				compatible = "nvidia,tegra186-admaif";
200				reg = <0x0290f000 0x1000>;
201				dmas = <&adma 1>, <&adma 1>,
202				       <&adma 2>, <&adma 2>,
203				       <&adma 3>, <&adma 3>,
204				       <&adma 4>, <&adma 4>,
205				       <&adma 5>, <&adma 5>,
206				       <&adma 6>, <&adma 6>,
207				       <&adma 7>, <&adma 7>,
208				       <&adma 8>, <&adma 8>,
209				       <&adma 9>, <&adma 9>,
210				       <&adma 10>, <&adma 10>,
211				       <&adma 11>, <&adma 11>,
212				       <&adma 12>, <&adma 12>,
213				       <&adma 13>, <&adma 13>,
214				       <&adma 14>, <&adma 14>,
215				       <&adma 15>, <&adma 15>,
216				       <&adma 16>, <&adma 16>,
217				       <&adma 17>, <&adma 17>,
218				       <&adma 18>, <&adma 18>,
219				       <&adma 19>, <&adma 19>,
220				       <&adma 20>, <&adma 20>;
221				dma-names = "rx1", "tx1",
222					    "rx2", "tx2",
223					    "rx3", "tx3",
224					    "rx4", "tx4",
225					    "rx5", "tx5",
226					    "rx6", "tx6",
227					    "rx7", "tx7",
228					    "rx8", "tx8",
229					    "rx9", "tx9",
230					    "rx10", "tx10",
231					    "rx11", "tx11",
232					    "rx12", "tx12",
233					    "rx13", "tx13",
234					    "rx14", "tx14",
235					    "rx15", "tx15",
236					    "rx16", "tx16",
237					    "rx17", "tx17",
238					    "rx18", "tx18",
239					    "rx19", "tx19",
240					    "rx20", "tx20";
241				status = "disabled";
242			};
243
244			tegra_i2s1: i2s@2901000 {
245				compatible = "nvidia,tegra186-i2s",
246					     "nvidia,tegra210-i2s";
247				reg = <0x2901000 0x100>;
248				clocks = <&bpmp TEGRA186_CLK_I2S1>,
249					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
250				clock-names = "i2s", "sync_input";
251				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
252				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253				assigned-clock-rates = <1536000>;
254				sound-name-prefix = "I2S1";
255				status = "disabled";
256			};
257
258			tegra_i2s2: i2s@2901100 {
259				compatible = "nvidia,tegra186-i2s",
260					     "nvidia,tegra210-i2s";
261				reg = <0x2901100 0x100>;
262				clocks = <&bpmp TEGRA186_CLK_I2S2>,
263					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
264				clock-names = "i2s", "sync_input";
265				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
266				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267				assigned-clock-rates = <1536000>;
268				sound-name-prefix = "I2S2";
269				status = "disabled";
270			};
271
272			tegra_i2s3: i2s@2901200 {
273				compatible = "nvidia,tegra186-i2s",
274					     "nvidia,tegra210-i2s";
275				reg = <0x2901200 0x100>;
276				clocks = <&bpmp TEGRA186_CLK_I2S3>,
277					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
278				clock-names = "i2s", "sync_input";
279				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
280				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281				assigned-clock-rates = <1536000>;
282				sound-name-prefix = "I2S3";
283				status = "disabled";
284			};
285
286			tegra_i2s4: i2s@2901300 {
287				compatible = "nvidia,tegra186-i2s",
288					     "nvidia,tegra210-i2s";
289				reg = <0x2901300 0x100>;
290				clocks = <&bpmp TEGRA186_CLK_I2S4>,
291					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
292				clock-names = "i2s", "sync_input";
293				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
294				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
295				assigned-clock-rates = <1536000>;
296				sound-name-prefix = "I2S4";
297				status = "disabled";
298			};
299
300			tegra_i2s5: i2s@2901400 {
301				compatible = "nvidia,tegra186-i2s",
302					     "nvidia,tegra210-i2s";
303				reg = <0x2901400 0x100>;
304				clocks = <&bpmp TEGRA186_CLK_I2S5>,
305					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
306				clock-names = "i2s", "sync_input";
307				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
308				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
309				assigned-clock-rates = <1536000>;
310				sound-name-prefix = "I2S5";
311				status = "disabled";
312			};
313
314			tegra_i2s6: i2s@2901500 {
315				compatible = "nvidia,tegra186-i2s",
316					     "nvidia,tegra210-i2s";
317				reg = <0x2901500 0x100>;
318				clocks = <&bpmp TEGRA186_CLK_I2S6>,
319					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
320				clock-names = "i2s", "sync_input";
321				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
322				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
323				assigned-clock-rates = <1536000>;
324				sound-name-prefix = "I2S6";
325				status = "disabled";
326			};
327
328			tegra_dmic1: dmic@2904000 {
329				compatible = "nvidia,tegra210-dmic";
330				reg = <0x2904000 0x100>;
331				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
332				clock-names = "dmic";
333				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
334				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
335				assigned-clock-rates = <3072000>;
336				sound-name-prefix = "DMIC1";
337				status = "disabled";
338			};
339
340			tegra_dmic2: dmic@2904100 {
341				compatible = "nvidia,tegra210-dmic";
342				reg = <0x2904100 0x100>;
343				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
344				clock-names = "dmic";
345				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
346				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
347				assigned-clock-rates = <3072000>;
348				sound-name-prefix = "DMIC2";
349				status = "disabled";
350			};
351
352			tegra_dmic3: dmic@2904200 {
353				compatible = "nvidia,tegra210-dmic";
354				reg = <0x2904200 0x100>;
355				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
356				clock-names = "dmic";
357				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
358				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
359				assigned-clock-rates = <3072000>;
360				sound-name-prefix = "DMIC3";
361				status = "disabled";
362			};
363
364			tegra_dmic4: dmic@2904300 {
365				compatible = "nvidia,tegra210-dmic";
366				reg = <0x2904300 0x100>;
367				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
368				clock-names = "dmic";
369				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
370				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
371				assigned-clock-rates = <3072000>;
372				sound-name-prefix = "DMIC4";
373				status = "disabled";
374			};
375
376			tegra_dspk1: dspk@2905000 {
377				compatible = "nvidia,tegra186-dspk";
378				reg = <0x2905000 0x100>;
379				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
380				clock-names = "dspk";
381				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
382				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
383				assigned-clock-rates = <12288000>;
384				sound-name-prefix = "DSPK1";
385				status = "disabled";
386			};
387
388			tegra_dspk2: dspk@2905100 {
389				compatible = "nvidia,tegra186-dspk";
390				reg = <0x2905100 0x100>;
391				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
392				clock-names = "dspk";
393				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
394				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
395				assigned-clock-rates = <12288000>;
396				sound-name-prefix = "DSPK2";
397				status = "disabled";
398			};
399
400			tegra_sfc1: sfc@2902000 {
401				compatible = "nvidia,tegra186-sfc",
402					     "nvidia,tegra210-sfc";
403				reg = <0x2902000 0x200>;
404				sound-name-prefix = "SFC1";
405				status = "disabled";
406			};
407
408			tegra_sfc2: sfc@2902200 {
409				compatible = "nvidia,tegra186-sfc",
410					     "nvidia,tegra210-sfc";
411				reg = <0x2902200 0x200>;
412				sound-name-prefix = "SFC2";
413				status = "disabled";
414			};
415
416			tegra_sfc3: sfc@2902400 {
417				compatible = "nvidia,tegra186-sfc",
418					     "nvidia,tegra210-sfc";
419				reg = <0x2902400 0x200>;
420				sound-name-prefix = "SFC3";
421				status = "disabled";
422			};
423
424			tegra_sfc4: sfc@2902600 {
425				compatible = "nvidia,tegra186-sfc",
426					     "nvidia,tegra210-sfc";
427				reg = <0x2902600 0x200>;
428				sound-name-prefix = "SFC4";
429				status = "disabled";
430			};
431
432			tegra_mvc1: mvc@290a000 {
433				compatible = "nvidia,tegra186-mvc",
434					     "nvidia,tegra210-mvc";
435				reg = <0x290a000 0x200>;
436				sound-name-prefix = "MVC1";
437				status = "disabled";
438			};
439
440			tegra_mvc2: mvc@290a200 {
441				compatible = "nvidia,tegra186-mvc",
442					     "nvidia,tegra210-mvc";
443				reg = <0x290a200 0x200>;
444				sound-name-prefix = "MVC2";
445				status = "disabled";
446			};
447
448			tegra_amx1: amx@2903000 {
449				compatible = "nvidia,tegra186-amx",
450					     "nvidia,tegra210-amx";
451				reg = <0x2903000 0x100>;
452				sound-name-prefix = "AMX1";
453				status = "disabled";
454			};
455
456			tegra_amx2: amx@2903100 {
457				compatible = "nvidia,tegra186-amx",
458					     "nvidia,tegra210-amx";
459				reg = <0x2903100 0x100>;
460				sound-name-prefix = "AMX2";
461				status = "disabled";
462			};
463
464			tegra_amx3: amx@2903200 {
465				compatible = "nvidia,tegra186-amx",
466					     "nvidia,tegra210-amx";
467				reg = <0x2903200 0x100>;
468				sound-name-prefix = "AMX3";
469				status = "disabled";
470			};
471
472			tegra_amx4: amx@2903300 {
473				compatible = "nvidia,tegra186-amx",
474					     "nvidia,tegra210-amx";
475				reg = <0x2903300 0x100>;
476				sound-name-prefix = "AMX4";
477				status = "disabled";
478			};
479
480			tegra_adx1: adx@2903800 {
481				compatible = "nvidia,tegra186-adx",
482					     "nvidia,tegra210-adx";
483				reg = <0x2903800 0x100>;
484				sound-name-prefix = "ADX1";
485				status = "disabled";
486			};
487
488			tegra_adx2: adx@2903900 {
489				compatible = "nvidia,tegra186-adx",
490					     "nvidia,tegra210-adx";
491				reg = <0x2903900 0x100>;
492				sound-name-prefix = "ADX2";
493				status = "disabled";
494			};
495
496			tegra_adx3: adx@2903a00 {
497				compatible = "nvidia,tegra186-adx",
498					     "nvidia,tegra210-adx";
499				reg = <0x2903a00 0x100>;
500				sound-name-prefix = "ADX3";
501				status = "disabled";
502			};
503
504			tegra_adx4: adx@2903b00 {
505				compatible = "nvidia,tegra186-adx",
506					     "nvidia,tegra210-adx";
507				reg = <0x2903b00 0x100>;
508				sound-name-prefix = "ADX4";
509				status = "disabled";
510			};
511
512			tegra_amixer: amixer@290bb00 {
513				compatible = "nvidia,tegra186-amixer",
514					     "nvidia,tegra210-amixer";
515				reg = <0x290bb00 0x800>;
516				sound-name-prefix = "MIXER1";
517				status = "disabled";
518			};
519
520			tegra_asrc: asrc@2910000 {
521				compatible = "nvidia,tegra186-asrc";
522				reg = <0x2910000 0x2000>;
523				sound-name-prefix = "ASRC1";
524				status = "disabled";
525			};
526		};
527	};
528
529	mc: memory-controller@2c00000 {
530		compatible = "nvidia,tegra186-mc";
531		reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
532		      <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
533		      <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
534		      <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
535		      <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
536		      <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
537		reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
538		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
539		status = "disabled";
540
541		#interconnect-cells = <1>;
542		#address-cells = <2>;
543		#size-cells = <2>;
544
545		ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
546
547		/*
548		 * Memory clients have access to all 40 bits that the memory
549		 * controller can address.
550		 */
551		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
552
553		emc: external-memory-controller@2c60000 {
554			compatible = "nvidia,tegra186-emc";
555			reg = <0x0 0x02c60000 0x0 0x50000>;
556			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
557			clocks = <&bpmp TEGRA186_CLK_EMC>;
558			clock-names = "emc";
559
560			#interconnect-cells = <0>;
561
562			nvidia,bpmp = <&bpmp>;
563		};
564	};
565
566	timer@3010000 {
567		compatible = "nvidia,tegra186-timer";
568		reg = <0x0 0x03010000 0x0 0x000e0000>;
569		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
570			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
571			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
572			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
573			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
574			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
575			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
576			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
577			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
578			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
579		status = "disabled";
580	};
581
582	uarta: serial@3100000 {
583		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
584		reg = <0x0 0x03100000 0x0 0x40>;
585		reg-shift = <2>;
586		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
587		clocks = <&bpmp TEGRA186_CLK_UARTA>;
588		clock-names = "serial";
589		resets = <&bpmp TEGRA186_RESET_UARTA>;
590		reset-names = "serial";
591		status = "disabled";
592	};
593
594	uartb: serial@3110000 {
595		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
596		reg = <0x0 0x03110000 0x0 0x40>;
597		reg-shift = <2>;
598		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
599		clocks = <&bpmp TEGRA186_CLK_UARTB>;
600		clock-names = "serial";
601		resets = <&bpmp TEGRA186_RESET_UARTB>;
602		reset-names = "serial";
603		status = "disabled";
604	};
605
606	uartd: serial@3130000 {
607		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
608		reg = <0x0 0x03130000 0x0 0x40>;
609		reg-shift = <2>;
610		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
611		clocks = <&bpmp TEGRA186_CLK_UARTD>;
612		clock-names = "serial";
613		resets = <&bpmp TEGRA186_RESET_UARTD>;
614		reset-names = "serial";
615		status = "disabled";
616	};
617
618	uarte: serial@3140000 {
619		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
620		reg = <0x0 0x03140000 0x0 0x40>;
621		reg-shift = <2>;
622		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
623		clocks = <&bpmp TEGRA186_CLK_UARTE>;
624		clock-names = "serial";
625		resets = <&bpmp TEGRA186_RESET_UARTE>;
626		reset-names = "serial";
627		status = "disabled";
628	};
629
630	uartf: serial@3150000 {
631		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
632		reg = <0x0 0x03150000 0x0 0x40>;
633		reg-shift = <2>;
634		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
635		clocks = <&bpmp TEGRA186_CLK_UARTF>;
636		clock-names = "serial";
637		resets = <&bpmp TEGRA186_RESET_UARTF>;
638		reset-names = "serial";
639		status = "disabled";
640	};
641
642	gen1_i2c: i2c@3160000 {
643		compatible = "nvidia,tegra186-i2c";
644		reg = <0x0 0x03160000 0x0 0x10000>;
645		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
646		#address-cells = <1>;
647		#size-cells = <0>;
648		clocks = <&bpmp TEGRA186_CLK_I2C1>;
649		clock-names = "div-clk";
650		resets = <&bpmp TEGRA186_RESET_I2C1>;
651		reset-names = "i2c";
652		status = "disabled";
653	};
654
655	cam_i2c: i2c@3180000 {
656		compatible = "nvidia,tegra186-i2c";
657		reg = <0x0 0x03180000 0x0 0x10000>;
658		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
659		#address-cells = <1>;
660		#size-cells = <0>;
661		clocks = <&bpmp TEGRA186_CLK_I2C3>;
662		clock-names = "div-clk";
663		resets = <&bpmp TEGRA186_RESET_I2C3>;
664		reset-names = "i2c";
665		status = "disabled";
666	};
667
668	/* shares pads with dpaux1 */
669	dp_aux_ch1_i2c: i2c@3190000 {
670		compatible = "nvidia,tegra186-i2c";
671		reg = <0x0 0x03190000 0x0 0x10000>;
672		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
673		#address-cells = <1>;
674		#size-cells = <0>;
675		clocks = <&bpmp TEGRA186_CLK_I2C4>;
676		clock-names = "div-clk";
677		resets = <&bpmp TEGRA186_RESET_I2C4>;
678		reset-names = "i2c";
679		pinctrl-names = "default", "idle";
680		pinctrl-0 = <&state_dpaux1_i2c>;
681		pinctrl-1 = <&state_dpaux1_off>;
682		status = "disabled";
683	};
684
685	/* controlled by BPMP, should not be enabled */
686	pwr_i2c: i2c@31a0000 {
687		compatible = "nvidia,tegra186-i2c";
688		reg = <0x0 0x031a0000 0x0 0x10000>;
689		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
690		#address-cells = <1>;
691		#size-cells = <0>;
692		clocks = <&bpmp TEGRA186_CLK_I2C5>;
693		clock-names = "div-clk";
694		resets = <&bpmp TEGRA186_RESET_I2C5>;
695		reset-names = "i2c";
696		status = "disabled";
697	};
698
699	/* shares pads with dpaux0 */
700	dp_aux_ch0_i2c: i2c@31b0000 {
701		compatible = "nvidia,tegra186-i2c";
702		reg = <0x0 0x031b0000 0x0 0x10000>;
703		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
704		#address-cells = <1>;
705		#size-cells = <0>;
706		clocks = <&bpmp TEGRA186_CLK_I2C6>;
707		clock-names = "div-clk";
708		resets = <&bpmp TEGRA186_RESET_I2C6>;
709		reset-names = "i2c";
710		pinctrl-names = "default", "idle";
711		pinctrl-0 = <&state_dpaux_i2c>;
712		pinctrl-1 = <&state_dpaux_off>;
713		status = "disabled";
714	};
715
716	gen7_i2c: i2c@31c0000 {
717		compatible = "nvidia,tegra186-i2c";
718		reg = <0x0 0x031c0000 0x0 0x10000>;
719		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
720		#address-cells = <1>;
721		#size-cells = <0>;
722		clocks = <&bpmp TEGRA186_CLK_I2C7>;
723		clock-names = "div-clk";
724		resets = <&bpmp TEGRA186_RESET_I2C7>;
725		reset-names = "i2c";
726		status = "disabled";
727	};
728
729	gen9_i2c: i2c@31e0000 {
730		compatible = "nvidia,tegra186-i2c";
731		reg = <0x0 0x031e0000 0x0 0x10000>;
732		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
733		#address-cells = <1>;
734		#size-cells = <0>;
735		clocks = <&bpmp TEGRA186_CLK_I2C9>;
736		clock-names = "div-clk";
737		resets = <&bpmp TEGRA186_RESET_I2C9>;
738		reset-names = "i2c";
739		status = "disabled";
740	};
741
742	pwm1: pwm@3280000 {
743		compatible = "nvidia,tegra186-pwm";
744		reg = <0x0 0x3280000 0x0 0x10000>;
745		clocks = <&bpmp TEGRA186_CLK_PWM1>;
746		clock-names = "pwm";
747		resets = <&bpmp TEGRA186_RESET_PWM1>;
748		reset-names = "pwm";
749		status = "disabled";
750		#pwm-cells = <2>;
751	};
752
753	pwm2: pwm@3290000 {
754		compatible = "nvidia,tegra186-pwm";
755		reg = <0x0 0x3290000 0x0 0x10000>;
756		clocks = <&bpmp TEGRA186_CLK_PWM2>;
757		clock-names = "pwm";
758		resets = <&bpmp TEGRA186_RESET_PWM2>;
759		reset-names = "pwm";
760		status = "disabled";
761		#pwm-cells = <2>;
762	};
763
764	pwm3: pwm@32a0000 {
765		compatible = "nvidia,tegra186-pwm";
766		reg = <0x0 0x32a0000 0x0 0x10000>;
767		clocks = <&bpmp TEGRA186_CLK_PWM3>;
768		clock-names = "pwm";
769		resets = <&bpmp TEGRA186_RESET_PWM3>;
770		reset-names = "pwm";
771		status = "disabled";
772		#pwm-cells = <2>;
773	};
774
775	pwm5: pwm@32c0000 {
776		compatible = "nvidia,tegra186-pwm";
777		reg = <0x0 0x32c0000 0x0 0x10000>;
778		clocks = <&bpmp TEGRA186_CLK_PWM5>;
779		clock-names = "pwm";
780		resets = <&bpmp TEGRA186_RESET_PWM5>;
781		reset-names = "pwm";
782		status = "disabled";
783		#pwm-cells = <2>;
784	};
785
786	pwm6: pwm@32d0000 {
787		compatible = "nvidia,tegra186-pwm";
788		reg = <0x0 0x32d0000 0x0 0x10000>;
789		clocks = <&bpmp TEGRA186_CLK_PWM6>;
790		clock-names = "pwm";
791		resets = <&bpmp TEGRA186_RESET_PWM6>;
792		reset-names = "pwm";
793		status = "disabled";
794		#pwm-cells = <2>;
795	};
796
797	pwm7: pwm@32e0000 {
798		compatible = "nvidia,tegra186-pwm";
799		reg = <0x0 0x32e0000 0x0 0x10000>;
800		clocks = <&bpmp TEGRA186_CLK_PWM7>;
801		clock-names = "pwm";
802		resets = <&bpmp TEGRA186_RESET_PWM7>;
803		reset-names = "pwm";
804		status = "disabled";
805		#pwm-cells = <2>;
806	};
807
808	pwm8: pwm@32f0000 {
809		compatible = "nvidia,tegra186-pwm";
810		reg = <0x0 0x32f0000 0x0 0x10000>;
811		clocks = <&bpmp TEGRA186_CLK_PWM8>;
812		clock-names = "pwm";
813		resets = <&bpmp TEGRA186_RESET_PWM8>;
814		reset-names = "pwm";
815		status = "disabled";
816		#pwm-cells = <2>;
817	};
818
819	sdmmc1: mmc@3400000 {
820		compatible = "nvidia,tegra186-sdhci";
821		reg = <0x0 0x03400000 0x0 0x10000>;
822		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
823		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
824			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
825		clock-names = "sdhci", "tmclk";
826		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
827		reset-names = "sdhci";
828		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
829				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
830		interconnect-names = "dma-mem", "write";
831		iommus = <&smmu TEGRA186_SID_SDMMC1>;
832		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
833		pinctrl-0 = <&sdmmc1_3v3>;
834		pinctrl-1 = <&sdmmc1_1v8>;
835		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
836		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
837		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
838		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
839		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
840		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
841		nvidia,default-tap = <0x5>;
842		nvidia,default-trim = <0xb>;
843		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
844				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
845		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
846		status = "disabled";
847	};
848
849	sdmmc2: mmc@3420000 {
850		compatible = "nvidia,tegra186-sdhci";
851		reg = <0x0 0x03420000 0x0 0x10000>;
852		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
853		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
854			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
855		clock-names = "sdhci", "tmclk";
856		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
857		reset-names = "sdhci";
858		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
859				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
860		interconnect-names = "dma-mem", "write";
861		iommus = <&smmu TEGRA186_SID_SDMMC2>;
862		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
863		pinctrl-0 = <&sdmmc2_3v3>;
864		pinctrl-1 = <&sdmmc2_1v8>;
865		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
866		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
867		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
868		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
869		nvidia,default-tap = <0x5>;
870		nvidia,default-trim = <0xb>;
871		status = "disabled";
872	};
873
874	sdmmc3: mmc@3440000 {
875		compatible = "nvidia,tegra186-sdhci";
876		reg = <0x0 0x03440000 0x0 0x10000>;
877		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
878		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
879			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
880		clock-names = "sdhci", "tmclk";
881		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
882		reset-names = "sdhci";
883		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
884				<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
885		interconnect-names = "dma-mem", "write";
886		iommus = <&smmu TEGRA186_SID_SDMMC3>;
887		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
888		pinctrl-0 = <&sdmmc3_3v3>;
889		pinctrl-1 = <&sdmmc3_1v8>;
890		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
891		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
892		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
893		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
894		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
895		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
896		nvidia,default-tap = <0x5>;
897		nvidia,default-trim = <0xb>;
898		status = "disabled";
899	};
900
901	sdmmc4: mmc@3460000 {
902		compatible = "nvidia,tegra186-sdhci";
903		reg = <0x0 0x03460000 0x0 0x10000>;
904		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
905		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
906			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
907		clock-names = "sdhci", "tmclk";
908		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
909				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
910		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
911		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
912		reset-names = "sdhci";
913		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
914				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
915		interconnect-names = "dma-mem", "write";
916		iommus = <&smmu TEGRA186_SID_SDMMC4>;
917		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
918		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
919		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
920		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
921		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
922		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
923		nvidia,default-tap = <0x9>;
924		nvidia,default-trim = <0x5>;
925		nvidia,dqs-trim = <63>;
926		mmc-hs400-1_8v;
927		supports-cqe;
928		status = "disabled";
929	};
930
931	hda@3510000 {
932		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
933		reg = <0x0 0x03510000 0x0 0x10000>;
934		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
935		clocks = <&bpmp TEGRA186_CLK_HDA>,
936			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
937			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
938		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
939		resets = <&bpmp TEGRA186_RESET_HDA>,
940			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
941			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
942		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
943		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
944		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
945				<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
946		interconnect-names = "dma-mem", "write";
947		iommus = <&smmu TEGRA186_SID_HDA>;
948		status = "disabled";
949	};
950
951	padctl: padctl@3520000 {
952		compatible = "nvidia,tegra186-xusb-padctl";
953		reg = <0x0 0x03520000 0x0 0x1000>,
954		      <0x0 0x03540000 0x0 0x1000>;
955		reg-names = "padctl", "ao";
956		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
957
958		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
959		reset-names = "padctl";
960
961		status = "disabled";
962
963		pads {
964			usb2 {
965				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
966				clock-names = "trk";
967				status = "disabled";
968
969				lanes {
970					usb2-0 {
971						status = "disabled";
972						#phy-cells = <0>;
973					};
974
975					usb2-1 {
976						status = "disabled";
977						#phy-cells = <0>;
978					};
979
980					usb2-2 {
981						status = "disabled";
982						#phy-cells = <0>;
983					};
984				};
985			};
986
987			hsic {
988				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
989				clock-names = "trk";
990				status = "disabled";
991
992				lanes {
993					hsic-0 {
994						status = "disabled";
995						#phy-cells = <0>;
996					};
997				};
998			};
999
1000			usb3 {
1001				status = "disabled";
1002
1003				lanes {
1004					usb3-0 {
1005						status = "disabled";
1006						#phy-cells = <0>;
1007					};
1008
1009					usb3-1 {
1010						status = "disabled";
1011						#phy-cells = <0>;
1012					};
1013
1014					usb3-2 {
1015						status = "disabled";
1016						#phy-cells = <0>;
1017					};
1018				};
1019			};
1020		};
1021
1022		ports {
1023			usb2-0 {
1024				status = "disabled";
1025			};
1026
1027			usb2-1 {
1028				status = "disabled";
1029			};
1030
1031			usb2-2 {
1032				status = "disabled";
1033			};
1034
1035			hsic-0 {
1036				status = "disabled";
1037			};
1038
1039			usb3-0 {
1040				status = "disabled";
1041			};
1042
1043			usb3-1 {
1044				status = "disabled";
1045			};
1046
1047			usb3-2 {
1048				status = "disabled";
1049			};
1050		};
1051	};
1052
1053	usb@3530000 {
1054		compatible = "nvidia,tegra186-xusb";
1055		reg = <0x0 0x03530000 0x0 0x8000>,
1056		      <0x0 0x03538000 0x0 0x1000>;
1057		reg-names = "hcd", "fpci";
1058		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1059			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1060		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1061			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1062			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1063			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1064			 <&bpmp TEGRA186_CLK_CLK_M>,
1065			 <&bpmp TEGRA186_CLK_XUSB_FS>,
1066			 <&bpmp TEGRA186_CLK_PLLU>,
1067			 <&bpmp TEGRA186_CLK_CLK_M>,
1068			 <&bpmp TEGRA186_CLK_PLLE>;
1069		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1070			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1071			      "pll_u_480m", "clk_m", "pll_e";
1072		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1073				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1074		power-domain-names = "xusb_host", "xusb_ss";
1075		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1076				<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1077		interconnect-names = "dma-mem", "write";
1078		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1079		#address-cells = <1>;
1080		#size-cells = <0>;
1081		status = "disabled";
1082
1083		nvidia,xusb-padctl = <&padctl>;
1084	};
1085
1086	usb@3550000 {
1087		compatible = "nvidia,tegra186-xudc";
1088		reg = <0x0 0x03550000 0x0 0x8000>,
1089		      <0x0 0x03558000 0x0 0x1000>;
1090		reg-names = "base", "fpci";
1091		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1092		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1093			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1094			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1095			 <&bpmp TEGRA186_CLK_XUSB_FS>;
1096		clock-names = "dev", "ss", "ss_src", "fs_src";
1097		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
1098				<&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
1099		interconnect-names = "dma-mem", "write";
1100		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1101		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1102				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1103		power-domain-names = "dev", "ss";
1104		nvidia,xusb-padctl = <&padctl>;
1105		status = "disabled";
1106	};
1107
1108	fuse@3820000 {
1109		compatible = "nvidia,tegra186-efuse";
1110		reg = <0x0 0x03820000 0x0 0x10000>;
1111		clocks = <&bpmp TEGRA186_CLK_FUSE>;
1112		clock-names = "fuse";
1113	};
1114
1115	gic: interrupt-controller@3881000 {
1116		compatible = "arm,gic-400";
1117		#interrupt-cells = <3>;
1118		interrupt-controller;
1119		reg = <0x0 0x03881000 0x0 0x1000>,
1120		      <0x0 0x03882000 0x0 0x2000>,
1121		      <0x0 0x03884000 0x0 0x2000>,
1122		      <0x0 0x03886000 0x0 0x2000>;
1123		interrupts = <GIC_PPI 9
1124			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1125		interrupt-parent = <&gic>;
1126	};
1127
1128	cec@3960000 {
1129		compatible = "nvidia,tegra186-cec";
1130		reg = <0x0 0x03960000 0x0 0x10000>;
1131		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1132		clocks = <&bpmp TEGRA186_CLK_CEC>;
1133		clock-names = "cec";
1134		status = "disabled";
1135	};
1136
1137	hsp_top0: hsp@3c00000 {
1138		compatible = "nvidia,tegra186-hsp";
1139		reg = <0x0 0x03c00000 0x0 0xa0000>;
1140		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1141		interrupt-names = "doorbell";
1142		#mbox-cells = <2>;
1143		status = "disabled";
1144	};
1145
1146	gen2_i2c: i2c@c240000 {
1147		compatible = "nvidia,tegra186-i2c";
1148		reg = <0x0 0x0c240000 0x0 0x10000>;
1149		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1150		#address-cells = <1>;
1151		#size-cells = <0>;
1152		clocks = <&bpmp TEGRA186_CLK_I2C2>;
1153		clock-names = "div-clk";
1154		resets = <&bpmp TEGRA186_RESET_I2C2>;
1155		reset-names = "i2c";
1156		status = "disabled";
1157	};
1158
1159	gen8_i2c: i2c@c250000 {
1160		compatible = "nvidia,tegra186-i2c";
1161		reg = <0x0 0x0c250000 0x0 0x10000>;
1162		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1163		#address-cells = <1>;
1164		#size-cells = <0>;
1165		clocks = <&bpmp TEGRA186_CLK_I2C8>;
1166		clock-names = "div-clk";
1167		resets = <&bpmp TEGRA186_RESET_I2C8>;
1168		reset-names = "i2c";
1169		status = "disabled";
1170	};
1171
1172	uartc: serial@c280000 {
1173		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1174		reg = <0x0 0x0c280000 0x0 0x40>;
1175		reg-shift = <2>;
1176		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1177		clocks = <&bpmp TEGRA186_CLK_UARTC>;
1178		clock-names = "serial";
1179		resets = <&bpmp TEGRA186_RESET_UARTC>;
1180		reset-names = "serial";
1181		status = "disabled";
1182	};
1183
1184	uartg: serial@c290000 {
1185		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1186		reg = <0x0 0x0c290000 0x0 0x40>;
1187		reg-shift = <2>;
1188		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1189		clocks = <&bpmp TEGRA186_CLK_UARTG>;
1190		clock-names = "serial";
1191		resets = <&bpmp TEGRA186_RESET_UARTG>;
1192		reset-names = "serial";
1193		status = "disabled";
1194	};
1195
1196	rtc: rtc@c2a0000 {
1197		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1198		reg = <0 0x0c2a0000 0 0x10000>;
1199		interrupt-parent = <&pmc>;
1200		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1201		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1202		clock-names = "rtc";
1203		status = "disabled";
1204	};
1205
1206	gpio_aon: gpio@c2f0000 {
1207		compatible = "nvidia,tegra186-gpio-aon";
1208		reg-names = "security", "gpio";
1209		reg = <0x0 0xc2f0000 0x0 0x1000>,
1210		      <0x0 0xc2f1000 0x0 0x1000>;
1211		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1212		gpio-controller;
1213		#gpio-cells = <2>;
1214		interrupt-controller;
1215		#interrupt-cells = <2>;
1216	};
1217
1218	pwm4: pwm@c340000 {
1219		compatible = "nvidia,tegra186-pwm";
1220		reg = <0x0 0xc340000 0x0 0x10000>;
1221		clocks = <&bpmp TEGRA186_CLK_PWM4>;
1222		clock-names = "pwm";
1223		resets = <&bpmp TEGRA186_RESET_PWM4>;
1224		reset-names = "pwm";
1225		status = "disabled";
1226		#pwm-cells = <2>;
1227	};
1228
1229	pmc: pmc@c360000 {
1230		compatible = "nvidia,tegra186-pmc";
1231		reg = <0 0x0c360000 0 0x10000>,
1232		      <0 0x0c370000 0 0x10000>,
1233		      <0 0x0c380000 0 0x10000>,
1234		      <0 0x0c390000 0 0x10000>;
1235		reg-names = "pmc", "wake", "aotag", "scratch";
1236
1237		#interrupt-cells = <2>;
1238		interrupt-controller;
1239
1240		sdmmc1_3v3: sdmmc1-3v3 {
1241			pins = "sdmmc1-hv";
1242			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1243		};
1244
1245		sdmmc1_1v8: sdmmc1-1v8 {
1246			pins = "sdmmc1-hv";
1247			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1248		};
1249
1250		sdmmc2_3v3: sdmmc2-3v3 {
1251			pins = "sdmmc2-hv";
1252			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1253		};
1254
1255		sdmmc2_1v8: sdmmc2-1v8 {
1256			pins = "sdmmc2-hv";
1257			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1258		};
1259
1260		sdmmc3_3v3: sdmmc3-3v3 {
1261			pins = "sdmmc3-hv";
1262			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1263		};
1264
1265		sdmmc3_1v8: sdmmc3-1v8 {
1266			pins = "sdmmc3-hv";
1267			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1268		};
1269	};
1270
1271	ccplex@e000000 {
1272		compatible = "nvidia,tegra186-ccplex-cluster";
1273		reg = <0x0 0x0e000000 0x0 0x400000>;
1274
1275		nvidia,bpmp = <&bpmp>;
1276	};
1277
1278	pcie@10003000 {
1279		compatible = "nvidia,tegra186-pcie";
1280		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1281		device_type = "pci";
1282		reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1283		      <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1284		      <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1285		reg-names = "pads", "afi", "cs";
1286
1287		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1288			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1289		interrupt-names = "intr", "msi";
1290
1291		#interrupt-cells = <1>;
1292		interrupt-map-mask = <0 0 0 0>;
1293		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1294
1295		bus-range = <0x00 0xff>;
1296		#address-cells = <3>;
1297		#size-cells = <2>;
1298
1299		ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1300			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1301			 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1302			 <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1303			 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1304			 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1305
1306		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1307			 <&bpmp TEGRA186_CLK_AFI>,
1308			 <&bpmp TEGRA186_CLK_PLLE>;
1309		clock-names = "pex", "afi", "pll_e";
1310
1311		resets = <&bpmp TEGRA186_RESET_PCIE>,
1312			 <&bpmp TEGRA186_RESET_AFI>,
1313			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1314		reset-names = "pex", "afi", "pcie_x";
1315
1316		interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1317				<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1318		interconnect-names = "dma-mem", "write";
1319
1320		iommus = <&smmu TEGRA186_SID_AFI>;
1321		iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1322		iommu-map-mask = <0x0>;
1323
1324		status = "disabled";
1325
1326		pci@1,0 {
1327			device_type = "pci";
1328			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1329			reg = <0x000800 0 0 0 0>;
1330			status = "disabled";
1331
1332			#address-cells = <3>;
1333			#size-cells = <2>;
1334			ranges;
1335
1336			nvidia,num-lanes = <2>;
1337		};
1338
1339		pci@2,0 {
1340			device_type = "pci";
1341			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1342			reg = <0x001000 0 0 0 0>;
1343			status = "disabled";
1344
1345			#address-cells = <3>;
1346			#size-cells = <2>;
1347			ranges;
1348
1349			nvidia,num-lanes = <1>;
1350		};
1351
1352		pci@3,0 {
1353			device_type = "pci";
1354			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1355			reg = <0x001800 0 0 0 0>;
1356			status = "disabled";
1357
1358			#address-cells = <3>;
1359			#size-cells = <2>;
1360			ranges;
1361
1362			nvidia,num-lanes = <1>;
1363		};
1364	};
1365
1366	smmu: iommu@12000000 {
1367		compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1368		reg = <0 0x12000000 0 0x800000>;
1369		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1370			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1371			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1372			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1373			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1374			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1375			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1376			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1377			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1378			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1379			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1380			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1381			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1382			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1383			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1384			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1385			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1386			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1387			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1388			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1389			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1390			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1391			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1392			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1393			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1394			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1395			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1396			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1397			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1398			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1399			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1400			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1401			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1402			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1403			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1404			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1405			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1406			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1407			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1408			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1409			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1410			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1411			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1412			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1413			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1414			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1415			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1416			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1417			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1418			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1419			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1420			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1421			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1422			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1423			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1424			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1425			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1426			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1427			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1428			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1429			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1430			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1431			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1432			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1433			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1434		stream-match-mask = <0x7f80>;
1435		#global-interrupts = <1>;
1436		#iommu-cells = <1>;
1437
1438		nvidia,memory-controller = <&mc>;
1439	};
1440
1441	host1x@13e00000 {
1442		compatible = "nvidia,tegra186-host1x";
1443		reg = <0x0 0x13e00000 0x0 0x10000>,
1444		      <0x0 0x13e10000 0x0 0x10000>;
1445		reg-names = "hypervisor", "vm";
1446		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1447		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1448		interrupt-names = "syncpt", "host1x";
1449		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1450		clock-names = "host1x";
1451		resets = <&bpmp TEGRA186_RESET_HOST1X>;
1452		reset-names = "host1x";
1453
1454		#address-cells = <1>;
1455		#size-cells = <1>;
1456
1457		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1458
1459		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1460		interconnect-names = "dma-mem";
1461
1462		iommus = <&smmu TEGRA186_SID_HOST1X>;
1463
1464		dpaux1: dpaux@15040000 {
1465			compatible = "nvidia,tegra186-dpaux";
1466			reg = <0x15040000 0x10000>;
1467			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1468			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1469				 <&bpmp TEGRA186_CLK_PLLDP>;
1470			clock-names = "dpaux", "parent";
1471			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1472			reset-names = "dpaux";
1473			status = "disabled";
1474
1475			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1476
1477			state_dpaux1_aux: pinmux-aux {
1478				groups = "dpaux-io";
1479				function = "aux";
1480			};
1481
1482			state_dpaux1_i2c: pinmux-i2c {
1483				groups = "dpaux-io";
1484				function = "i2c";
1485			};
1486
1487			state_dpaux1_off: pinmux-off {
1488				groups = "dpaux-io";
1489				function = "off";
1490			};
1491
1492			i2c-bus {
1493				#address-cells = <1>;
1494				#size-cells = <0>;
1495			};
1496		};
1497
1498		display-hub@15200000 {
1499			compatible = "nvidia,tegra186-display";
1500			reg = <0x15200000 0x00040000>;
1501			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1502				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1503				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1504				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1505				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1506				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1507				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1508			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1509				      "wgrp3", "wgrp4", "wgrp5";
1510			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1511				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1512				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1513			clock-names = "disp", "dsc", "hub";
1514			status = "disabled";
1515
1516			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1517
1518			#address-cells = <1>;
1519			#size-cells = <1>;
1520
1521			ranges = <0x15200000 0x15200000 0x40000>;
1522
1523			display@15200000 {
1524				compatible = "nvidia,tegra186-dc";
1525				reg = <0x15200000 0x10000>;
1526				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1527				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1528				clock-names = "dc";
1529				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1530				reset-names = "dc";
1531
1532				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1533				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1534						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1535				interconnect-names = "dma-mem", "read-1";
1536				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1537
1538				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1539				nvidia,head = <0>;
1540			};
1541
1542			display@15210000 {
1543				compatible = "nvidia,tegra186-dc";
1544				reg = <0x15210000 0x10000>;
1545				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1546				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1547				clock-names = "dc";
1548				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1549				reset-names = "dc";
1550
1551				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1552				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1553						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1554				interconnect-names = "dma-mem", "read-1";
1555				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1556
1557				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1558				nvidia,head = <1>;
1559			};
1560
1561			display@15220000 {
1562				compatible = "nvidia,tegra186-dc";
1563				reg = <0x15220000 0x10000>;
1564				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1565				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1566				clock-names = "dc";
1567				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1568				reset-names = "dc";
1569
1570				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1571				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1572						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1573				interconnect-names = "dma-mem", "read-1";
1574				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1575
1576				nvidia,outputs = <&sor0 &sor1>;
1577				nvidia,head = <2>;
1578			};
1579		};
1580
1581		dsia: dsi@15300000 {
1582			compatible = "nvidia,tegra186-dsi";
1583			reg = <0x15300000 0x10000>;
1584			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1585			clocks = <&bpmp TEGRA186_CLK_DSI>,
1586				 <&bpmp TEGRA186_CLK_DSIA_LP>,
1587				 <&bpmp TEGRA186_CLK_PLLD>;
1588			clock-names = "dsi", "lp", "parent";
1589			resets = <&bpmp TEGRA186_RESET_DSI>;
1590			reset-names = "dsi";
1591			status = "disabled";
1592
1593			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1594		};
1595
1596		vic@15340000 {
1597			compatible = "nvidia,tegra186-vic";
1598			reg = <0x15340000 0x40000>;
1599			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1600			clocks = <&bpmp TEGRA186_CLK_VIC>;
1601			clock-names = "vic";
1602			resets = <&bpmp TEGRA186_RESET_VIC>;
1603			reset-names = "vic";
1604
1605			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1606			interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1607					<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1608			interconnect-names = "dma-mem", "write";
1609			iommus = <&smmu TEGRA186_SID_VIC>;
1610		};
1611
1612		nvjpg@15380000 {
1613			compatible = "nvidia,tegra186-nvjpg";
1614			reg = <0x15380000 0x40000>;
1615			clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1616			clock-names = "nvjpg";
1617			resets = <&bpmp TEGRA186_RESET_NVJPG>;
1618			reset-names = "nvjpg";
1619
1620			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1621			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
1622					<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
1623			interconnect-names = "dma-mem", "write";
1624			iommus = <&smmu TEGRA186_SID_NVJPG>;
1625		};
1626
1627		dsib: dsi@15400000 {
1628			compatible = "nvidia,tegra186-dsi";
1629			reg = <0x15400000 0x10000>;
1630			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1631			clocks = <&bpmp TEGRA186_CLK_DSIB>,
1632				 <&bpmp TEGRA186_CLK_DSIB_LP>,
1633				 <&bpmp TEGRA186_CLK_PLLD>;
1634			clock-names = "dsi", "lp", "parent";
1635			resets = <&bpmp TEGRA186_RESET_DSIB>;
1636			reset-names = "dsi";
1637			status = "disabled";
1638
1639			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1640		};
1641
1642		nvdec@15480000 {
1643			compatible = "nvidia,tegra186-nvdec";
1644			reg = <0x15480000 0x40000>;
1645			clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1646			clock-names = "nvdec";
1647			resets = <&bpmp TEGRA186_RESET_NVDEC>;
1648			reset-names = "nvdec";
1649
1650			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1651			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
1652					<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
1653					<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
1654			interconnect-names = "dma-mem", "read-1", "write";
1655			iommus = <&smmu TEGRA186_SID_NVDEC>;
1656		};
1657
1658		nvenc@154c0000 {
1659			compatible = "nvidia,tegra186-nvenc";
1660			reg = <0x154c0000 0x40000>;
1661			clocks = <&bpmp TEGRA186_CLK_NVENC>;
1662			clock-names = "nvenc";
1663			resets = <&bpmp TEGRA186_RESET_NVENC>;
1664			reset-names = "nvenc";
1665
1666			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1667			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
1668					<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
1669			interconnect-names = "dma-mem", "write";
1670			iommus = <&smmu TEGRA186_SID_NVENC>;
1671		};
1672
1673		sor0: sor@15540000 {
1674			compatible = "nvidia,tegra186-sor";
1675			reg = <0x15540000 0x10000>;
1676			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1677			clocks = <&bpmp TEGRA186_CLK_SOR0>,
1678				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1679				 <&bpmp TEGRA186_CLK_PLLD2>,
1680				 <&bpmp TEGRA186_CLK_PLLDP>,
1681				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1682				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1683			clock-names = "sor", "out", "parent", "dp", "safe",
1684				      "pad";
1685			resets = <&bpmp TEGRA186_RESET_SOR0>;
1686			reset-names = "sor";
1687			pinctrl-0 = <&state_dpaux_aux>;
1688			pinctrl-1 = <&state_dpaux_i2c>;
1689			pinctrl-2 = <&state_dpaux_off>;
1690			pinctrl-names = "aux", "i2c", "off";
1691			status = "disabled";
1692
1693			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1694			nvidia,interface = <0>;
1695		};
1696
1697		sor1: sor@15580000 {
1698			compatible = "nvidia,tegra186-sor";
1699			reg = <0x15580000 0x10000>;
1700			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1701			clocks = <&bpmp TEGRA186_CLK_SOR1>,
1702				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1703				 <&bpmp TEGRA186_CLK_PLLD3>,
1704				 <&bpmp TEGRA186_CLK_PLLDP>,
1705				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1706				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1707			clock-names = "sor", "out", "parent", "dp", "safe",
1708				      "pad";
1709			resets = <&bpmp TEGRA186_RESET_SOR1>;
1710			reset-names = "sor";
1711			pinctrl-0 = <&state_dpaux1_aux>;
1712			pinctrl-1 = <&state_dpaux1_i2c>;
1713			pinctrl-2 = <&state_dpaux1_off>;
1714			pinctrl-names = "aux", "i2c", "off";
1715			status = "disabled";
1716
1717			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1718			nvidia,interface = <1>;
1719		};
1720
1721		dpaux: dpaux@155c0000 {
1722			compatible = "nvidia,tegra186-dpaux";
1723			reg = <0x155c0000 0x10000>;
1724			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1725			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1726				 <&bpmp TEGRA186_CLK_PLLDP>;
1727			clock-names = "dpaux", "parent";
1728			resets = <&bpmp TEGRA186_RESET_DPAUX>;
1729			reset-names = "dpaux";
1730			status = "disabled";
1731
1732			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1733
1734			state_dpaux_aux: pinmux-aux {
1735				groups = "dpaux-io";
1736				function = "aux";
1737			};
1738
1739			state_dpaux_i2c: pinmux-i2c {
1740				groups = "dpaux-io";
1741				function = "i2c";
1742			};
1743
1744			state_dpaux_off: pinmux-off {
1745				groups = "dpaux-io";
1746				function = "off";
1747			};
1748
1749			i2c-bus {
1750				#address-cells = <1>;
1751				#size-cells = <0>;
1752			};
1753		};
1754
1755		padctl@15880000 {
1756			compatible = "nvidia,tegra186-dsi-padctl";
1757			reg = <0x15880000 0x10000>;
1758			resets = <&bpmp TEGRA186_RESET_DSI>;
1759			reset-names = "dsi";
1760			status = "disabled";
1761		};
1762
1763		dsic: dsi@15900000 {
1764			compatible = "nvidia,tegra186-dsi";
1765			reg = <0x15900000 0x10000>;
1766			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1767			clocks = <&bpmp TEGRA186_CLK_DSIC>,
1768				 <&bpmp TEGRA186_CLK_DSIC_LP>,
1769				 <&bpmp TEGRA186_CLK_PLLD>;
1770			clock-names = "dsi", "lp", "parent";
1771			resets = <&bpmp TEGRA186_RESET_DSIC>;
1772			reset-names = "dsi";
1773			status = "disabled";
1774
1775			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1776		};
1777
1778		dsid: dsi@15940000 {
1779			compatible = "nvidia,tegra186-dsi";
1780			reg = <0x15940000 0x10000>;
1781			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1782			clocks = <&bpmp TEGRA186_CLK_DSID>,
1783				 <&bpmp TEGRA186_CLK_DSID_LP>,
1784				 <&bpmp TEGRA186_CLK_PLLD>;
1785			clock-names = "dsi", "lp", "parent";
1786			resets = <&bpmp TEGRA186_RESET_DSID>;
1787			reset-names = "dsi";
1788			status = "disabled";
1789
1790			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1791		};
1792	};
1793
1794	gpu@17000000 {
1795		compatible = "nvidia,gp10b";
1796		reg = <0x0 0x17000000 0x0 0x1000000>,
1797		      <0x0 0x18000000 0x0 0x1000000>;
1798		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1799			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1800		interrupt-names = "stall", "nonstall";
1801
1802		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1803			 <&bpmp TEGRA186_CLK_GPU>;
1804		clock-names = "gpu", "pwr";
1805		resets = <&bpmp TEGRA186_RESET_GPU>;
1806		reset-names = "gpu";
1807		status = "disabled";
1808
1809		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1810		interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1811				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1812				<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1813				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1814		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1815	};
1816
1817	sram@30000000 {
1818		compatible = "nvidia,tegra186-sysram", "mmio-sram";
1819		reg = <0x0 0x30000000 0x0 0x50000>;
1820		#address-cells = <1>;
1821		#size-cells = <1>;
1822		ranges = <0x0 0x0 0x30000000 0x50000>;
1823		no-memory-wc;
1824
1825		cpu_bpmp_tx: sram@4e000 {
1826			reg = <0x4e000 0x1000>;
1827			label = "cpu-bpmp-tx";
1828			pool;
1829		};
1830
1831		cpu_bpmp_rx: sram@4f000 {
1832			reg = <0x4f000 0x1000>;
1833			label = "cpu-bpmp-rx";
1834			pool;
1835		};
1836	};
1837
1838	sata@3507000 {
1839		compatible = "nvidia,tegra186-ahci";
1840		reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1841		      <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1842		      <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1843		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1844
1845		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1846		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
1847				<&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
1848		interconnect-names = "dma-mem", "write";
1849		iommus = <&smmu TEGRA186_SID_SATA>;
1850
1851		clocks = <&bpmp TEGRA186_CLK_SATA>,
1852			 <&bpmp TEGRA186_CLK_SATA_OOB>;
1853		clock-names = "sata", "sata-oob";
1854		assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1855				  <&bpmp TEGRA186_CLK_SATA_OOB>;
1856		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1857					 <&bpmp TEGRA186_CLK_PLLP>;
1858		assigned-clock-rates = <102000000>,
1859				       <204000000>;
1860		resets = <&bpmp TEGRA186_RESET_SATA>,
1861			<&bpmp TEGRA186_RESET_SATACOLD>;
1862		reset-names = "sata", "sata-cold";
1863		status = "disabled";
1864	};
1865
1866	bpmp: bpmp {
1867		compatible = "nvidia,tegra186-bpmp";
1868		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1869				<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1870				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1871				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1872		interconnect-names = "read", "write", "dma-mem", "dma-write";
1873		iommus = <&smmu TEGRA186_SID_BPMP>;
1874		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1875				    TEGRA_HSP_DB_MASTER_BPMP>;
1876		shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
1877		#clock-cells = <1>;
1878		#reset-cells = <1>;
1879		#power-domain-cells = <1>;
1880
1881		bpmp_i2c: i2c {
1882			compatible = "nvidia,tegra186-bpmp-i2c";
1883			nvidia,bpmp-bus-id = <5>;
1884			#address-cells = <1>;
1885			#size-cells = <0>;
1886			status = "disabled";
1887		};
1888
1889		bpmp_thermal: thermal {
1890			compatible = "nvidia,tegra186-bpmp-thermal";
1891			#thermal-sensor-cells = <1>;
1892		};
1893	};
1894
1895	cpus {
1896		#address-cells = <1>;
1897		#size-cells = <0>;
1898
1899		denver_0: cpu@0 {
1900			compatible = "nvidia,tegra186-denver";
1901			device_type = "cpu";
1902			i-cache-size = <0x20000>;
1903			i-cache-line-size = <64>;
1904			i-cache-sets = <512>;
1905			d-cache-size = <0x10000>;
1906			d-cache-line-size = <64>;
1907			d-cache-sets = <256>;
1908			next-level-cache = <&L2_DENVER>;
1909			reg = <0x000>;
1910		};
1911
1912		denver_1: cpu@1 {
1913			compatible = "nvidia,tegra186-denver";
1914			device_type = "cpu";
1915			i-cache-size = <0x20000>;
1916			i-cache-line-size = <64>;
1917			i-cache-sets = <512>;
1918			d-cache-size = <0x10000>;
1919			d-cache-line-size = <64>;
1920			d-cache-sets = <256>;
1921			next-level-cache = <&L2_DENVER>;
1922			reg = <0x001>;
1923		};
1924
1925		ca57_0: cpu@2 {
1926			compatible = "arm,cortex-a57";
1927			device_type = "cpu";
1928			i-cache-size = <0xC000>;
1929			i-cache-line-size = <64>;
1930			i-cache-sets = <256>;
1931			d-cache-size = <0x8000>;
1932			d-cache-line-size = <64>;
1933			d-cache-sets = <256>;
1934			next-level-cache = <&L2_A57>;
1935			reg = <0x100>;
1936		};
1937
1938		ca57_1: cpu@3 {
1939			compatible = "arm,cortex-a57";
1940			device_type = "cpu";
1941			i-cache-size = <0xC000>;
1942			i-cache-line-size = <64>;
1943			i-cache-sets = <256>;
1944			d-cache-size = <0x8000>;
1945			d-cache-line-size = <64>;
1946			d-cache-sets = <256>;
1947			next-level-cache = <&L2_A57>;
1948			reg = <0x101>;
1949		};
1950
1951		ca57_2: cpu@4 {
1952			compatible = "arm,cortex-a57";
1953			device_type = "cpu";
1954			i-cache-size = <0xC000>;
1955			i-cache-line-size = <64>;
1956			i-cache-sets = <256>;
1957			d-cache-size = <0x8000>;
1958			d-cache-line-size = <64>;
1959			d-cache-sets = <256>;
1960			next-level-cache = <&L2_A57>;
1961			reg = <0x102>;
1962		};
1963
1964		ca57_3: cpu@5 {
1965			compatible = "arm,cortex-a57";
1966			device_type = "cpu";
1967			i-cache-size = <0xC000>;
1968			i-cache-line-size = <64>;
1969			i-cache-sets = <256>;
1970			d-cache-size = <0x8000>;
1971			d-cache-line-size = <64>;
1972			d-cache-sets = <256>;
1973			next-level-cache = <&L2_A57>;
1974			reg = <0x103>;
1975		};
1976
1977		L2_DENVER: l2-cache0 {
1978			compatible = "cache";
1979			cache-unified;
1980			cache-level = <2>;
1981			cache-size = <0x200000>;
1982			cache-line-size = <64>;
1983			cache-sets = <2048>;
1984		};
1985
1986		L2_A57: l2-cache1 {
1987			compatible = "cache";
1988			cache-unified;
1989			cache-level = <2>;
1990			cache-size = <0x200000>;
1991			cache-line-size = <64>;
1992			cache-sets = <2048>;
1993		};
1994	};
1995
1996	pmu_denver {
1997		compatible = "nvidia,denver-pmu";
1998		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1999			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2000		interrupt-affinity = <&denver_0 &denver_1>;
2001	};
2002
2003	pmu_a57 {
2004		compatible = "arm,cortex-a57-pmu";
2005		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
2006			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
2007			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
2008			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
2009		interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2010	};
2011
2012	sound {
2013		status = "disabled";
2014
2015		clocks = <&bpmp TEGRA186_CLK_PLLA>,
2016			 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2017		clock-names = "pll_a", "plla_out0";
2018		assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2019				  <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2020				  <&bpmp TEGRA186_CLK_AUD_MCLK>;
2021		assigned-clock-parents = <0>,
2022					 <&bpmp TEGRA186_CLK_PLLA>,
2023					 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2024		/*
2025		 * PLLA supports dynamic ramp. Below initial rate is chosen
2026		 * for this to work and oscillate between base rates required
2027		 * for 8x and 11.025x sample rate streams.
2028		 */
2029		assigned-clock-rates = <258000000>;
2030
2031		iommus = <&smmu TEGRA186_SID_APE>;
2032	};
2033
2034	thermal-zones {
2035		/* Cortex-A57 cluster */
2036		cpu-thermal {
2037			polling-delay = <0>;
2038			polling-delay-passive = <1000>;
2039
2040			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2041
2042			trips {
2043				critical {
2044					temperature = <101000>;
2045					hysteresis = <0>;
2046					type = "critical";
2047				};
2048			};
2049
2050			cooling-maps {
2051			};
2052		};
2053
2054		/* Denver cluster */
2055		aux-thermal {
2056			polling-delay = <0>;
2057			polling-delay-passive = <1000>;
2058
2059			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2060
2061			trips {
2062				critical {
2063					temperature = <101000>;
2064					hysteresis = <0>;
2065					type = "critical";
2066				};
2067			};
2068
2069			cooling-maps {
2070			};
2071		};
2072
2073		gpu-thermal {
2074			polling-delay = <0>;
2075			polling-delay-passive = <1000>;
2076
2077			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2078
2079			trips {
2080				critical {
2081					temperature = <101000>;
2082					hysteresis = <0>;
2083					type = "critical";
2084				};
2085			};
2086
2087			cooling-maps {
2088			};
2089		};
2090
2091		pll-thermal {
2092			polling-delay = <0>;
2093			polling-delay-passive = <1000>;
2094
2095			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2096
2097			trips {
2098				critical {
2099					temperature = <101000>;
2100					hysteresis = <0>;
2101					type = "critical";
2102				};
2103			};
2104
2105			cooling-maps {
2106			};
2107		};
2108
2109		ao-thermal {
2110			polling-delay = <0>;
2111			polling-delay-passive = <1000>;
2112
2113			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2114
2115			trips {
2116				critical {
2117					temperature = <101000>;
2118					hysteresis = <0>;
2119					type = "critical";
2120				};
2121			};
2122
2123			cooling-maps {
2124			};
2125		};
2126	};
2127
2128	timer {
2129		compatible = "arm,armv8-timer";
2130		interrupts = <GIC_PPI 13
2131				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2132			     <GIC_PPI 14
2133				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2134			     <GIC_PPI 11
2135				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2136			     <GIC_PPI 10
2137				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2138		interrupt-parent = <&gic>;
2139		always-on;
2140	};
2141};
2142