1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9
10audio_subsys: bus@59000000 {
11	compatible = "simple-bus";
12	#address-cells = <1>;
13	#size-cells = <1>;
14	ranges = <0x59000000 0x0 0x59000000 0x1000000>;
15
16	audio_ipg_clk: clock-audio-ipg {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		clock-frequency = <120000000>;
20		clock-output-names = "audio_ipg_clk";
21	};
22
23	dsp_lpcg: clock-controller@59580000 {
24		compatible = "fsl,imx8qxp-lpcg";
25		reg = <0x59580000 0x10000>;
26		#clock-cells = <1>;
27		clocks = <&audio_ipg_clk>,
28			 <&audio_ipg_clk>,
29			 <&audio_ipg_clk>;
30		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
31				<IMX_LPCG_CLK_7>;
32		clock-output-names = "dsp_lpcg_adb_clk",
33				     "dsp_lpcg_ipg_clk",
34				     "dsp_lpcg_core_clk";
35		power-domains = <&pd IMX_SC_R_DSP>;
36	};
37
38	dsp_ram_lpcg: clock-controller@59590000 {
39		compatible = "fsl,imx8qxp-lpcg";
40		reg = <0x59590000 0x10000>;
41		#clock-cells = <1>;
42		clocks = <&audio_ipg_clk>;
43		clock-indices = <IMX_LPCG_CLK_4>;
44		clock-output-names = "dsp_ram_lpcg_ipg_clk";
45		power-domains = <&pd IMX_SC_R_DSP_RAM>;
46	};
47
48	dsp: dsp@596e8000 {
49		compatible = "fsl,imx8qxp-dsp";
50		reg = <0x596e8000 0x88000>;
51		clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
52			 <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
53			 <&dsp_lpcg IMX_LPCG_CLK_7>;
54		clock-names = "ipg", "ocram", "core";
55		power-domains = <&pd IMX_SC_R_MU_13A>,
56			<&pd IMX_SC_R_MU_13B>,
57			<&pd IMX_SC_R_DSP>,
58			<&pd IMX_SC_R_DSP_RAM>;
59		mbox-names = "txdb0", "txdb1",
60			"rxdb0", "rxdb1";
61		mboxes = <&lsio_mu13 2 0>,
62			<&lsio_mu13 2 1>,
63			<&lsio_mu13 3 0>,
64			<&lsio_mu13 3 1>;
65		memory-region = <&dsp_reserved>;
66		status = "disabled";
67	};
68};
69