1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (c) 2006 Simtec Electronics
4 // Ben Dooks <ben@simtec.co.uk>
5 //
6 // S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
7
8 #include <linux/init.h>
9 #include <linux/suspend.h>
10 #include <linux/errno.h>
11 #include <linux/time.h>
12 #include <linux/device.h>
13 #include <linux/syscore_ops.h>
14 #include <linux/gpio.h>
15 #include <linux/io.h>
16
17 #include <asm/mach-types.h>
18
19 #include "regs-gpio.h"
20 #include "gpio-samsung.h"
21
22 #include "gpio-cfg.h"
23 #include "cpu.h"
24 #include "pm.h"
25
26 #include "h1940.h"
27
s3c2410_pm_prepare(void)28 static void s3c2410_pm_prepare(void)
29 {
30 /* ensure at least GSTATUS3 has the resume address */
31
32 __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
33
34 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
35 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
36
37 if (machine_is_h1940()) {
38 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
39 unsigned long ptr;
40 unsigned long calc = 0;
41
42 /* generate check for the bootloader to check on resume */
43
44 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
45 calc += __raw_readl(base+ptr);
46
47 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
48 }
49
50 /* RX3715 and RX1950 use similar to H1940 code and the
51 * same offsets for resume and checksum pointers */
52
53 if (machine_is_rx3715() || machine_is_rx1950()) {
54 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
55 unsigned long ptr;
56 unsigned long calc = 0;
57
58 /* generate check for the bootloader to check on resume */
59
60 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
61 calc += __raw_readl(base+ptr);
62
63 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
64 }
65
66 if (machine_is_aml_m5900()) {
67 gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
68 gpio_free(S3C2410_GPF(2));
69 }
70
71 if (machine_is_rx1950()) {
72 /* According to S3C2442 user's manual, page 7-17,
73 * when the system is operating in NAND boot mode,
74 * the hardware pin configuration - EINT[23:21] –
75 * must be set as input for starting up after
76 * wakeup from sleep mode
77 */
78 s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
79 s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
80 s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
81 }
82 }
83
s3c2410_pm_resume(void)84 static void s3c2410_pm_resume(void)
85 {
86 unsigned long tmp;
87
88 /* unset the return-from-sleep flag, to ensure reset */
89
90 tmp = __raw_readl(S3C2410_GSTATUS2);
91 tmp &= S3C2410_GSTATUS2_OFFRESET;
92 __raw_writel(tmp, S3C2410_GSTATUS2);
93
94 if (machine_is_aml_m5900()) {
95 gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
96 gpio_free(S3C2410_GPF(2));
97 }
98 }
99
100 struct syscore_ops s3c2410_pm_syscore_ops = {
101 .resume = s3c2410_pm_resume,
102 };
103
s3c2410_pm_add(struct device * dev,struct subsys_interface * sif)104 static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
105 {
106 pm_cpu_prep = s3c2410_pm_prepare;
107 pm_cpu_sleep = s3c2410_cpu_suspend;
108
109 return 0;
110 }
111
112 #if defined(CONFIG_CPU_S3C2410)
113 static struct subsys_interface s3c2410_pm_interface = {
114 .name = "s3c2410_pm",
115 .subsys = &s3c2410_subsys,
116 .add_dev = s3c2410_pm_add,
117 };
118
119 /* register ourselves */
120
s3c2410_pm_drvinit(void)121 static int __init s3c2410_pm_drvinit(void)
122 {
123 return subsys_interface_register(&s3c2410_pm_interface);
124 }
125
126 arch_initcall(s3c2410_pm_drvinit);
127
128 static struct subsys_interface s3c2410a_pm_interface = {
129 .name = "s3c2410a_pm",
130 .subsys = &s3c2410a_subsys,
131 .add_dev = s3c2410_pm_add,
132 };
133
s3c2410a_pm_drvinit(void)134 static int __init s3c2410a_pm_drvinit(void)
135 {
136 return subsys_interface_register(&s3c2410a_pm_interface);
137 }
138
139 arch_initcall(s3c2410a_pm_drvinit);
140 #endif
141
142 #if defined(CONFIG_CPU_S3C2440)
143 static struct subsys_interface s3c2440_pm_interface = {
144 .name = "s3c2440_pm",
145 .subsys = &s3c2440_subsys,
146 .add_dev = s3c2410_pm_add,
147 };
148
s3c2440_pm_drvinit(void)149 static int __init s3c2440_pm_drvinit(void)
150 {
151 return subsys_interface_register(&s3c2440_pm_interface);
152 }
153
154 arch_initcall(s3c2440_pm_drvinit);
155 #endif
156
157 #if defined(CONFIG_CPU_S3C2442)
158 static struct subsys_interface s3c2442_pm_interface = {
159 .name = "s3c2442_pm",
160 .subsys = &s3c2442_subsys,
161 .add_dev = s3c2410_pm_add,
162 };
163
s3c2442_pm_drvinit(void)164 static int __init s3c2442_pm_drvinit(void)
165 {
166 return subsys_interface_register(&s3c2442_pm_interface);
167 }
168
169 arch_initcall(s3c2442_pm_drvinit);
170 #endif
171