1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * OMAP3xxx PRM module functions
4  *
5  * Copyright (C) 2010-2012 Texas Instruments, Inc.
6  * Copyright (C) 2010 Nokia Corporation
7  * Benoît Cousson
8  * Paul Walmsley
9  * Rajendra Nayak <rnayak@ti.com>
10  */
11 
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/of_irq.h>
18 
19 #include "soc.h"
20 #include "common.h"
21 #include "vp.h"
22 #include "powerdomain.h"
23 #include "prm3xxx.h"
24 #include "prm2xxx_3xxx.h"
25 #include "cm2xxx_3xxx.h"
26 #include "prm-regbits-34xx.h"
27 #include "cm3xxx.h"
28 #include "cm-regbits-34xx.h"
29 #include "clock.h"
30 
31 static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
32 static void omap3xxx_prm_ocp_barrier(void);
33 static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
34 static void omap3xxx_prm_restore_irqen(u32 *saved_mask);
35 
36 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
37 	OMAP_PRCM_IRQ("wkup",	0,	0),
38 	OMAP_PRCM_IRQ("io",	9,	1),
39 };
40 
41 static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
42 	.ack			= OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
43 	.mask			= OMAP3_PRM_IRQENABLE_MPU_OFFSET,
44 	.nr_regs		= 1,
45 	.irqs			= omap3_prcm_irqs,
46 	.nr_irqs		= ARRAY_SIZE(omap3_prcm_irqs),
47 	.irq			= 11 + OMAP_INTC_START,
48 	.read_pending_irqs	= &omap3xxx_prm_read_pending_irqs,
49 	.ocp_barrier		= &omap3xxx_prm_ocp_barrier,
50 	.save_and_clear_irqen	= &omap3xxx_prm_save_and_clear_irqen,
51 	.restore_irqen		= &omap3xxx_prm_restore_irqen,
52 	.reconfigure_io_chain	= NULL,
53 };
54 
55 /*
56  * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware
57  *   register (which are specific to OMAP3xxx SoCs) to reset source ID
58  *   bit shifts (which is an OMAP SoC-independent enumeration)
59  */
60 static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = {
61 	{ OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
62 	{ OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
63 	{ OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
64 	{ OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
65 	{ OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
66 	{ OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
67 	{ OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT,
68 	  OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
69 	{ OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT,
70 	  OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
71 	{ OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
72 	{ OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT },
73 	{ -1, -1 },
74 };
75 
76 /* PRM VP */
77 
78 /*
79  * struct omap3_vp - OMAP3 VP register access description.
80  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
81  */
82 struct omap3_vp {
83 	u32 tranxdone_status;
84 };
85 
86 static struct omap3_vp omap3_vp[] = {
87 	[OMAP3_VP_VDD_MPU_ID] = {
88 		.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
89 	},
90 	[OMAP3_VP_VDD_CORE_ID] = {
91 		.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
92 	},
93 };
94 
95 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
96 
omap3_prm_vp_check_txdone(u8 vp_id)97 static u32 omap3_prm_vp_check_txdone(u8 vp_id)
98 {
99 	struct omap3_vp *vp = &omap3_vp[vp_id];
100 	u32 irqstatus;
101 
102 	irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
103 					   OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
104 	return irqstatus & vp->tranxdone_status;
105 }
106 
omap3_prm_vp_clear_txdone(u8 vp_id)107 static void omap3_prm_vp_clear_txdone(u8 vp_id)
108 {
109 	struct omap3_vp *vp = &omap3_vp[vp_id];
110 
111 	omap2_prm_write_mod_reg(vp->tranxdone_status,
112 				OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
113 }
114 
omap3_prm_vcvp_read(u8 offset)115 u32 omap3_prm_vcvp_read(u8 offset)
116 {
117 	return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
118 }
119 
omap3_prm_vcvp_write(u32 val,u8 offset)120 void omap3_prm_vcvp_write(u32 val, u8 offset)
121 {
122 	omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
123 }
124 
omap3_prm_vcvp_rmw(u32 mask,u32 bits,u8 offset)125 u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
126 {
127 	return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
128 }
129 
130 /**
131  * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC
132  *
133  * Set the DPLL3 reset bit, which should reboot the SoC.  This is the
134  * recommended way to restart the SoC, considering Errata i520.  No
135  * return value.
136  */
omap3xxx_prm_dpll3_reset(void)137 static void omap3xxx_prm_dpll3_reset(void)
138 {
139 	omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD,
140 				   OMAP2_RM_RSTCTRL);
141 	/* OCP barrier */
142 	omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL);
143 }
144 
145 /**
146  * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
147  * @events: ptr to a u32, preallocated by caller
148  *
149  * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
150  * MPU IRQs, and store the result into the u32 pointed to by @events.
151  * No return value.
152  */
omap3xxx_prm_read_pending_irqs(unsigned long * events)153 static void omap3xxx_prm_read_pending_irqs(unsigned long *events)
154 {
155 	u32 mask, st;
156 
157 	/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
158 	mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
159 	st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
160 
161 	events[0] = mask & st;
162 }
163 
164 /**
165  * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
166  *
167  * Force any buffered writes to the PRM IP block to complete.  Needed
168  * by the PRM IRQ handler, which reads and writes directly to the IP
169  * block, to avoid race conditions after acknowledging or clearing IRQ
170  * bits.  No return value.
171  */
omap3xxx_prm_ocp_barrier(void)172 static void omap3xxx_prm_ocp_barrier(void)
173 {
174 	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
175 }
176 
177 /**
178  * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
179  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
180  *
181  * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
182  * must be allocated by the caller.  Intended to be used in the PRM
183  * interrupt handler suspend callback.  The OCP barrier is needed to
184  * ensure the write to disable PRM interrupts reaches the PRM before
185  * returning; otherwise, spurious interrupts might occur.  No return
186  * value.
187  */
omap3xxx_prm_save_and_clear_irqen(u32 * saved_mask)188 static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
189 {
190 	saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
191 					       OMAP3_PRM_IRQENABLE_MPU_OFFSET);
192 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
193 
194 	/* OCP barrier */
195 	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
196 }
197 
198 /**
199  * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
200  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
201  *
202  * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
203  * to be used in the PRM interrupt handler resume callback to restore
204  * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
205  * barrier should be needed here; any pending PRM interrupts will fire
206  * once the writes reach the PRM.  No return value.
207  */
omap3xxx_prm_restore_irqen(u32 * saved_mask)208 static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
209 {
210 	omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
211 				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
212 }
213 
214 /**
215  * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
216  * @module: PRM module to clear wakeups from
217  * @regs: register set to clear, 1 or 3
218  * @wkst_mask: wkst bits to clear
219  *
220  * The purpose of this function is to clear any wake-up events latched
221  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
222  * may occur whilst attempting to clear a PM_WKST_x register and thus
223  * set another bit in this register. A while loop is used to ensure
224  * that any peripheral wake-up events occurring while attempting to
225  * clear the PM_WKST_x are detected and cleared.
226  */
omap3xxx_prm_clear_mod_irqs(s16 module,u8 regs,u32 wkst_mask)227 static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
228 {
229 	u32 wkst, fclk, iclk, clken;
230 	u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
231 	u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
232 	u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
233 	u16 grpsel_off = (regs == 3) ?
234 		OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
235 	int c = 0;
236 
237 	wkst = omap2_prm_read_mod_reg(module, wkst_off);
238 	wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
239 	wkst &= wkst_mask;
240 	if (wkst) {
241 		iclk = omap2_cm_read_mod_reg(module, iclk_off);
242 		fclk = omap2_cm_read_mod_reg(module, fclk_off);
243 		while (wkst) {
244 			clken = wkst;
245 			omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
246 			/*
247 			 * For USBHOST, we don't know whether HOST1 or
248 			 * HOST2 woke us up, so enable both f-clocks
249 			 */
250 			if (module == OMAP3430ES2_USBHOST_MOD)
251 				clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
252 			omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
253 			omap2_prm_write_mod_reg(wkst, module, wkst_off);
254 			wkst = omap2_prm_read_mod_reg(module, wkst_off);
255 			wkst &= wkst_mask;
256 			c++;
257 		}
258 		omap2_cm_write_mod_reg(iclk, module, iclk_off);
259 		omap2_cm_write_mod_reg(fclk, module, fclk_off);
260 	}
261 
262 	return c;
263 }
264 
265 /**
266  * omap3_prm_reset_modem - toggle reset signal for modem
267  *
268  * Toggles the reset signal to modem IP block. Required to allow
269  * OMAP3430 without stacked modem to idle properly.
270  */
omap3_prm_reset_modem(void)271 void __init omap3_prm_reset_modem(void)
272 {
273 	omap2_prm_write_mod_reg(
274 		OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
275 		OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
276 				CORE_MOD, OMAP2_RM_RSTCTRL);
277 	omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
278 }
279 
280 /**
281  * omap3_prm_init_pm - initialize PM related registers for PRM
282  * @has_uart4: SoC has UART4
283  * @has_iva: SoC has IVA
284  *
285  * Initializes PRM registers for PM use. Called from PM init.
286  */
omap3_prm_init_pm(bool has_uart4,bool has_iva)287 void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
288 {
289 	u32 en_uart4_mask;
290 	u32 grpsel_uart4_mask;
291 
292 	/*
293 	 * Enable control of expternal oscillator through
294 	 * sys_clkreq. In the long run clock framework should
295 	 * take care of this.
296 	 */
297 	omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
298 				   1 << OMAP_AUTOEXTCLKMODE_SHIFT,
299 				   OMAP3430_GR_MOD,
300 				   OMAP3_PRM_CLKSRC_CTRL_OFFSET);
301 
302 	/* setup wakup source */
303 	omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
304 				OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
305 				WKUP_MOD, PM_WKEN);
306 	/* No need to write EN_IO, that is always enabled */
307 	omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
308 				OMAP3430_GRPSEL_GPT1_MASK |
309 				OMAP3430_GRPSEL_GPT12_MASK,
310 				WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
311 
312 	/* Enable PM_WKEN to support DSS LPR */
313 	omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
314 				OMAP3430_DSS_MOD, PM_WKEN);
315 
316 	if (has_uart4) {
317 		en_uart4_mask = OMAP3630_EN_UART4_MASK;
318 		grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
319 	} else {
320 		en_uart4_mask = 0;
321 		grpsel_uart4_mask = 0;
322 	}
323 
324 	/* Enable wakeups in PER */
325 	omap2_prm_write_mod_reg(en_uart4_mask |
326 				OMAP3430_EN_GPIO2_MASK |
327 				OMAP3430_EN_GPIO3_MASK |
328 				OMAP3430_EN_GPIO4_MASK |
329 				OMAP3430_EN_GPIO5_MASK |
330 				OMAP3430_EN_GPIO6_MASK |
331 				OMAP3430_EN_UART3_MASK |
332 				OMAP3430_EN_MCBSP2_MASK |
333 				OMAP3430_EN_MCBSP3_MASK |
334 				OMAP3430_EN_MCBSP4_MASK,
335 				OMAP3430_PER_MOD, PM_WKEN);
336 
337 	/* and allow them to wake up MPU */
338 	omap2_prm_write_mod_reg(grpsel_uart4_mask |
339 				OMAP3430_GRPSEL_GPIO2_MASK |
340 				OMAP3430_GRPSEL_GPIO3_MASK |
341 				OMAP3430_GRPSEL_GPIO4_MASK |
342 				OMAP3430_GRPSEL_GPIO5_MASK |
343 				OMAP3430_GRPSEL_GPIO6_MASK |
344 				OMAP3430_GRPSEL_UART3_MASK |
345 				OMAP3430_GRPSEL_MCBSP2_MASK |
346 				OMAP3430_GRPSEL_MCBSP3_MASK |
347 				OMAP3430_GRPSEL_MCBSP4_MASK,
348 				OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
349 
350 	/* Don't attach IVA interrupts */
351 	if (has_iva) {
352 		omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
353 		omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
354 		omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
355 		omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
356 					OMAP3430_PM_IVAGRPSEL);
357 	}
358 
359 	/* Clear any pending 'reset' flags */
360 	omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
361 	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
362 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
363 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
364 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
365 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
366 	omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
367 				OMAP2_RM_RSTST);
368 
369 	/* Clear any pending PRCM interrupts */
370 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
371 
372 	/* We need to idle iva2_pwrdm even on am3703 with no iva2. */
373 	omap3xxx_prm_iva_idle();
374 
375 	omap3_prm_reset_modem();
376 }
377 
378 /**
379  * omap3430_pre_es3_1_reconfigure_io_chain - restart wake-up daisy chain
380  *
381  * The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only
382  * thing we can do is toggle EN_IO bit for earlier omaps.
383  */
omap3430_pre_es3_1_reconfigure_io_chain(void)384 static void omap3430_pre_es3_1_reconfigure_io_chain(void)
385 {
386 	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
387 				     PM_WKEN);
388 	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
389 				   PM_WKEN);
390 	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
391 }
392 
393 /**
394  * omap3_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
395  *
396  * Clear any previously-latched I/O wakeup events and ensure that the
397  * I/O wakeup gates are aligned with the current mux settings.  Works
398  * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
399  * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
400  * return value. These registers are only available in 3430 es3.1 and later.
401  */
omap3_prm_reconfigure_io_chain(void)402 static void omap3_prm_reconfigure_io_chain(void)
403 {
404 	int i = 0;
405 
406 	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
407 				   PM_WKEN);
408 
409 	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
410 			  OMAP3430_ST_IO_CHAIN_MASK,
411 			  MAX_IOPAD_LATCH_TIME, i);
412 	if (i == MAX_IOPAD_LATCH_TIME)
413 		pr_warn("PRM: I/O chain clock line assertion timed out\n");
414 
415 	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
416 				     PM_WKEN);
417 
418 	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
419 				   PM_WKST);
420 
421 	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
422 }
423 
424 /**
425  * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
426  *
427  * Activates the I/O wakeup event latches and allows events logged by
428  * those latches to signal a wakeup event to the PRCM.  For I/O
429  * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
430  * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
431  * No return value.
432  */
omap3xxx_prm_enable_io_wakeup(void)433 static void omap3xxx_prm_enable_io_wakeup(void)
434 {
435 	if (prm_features & PRM_HAS_IO_WAKEUP)
436 		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
437 					   PM_WKEN);
438 }
439 
440 /**
441  * omap3xxx_prm_read_reset_sources - return the last SoC reset source
442  *
443  * Return a u32 representing the last reset sources of the SoC.  The
444  * returned reset source bits are standardized across OMAP SoCs.
445  */
omap3xxx_prm_read_reset_sources(void)446 static u32 omap3xxx_prm_read_reset_sources(void)
447 {
448 	struct prm_reset_src_map *p;
449 	u32 r = 0;
450 	u32 v;
451 
452 	v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
453 
454 	p = omap3xxx_prm_reset_src_map;
455 	while (p->reg_shift >= 0 && p->std_shift >= 0) {
456 		if (v & (1 << p->reg_shift))
457 			r |= 1 << p->std_shift;
458 		p++;
459 	}
460 
461 	return r;
462 }
463 
464 /**
465  * omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
466  *
467  * In cases where IVA2 is activated by bootcode, it may prevent
468  * full-chip retention or off-mode because it is not idle.  This
469  * function forces the IVA2 into idle state so it can go
470  * into retention/off and thus allow full-chip retention/off.
471  */
omap3xxx_prm_iva_idle(void)472 void omap3xxx_prm_iva_idle(void)
473 {
474 	/* ensure IVA2 clock is disabled */
475 	omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
476 
477 	/* if no clock activity, nothing else to do */
478 	if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
479 	      OMAP3430_CLKACTIVITY_IVA2_MASK))
480 		return;
481 
482 	/* Reset IVA2 */
483 	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
484 				OMAP3430_RST2_IVA2_MASK |
485 				OMAP3430_RST3_IVA2_MASK,
486 				OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
487 
488 	/* Enable IVA2 clock */
489 	omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
490 			       OMAP3430_IVA2_MOD, CM_FCLKEN);
491 
492 	/* Un-reset IVA2 */
493 	omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
494 
495 	/* Disable IVA2 clock */
496 	omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
497 
498 	/* Reset IVA2 */
499 	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
500 				OMAP3430_RST2_IVA2_MASK |
501 				OMAP3430_RST3_IVA2_MASK,
502 				OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
503 }
504 
505 /**
506  * omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
507  *					  and clears it if asserted
508  *
509  * Checks if cold-reset has occurred and clears the status bit if yes. Returns
510  * 1 if cold-reset has occurred, 0 otherwise.
511  */
omap3xxx_prm_clear_global_cold_reset(void)512 int omap3xxx_prm_clear_global_cold_reset(void)
513 {
514 	if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
515 	    OMAP3430_GLOBAL_COLD_RST_MASK) {
516 		omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
517 					   OMAP3430_GR_MOD,
518 					   OMAP3_PRM_RSTST_OFFSET);
519 		return 1;
520 	}
521 
522 	return 0;
523 }
524 
omap3_prm_save_scratchpad_contents(u32 * ptr)525 void omap3_prm_save_scratchpad_contents(u32 *ptr)
526 {
527 	*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
528 					OMAP3_PRM_CLKSRC_CTRL_OFFSET);
529 
530 	*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
531 					OMAP3_PRM_CLKSEL_OFFSET);
532 }
533 
534 /* Powerdomain low-level functions */
535 
omap3_pwrdm_set_next_pwrst(struct powerdomain * pwrdm,u8 pwrst)536 static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
537 {
538 	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
539 				   (pwrst << OMAP_POWERSTATE_SHIFT),
540 				   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
541 	return 0;
542 }
543 
omap3_pwrdm_read_next_pwrst(struct powerdomain * pwrdm)544 static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
545 {
546 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
547 					     OMAP2_PM_PWSTCTRL,
548 					     OMAP_POWERSTATE_MASK);
549 }
550 
omap3_pwrdm_read_pwrst(struct powerdomain * pwrdm)551 static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm)
552 {
553 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
554 					     OMAP2_PM_PWSTST,
555 					     OMAP_POWERSTATEST_MASK);
556 }
557 
558 /* Applicable only for OMAP3. Not supported on OMAP2 */
omap3_pwrdm_read_prev_pwrst(struct powerdomain * pwrdm)559 static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
560 {
561 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
562 					     OMAP3430_PM_PREPWSTST,
563 					     OMAP3430_LASTPOWERSTATEENTERED_MASK);
564 }
565 
omap3_pwrdm_read_logic_pwrst(struct powerdomain * pwrdm)566 static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
567 {
568 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
569 					     OMAP2_PM_PWSTST,
570 					     OMAP3430_LOGICSTATEST_MASK);
571 }
572 
omap3_pwrdm_read_logic_retst(struct powerdomain * pwrdm)573 static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
574 {
575 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
576 					     OMAP2_PM_PWSTCTRL,
577 					     OMAP3430_LOGICSTATEST_MASK);
578 }
579 
omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain * pwrdm)580 static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
581 {
582 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
583 					     OMAP3430_PM_PREPWSTST,
584 					     OMAP3430_LASTLOGICSTATEENTERED_MASK);
585 }
586 
omap3_get_mem_bank_lastmemst_mask(u8 bank)587 static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
588 {
589 	switch (bank) {
590 	case 0:
591 		return OMAP3430_LASTMEM1STATEENTERED_MASK;
592 	case 1:
593 		return OMAP3430_LASTMEM2STATEENTERED_MASK;
594 	case 2:
595 		return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
596 	case 3:
597 		return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
598 	default:
599 		WARN_ON(1); /* should never happen */
600 		return -EEXIST;
601 	}
602 	return 0;
603 }
604 
omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain * pwrdm,u8 bank)605 static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
606 {
607 	u32 m;
608 
609 	m = omap3_get_mem_bank_lastmemst_mask(bank);
610 
611 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
612 				OMAP3430_PM_PREPWSTST, m);
613 }
614 
omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain * pwrdm)615 static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
616 {
617 	omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
618 	return 0;
619 }
620 
omap3_pwrdm_enable_hdwr_sar(struct powerdomain * pwrdm)621 static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
622 {
623 	return omap2_prm_rmw_mod_reg_bits(0,
624 					  1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
625 					  pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
626 }
627 
omap3_pwrdm_disable_hdwr_sar(struct powerdomain * pwrdm)628 static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
629 {
630 	return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
631 					  0, pwrdm->prcm_offs,
632 					  OMAP2_PM_PWSTCTRL);
633 }
634 
635 struct pwrdm_ops omap3_pwrdm_operations = {
636 	.pwrdm_set_next_pwrst	= omap3_pwrdm_set_next_pwrst,
637 	.pwrdm_read_next_pwrst	= omap3_pwrdm_read_next_pwrst,
638 	.pwrdm_read_pwrst	= omap3_pwrdm_read_pwrst,
639 	.pwrdm_read_prev_pwrst	= omap3_pwrdm_read_prev_pwrst,
640 	.pwrdm_set_logic_retst	= omap2_pwrdm_set_logic_retst,
641 	.pwrdm_read_logic_pwrst	= omap3_pwrdm_read_logic_pwrst,
642 	.pwrdm_read_logic_retst	= omap3_pwrdm_read_logic_retst,
643 	.pwrdm_read_prev_logic_pwrst	= omap3_pwrdm_read_prev_logic_pwrst,
644 	.pwrdm_set_mem_onst	= omap2_pwrdm_set_mem_onst,
645 	.pwrdm_set_mem_retst	= omap2_pwrdm_set_mem_retst,
646 	.pwrdm_read_mem_pwrst	= omap2_pwrdm_read_mem_pwrst,
647 	.pwrdm_read_mem_retst	= omap2_pwrdm_read_mem_retst,
648 	.pwrdm_read_prev_mem_pwrst	= omap3_pwrdm_read_prev_mem_pwrst,
649 	.pwrdm_clear_all_prev_pwrst	= omap3_pwrdm_clear_all_prev_pwrst,
650 	.pwrdm_enable_hdwr_sar	= omap3_pwrdm_enable_hdwr_sar,
651 	.pwrdm_disable_hdwr_sar	= omap3_pwrdm_disable_hdwr_sar,
652 	.pwrdm_wait_transition	= omap2_pwrdm_wait_transition,
653 };
654 
655 /*
656  *
657  */
658 
659 static int omap3xxx_prm_late_init(void);
660 
661 static struct prm_ll_data omap3xxx_prm_ll_data = {
662 	.read_reset_sources = &omap3xxx_prm_read_reset_sources,
663 	.late_init = &omap3xxx_prm_late_init,
664 	.assert_hardreset = &omap2_prm_assert_hardreset,
665 	.deassert_hardreset = &omap2_prm_deassert_hardreset,
666 	.is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
667 	.reset_system = &omap3xxx_prm_dpll3_reset,
668 	.clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs,
669 	.vp_check_txdone = &omap3_prm_vp_check_txdone,
670 	.vp_clear_txdone = &omap3_prm_vp_clear_txdone,
671 };
672 
omap3xxx_prm_init(const struct omap_prcm_init_data * data)673 int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
674 {
675 	omap2_clk_legacy_provider_init(TI_CLKM_PRM,
676 				       prm_base.va + OMAP3430_IVA2_MOD);
677 	if (omap3_has_io_wakeup())
678 		prm_features |= PRM_HAS_IO_WAKEUP;
679 
680 	return prm_register(&omap3xxx_prm_ll_data);
681 }
682 
683 static const struct of_device_id omap3_prm_dt_match_table[] = {
684 	{ .compatible = "ti,omap3-prm" },
685 	{ }
686 };
687 
omap3xxx_prm_late_init(void)688 static int omap3xxx_prm_late_init(void)
689 {
690 	struct device_node *np;
691 	int irq_num;
692 
693 	if (!(prm_features & PRM_HAS_IO_WAKEUP))
694 		return 0;
695 
696 	if (omap3_has_io_chain_ctrl())
697 		omap3_prcm_irq_setup.reconfigure_io_chain =
698 			omap3_prm_reconfigure_io_chain;
699 	else
700 		omap3_prcm_irq_setup.reconfigure_io_chain =
701 			omap3430_pre_es3_1_reconfigure_io_chain;
702 
703 	np = of_find_matching_node(NULL, omap3_prm_dt_match_table);
704 	if (!np) {
705 		pr_err("PRM: no device tree node for interrupt?\n");
706 
707 		return -ENODEV;
708 	}
709 
710 	irq_num = of_irq_get(np, 0);
711 	of_node_put(np);
712 	if (irq_num == -EPROBE_DEFER)
713 		return irq_num;
714 
715 	omap3_prcm_irq_setup.irq = irq_num;
716 
717 	omap3xxx_prm_enable_io_wakeup();
718 
719 	return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
720 }
721 
omap3xxx_prm_exit(void)722 static void __exit omap3xxx_prm_exit(void)
723 {
724 	prm_unregister(&omap3xxx_prm_ll_data);
725 }
726 __exitcall(omap3xxx_prm_exit);
727