1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interconnect/qcom,msm8974.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8974.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/reset/qcom,gcc-msm8974.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 xo_board: xo_board { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <19200000>; 22 }; 23 24 sleep_clk: sleep_clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <32768>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 interrupts = <GIC_PPI 9 0xf04>; 35 36 CPU0: cpu@0 { 37 compatible = "qcom,krait"; 38 enable-method = "qcom,kpss-acc-v2"; 39 device_type = "cpu"; 40 reg = <0>; 41 next-level-cache = <&L2>; 42 qcom,acc = <&acc0>; 43 qcom,saw = <&saw0>; 44 cpu-idle-states = <&CPU_SPC>; 45 }; 46 47 CPU1: cpu@1 { 48 compatible = "qcom,krait"; 49 enable-method = "qcom,kpss-acc-v2"; 50 device_type = "cpu"; 51 reg = <1>; 52 next-level-cache = <&L2>; 53 qcom,acc = <&acc1>; 54 qcom,saw = <&saw1>; 55 cpu-idle-states = <&CPU_SPC>; 56 }; 57 58 CPU2: cpu@2 { 59 compatible = "qcom,krait"; 60 enable-method = "qcom,kpss-acc-v2"; 61 device_type = "cpu"; 62 reg = <2>; 63 next-level-cache = <&L2>; 64 qcom,acc = <&acc2>; 65 qcom,saw = <&saw2>; 66 cpu-idle-states = <&CPU_SPC>; 67 }; 68 69 CPU3: cpu@3 { 70 compatible = "qcom,krait"; 71 enable-method = "qcom,kpss-acc-v2"; 72 device_type = "cpu"; 73 reg = <3>; 74 next-level-cache = <&L2>; 75 qcom,acc = <&acc3>; 76 qcom,saw = <&saw3>; 77 cpu-idle-states = <&CPU_SPC>; 78 }; 79 80 L2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 qcom,saw = <&saw_l2>; 84 }; 85 86 idle-states { 87 CPU_SPC: spc { 88 compatible = "qcom,idle-state-spc", 89 "arm,idle-state"; 90 entry-latency-us = <150>; 91 exit-latency-us = <200>; 92 min-residency-us = <2000>; 93 }; 94 }; 95 }; 96 97 firmware { 98 scm { 99 compatible = "qcom,scm"; 100 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 101 clock-names = "core", "bus", "iface"; 102 }; 103 }; 104 105 memory { 106 device_type = "memory"; 107 reg = <0x0 0x0>; 108 }; 109 110 pmu { 111 compatible = "qcom,krait-pmu"; 112 interrupts = <GIC_PPI 7 0xf04>; 113 }; 114 115 reserved-memory { 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges; 119 120 mpss_region: mpss@8000000 { 121 reg = <0x08000000 0x5100000>; 122 no-map; 123 }; 124 125 mba_region: mba@d100000 { 126 reg = <0x0d100000 0x100000>; 127 no-map; 128 }; 129 130 wcnss_region: wcnss@d200000 { 131 reg = <0x0d200000 0xa00000>; 132 no-map; 133 }; 134 135 adsp_region: adsp@dc00000 { 136 reg = <0x0dc00000 0x1900000>; 137 no-map; 138 }; 139 140 venus_region: memory@f500000 { 141 reg = <0x0f500000 0x500000>; 142 no-map; 143 }; 144 145 smem_region: smem@fa00000 { 146 reg = <0xfa00000 0x200000>; 147 no-map; 148 }; 149 150 tz_region: memory@fc00000 { 151 reg = <0x0fc00000 0x160000>; 152 no-map; 153 }; 154 155 rfsa_mem: memory@fd60000 { 156 reg = <0x0fd60000 0x20000>; 157 no-map; 158 }; 159 160 rmtfs@fd80000 { 161 compatible = "qcom,rmtfs-mem"; 162 reg = <0x0fd80000 0x180000>; 163 no-map; 164 165 qcom,client-id = <1>; 166 }; 167 }; 168 169 smem { 170 compatible = "qcom,smem"; 171 172 memory-region = <&smem_region>; 173 qcom,rpm-msg-ram = <&rpm_msg_ram>; 174 175 hwlocks = <&tcsr_mutex 3>; 176 }; 177 178 smp2p-adsp { 179 compatible = "qcom,smp2p"; 180 qcom,smem = <443>, <429>; 181 182 interrupt-parent = <&intc>; 183 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 184 185 qcom,ipc = <&apcs 8 10>; 186 187 qcom,local-pid = <0>; 188 qcom,remote-pid = <2>; 189 190 adsp_smp2p_out: master-kernel { 191 qcom,entry-name = "master-kernel"; 192 #qcom,smem-state-cells = <1>; 193 }; 194 195 adsp_smp2p_in: slave-kernel { 196 qcom,entry-name = "slave-kernel"; 197 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 }; 201 }; 202 203 smp2p-modem { 204 compatible = "qcom,smp2p"; 205 qcom,smem = <435>, <428>; 206 207 interrupt-parent = <&intc>; 208 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 209 210 qcom,ipc = <&apcs 8 14>; 211 212 qcom,local-pid = <0>; 213 qcom,remote-pid = <1>; 214 215 modem_smp2p_out: master-kernel { 216 qcom,entry-name = "master-kernel"; 217 #qcom,smem-state-cells = <1>; 218 }; 219 220 modem_smp2p_in: slave-kernel { 221 qcom,entry-name = "slave-kernel"; 222 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 }; 226 }; 227 228 smp2p-wcnss { 229 compatible = "qcom,smp2p"; 230 qcom,smem = <451>, <431>; 231 232 interrupt-parent = <&intc>; 233 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 234 235 qcom,ipc = <&apcs 8 18>; 236 237 qcom,local-pid = <0>; 238 qcom,remote-pid = <4>; 239 240 wcnss_smp2p_out: master-kernel { 241 qcom,entry-name = "master-kernel"; 242 243 #qcom,smem-state-cells = <1>; 244 }; 245 246 wcnss_smp2p_in: slave-kernel { 247 qcom,entry-name = "slave-kernel"; 248 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 }; 253 254 smsm { 255 compatible = "qcom,smsm"; 256 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 qcom,ipc-1 = <&apcs 8 13>; 261 qcom,ipc-2 = <&apcs 8 9>; 262 qcom,ipc-3 = <&apcs 8 19>; 263 264 apps_smsm: apps@0 { 265 reg = <0>; 266 267 #qcom,smem-state-cells = <1>; 268 }; 269 270 modem_smsm: modem@1 { 271 reg = <1>; 272 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 273 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 }; 277 278 adsp_smsm: adsp@2 { 279 reg = <2>; 280 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 281 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 }; 285 286 wcnss_smsm: wcnss@7 { 287 reg = <7>; 288 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 289 290 interrupt-controller; 291 #interrupt-cells = <2>; 292 }; 293 }; 294 295 smd { 296 compatible = "qcom,smd"; 297 298 rpm { 299 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 300 qcom,ipc = <&apcs 8 0>; 301 qcom,smd-edge = <15>; 302 303 rpm_requests: rpm_requests { 304 compatible = "qcom,rpm-msm8974"; 305 qcom,smd-channels = "rpm_requests"; 306 307 rpmcc: clock-controller { 308 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 309 #clock-cells = <1>; 310 }; 311 }; 312 }; 313 }; 314 315 soc: soc { 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges; 319 compatible = "simple-bus"; 320 321 intc: interrupt-controller@f9000000 { 322 compatible = "qcom,msm-qgic2"; 323 interrupt-controller; 324 #interrupt-cells = <3>; 325 reg = <0xf9000000 0x1000>, 326 <0xf9002000 0x1000>; 327 }; 328 329 apcs: syscon@f9011000 { 330 compatible = "syscon"; 331 reg = <0xf9011000 0x1000>; 332 }; 333 334 timer@f9020000 { 335 #address-cells = <1>; 336 #size-cells = <1>; 337 ranges; 338 compatible = "arm,armv7-timer-mem"; 339 reg = <0xf9020000 0x1000>; 340 clock-frequency = <19200000>; 341 342 frame@f9021000 { 343 frame-number = <0>; 344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 346 reg = <0xf9021000 0x1000>, 347 <0xf9022000 0x1000>; 348 }; 349 350 frame@f9023000 { 351 frame-number = <1>; 352 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 353 reg = <0xf9023000 0x1000>; 354 status = "disabled"; 355 }; 356 357 frame@f9024000 { 358 frame-number = <2>; 359 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 360 reg = <0xf9024000 0x1000>; 361 status = "disabled"; 362 }; 363 364 frame@f9025000 { 365 frame-number = <3>; 366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 367 reg = <0xf9025000 0x1000>; 368 status = "disabled"; 369 }; 370 371 frame@f9026000 { 372 frame-number = <4>; 373 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 374 reg = <0xf9026000 0x1000>; 375 status = "disabled"; 376 }; 377 378 frame@f9027000 { 379 frame-number = <5>; 380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 381 reg = <0xf9027000 0x1000>; 382 status = "disabled"; 383 }; 384 385 frame@f9028000 { 386 frame-number = <6>; 387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 388 reg = <0xf9028000 0x1000>; 389 status = "disabled"; 390 }; 391 }; 392 393 saw0: power-controller@f9089000 { 394 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 395 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 396 }; 397 398 saw1: power-controller@f9099000 { 399 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 400 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 401 }; 402 403 saw2: power-controller@f90a9000 { 404 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 405 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 406 }; 407 408 saw3: power-controller@f90b9000 { 409 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 410 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 411 }; 412 413 saw_l2: power-controller@f9012000 { 414 compatible = "qcom,saw2"; 415 reg = <0xf9012000 0x1000>; 416 regulator; 417 }; 418 419 acc0: clock-controller@f9088000 { 420 compatible = "qcom,kpss-acc-v2"; 421 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 422 }; 423 424 acc1: clock-controller@f9098000 { 425 compatible = "qcom,kpss-acc-v2"; 426 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 427 }; 428 429 acc2: clock-controller@f90a8000 { 430 compatible = "qcom,kpss-acc-v2"; 431 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 432 }; 433 434 acc3: clock-controller@f90b8000 { 435 compatible = "qcom,kpss-acc-v2"; 436 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 437 }; 438 439 sdhc_1: sdhci@f9824900 { 440 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 442 reg-names = "hc_mem", "core_mem"; 443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-names = "hc_irq", "pwr_irq"; 446 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 447 <&gcc GCC_SDCC1_AHB_CLK>, 448 <&xo_board>; 449 clock-names = "core", "iface", "xo"; 450 bus-width = <8>; 451 non-removable; 452 453 status = "disabled"; 454 }; 455 456 sdhc_3: sdhci@f9864900 { 457 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 459 reg-names = "hc_mem", "core_mem"; 460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "hc_irq", "pwr_irq"; 463 clocks = <&gcc GCC_SDCC3_APPS_CLK>, 464 <&gcc GCC_SDCC3_AHB_CLK>, 465 <&xo_board>; 466 clock-names = "core", "iface", "xo"; 467 bus-width = <4>; 468 469 #address-cells = <1>; 470 #size-cells = <0>; 471 472 status = "disabled"; 473 }; 474 475 sdhc_2: sdhci@f98a4900 { 476 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 478 reg-names = "hc_mem", "core_mem"; 479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "hc_irq", "pwr_irq"; 482 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 483 <&gcc GCC_SDCC2_AHB_CLK>, 484 <&xo_board>; 485 clock-names = "core", "iface", "xo"; 486 bus-width = <4>; 487 488 #address-cells = <1>; 489 #size-cells = <0>; 490 491 status = "disabled"; 492 }; 493 494 blsp1_uart1: serial@f991d000 { 495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 496 reg = <0xf991d000 0x1000>; 497 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 499 clock-names = "core", "iface"; 500 status = "disabled"; 501 }; 502 503 blsp1_uart2: serial@f991e000 { 504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 505 reg = <0xf991e000 0x1000>; 506 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 508 clock-names = "core", "iface"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&blsp1_uart2_default>; 511 status = "disabled"; 512 }; 513 514 blsp1_i2c1: i2c@f9923000 { 515 status = "disabled"; 516 compatible = "qcom,i2c-qup-v2.1.1"; 517 reg = <0xf9923000 0x1000>; 518 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 520 clock-names = "core", "iface"; 521 pinctrl-names = "default", "sleep"; 522 pinctrl-0 = <&blsp1_i2c1_default>; 523 pinctrl-1 = <&blsp1_i2c1_sleep>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 }; 527 528 blsp1_i2c2: i2c@f9924000 { 529 status = "disabled"; 530 compatible = "qcom,i2c-qup-v2.1.1"; 531 reg = <0xf9924000 0x1000>; 532 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 534 clock-names = "core", "iface"; 535 pinctrl-names = "default", "sleep"; 536 pinctrl-0 = <&blsp1_i2c2_default>; 537 pinctrl-1 = <&blsp1_i2c2_sleep>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 }; 541 542 blsp1_i2c3: i2c@f9925000 { 543 status = "disabled"; 544 compatible = "qcom,i2c-qup-v2.1.1"; 545 reg = <0xf9925000 0x1000>; 546 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 548 clock-names = "core", "iface"; 549 pinctrl-names = "default", "sleep"; 550 pinctrl-0 = <&blsp1_i2c3_default>; 551 pinctrl-1 = <&blsp1_i2c3_sleep>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 }; 555 556 blsp1_i2c6: i2c@f9928000 { 557 status = "disabled"; 558 compatible = "qcom,i2c-qup-v2.1.1"; 559 reg = <0xf9928000 0x1000>; 560 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 562 clock-names = "core", "iface"; 563 pinctrl-names = "default", "sleep"; 564 pinctrl-0 = <&blsp1_i2c6_default>; 565 pinctrl-1 = <&blsp1_i2c6_sleep>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 }; 569 570 blsp2_dma: dma-controller@f9944000 { 571 compatible = "qcom,bam-v1.4.0"; 572 reg = <0xf9944000 0x19000>; 573 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 575 clock-names = "bam_clk"; 576 #dma-cells = <1>; 577 qcom,ee = <0>; 578 }; 579 580 blsp2_uart1: serial@f995d000 { 581 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 582 reg = <0xf995d000 0x1000>; 583 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 585 clock-names = "core", "iface"; 586 pinctrl-names = "default", "sleep"; 587 pinctrl-0 = <&blsp2_uart1_default>; 588 pinctrl-1 = <&blsp2_uart1_sleep>; 589 status = "disabled"; 590 }; 591 592 blsp2_uart2: serial@f995e000 { 593 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 594 reg = <0xf995e000 0x1000>; 595 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 597 clock-names = "core", "iface"; 598 status = "disabled"; 599 }; 600 601 blsp2_uart4: serial@f9960000 { 602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 603 reg = <0xf9960000 0x1000>; 604 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 606 clock-names = "core", "iface"; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&blsp2_uart4_default>; 609 status = "disabled"; 610 }; 611 612 blsp2_i2c2: i2c@f9964000 { 613 status = "disabled"; 614 compatible = "qcom,i2c-qup-v2.1.1"; 615 reg = <0xf9964000 0x1000>; 616 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 618 clock-names = "core", "iface"; 619 pinctrl-names = "default", "sleep"; 620 pinctrl-0 = <&blsp2_i2c2_default>; 621 pinctrl-1 = <&blsp2_i2c2_sleep>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 }; 625 626 blsp2_i2c5: i2c@f9967000 { 627 status = "disabled"; 628 compatible = "qcom,i2c-qup-v2.1.1"; 629 reg = <0xf9967000 0x1000>; 630 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 632 clock-names = "core", "iface"; 633 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 634 dma-names = "tx", "rx"; 635 pinctrl-names = "default", "sleep"; 636 pinctrl-0 = <&blsp2_i2c5_default>; 637 pinctrl-1 = <&blsp2_i2c5_sleep>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 }; 641 642 blsp2_i2c6: i2c@f9968000 { 643 status = "disabled"; 644 compatible = "qcom,i2c-qup-v2.1.1"; 645 reg = <0xf9968000 0x1000>; 646 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 648 clock-names = "core", "iface"; 649 pinctrl-names = "default", "sleep"; 650 pinctrl-0 = <&blsp2_i2c6_default>; 651 pinctrl-1 = <&blsp2_i2c6_sleep>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 }; 655 656 otg: usb@f9a55000 { 657 compatible = "qcom,ci-hdrc"; 658 reg = <0xf9a55000 0x200>, 659 <0xf9a55200 0x200>; 660 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 662 <&gcc GCC_USB_HS_SYSTEM_CLK>; 663 clock-names = "iface", "core"; 664 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 665 assigned-clock-rates = <75000000>; 666 resets = <&gcc GCC_USB_HS_BCR>; 667 reset-names = "core"; 668 phy_type = "ulpi"; 669 dr_mode = "otg"; 670 ahb-burst-config = <0>; 671 phy-names = "usb-phy"; 672 status = "disabled"; 673 #reset-cells = <1>; 674 675 ulpi { 676 usb_hs1_phy: phy@a { 677 compatible = "qcom,usb-hs-phy-msm8974", 678 "qcom,usb-hs-phy"; 679 #phy-cells = <0>; 680 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 681 clock-names = "ref", "sleep"; 682 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 683 reset-names = "phy", "por"; 684 status = "disabled"; 685 }; 686 687 usb_hs2_phy: phy@b { 688 compatible = "qcom,usb-hs-phy-msm8974", 689 "qcom,usb-hs-phy"; 690 #phy-cells = <0>; 691 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 692 clock-names = "ref", "sleep"; 693 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; 694 reset-names = "phy", "por"; 695 status = "disabled"; 696 }; 697 }; 698 }; 699 700 rng@f9bff000 { 701 compatible = "qcom,prng"; 702 reg = <0xf9bff000 0x200>; 703 clocks = <&gcc GCC_PRNG_AHB_CLK>; 704 clock-names = "core"; 705 }; 706 707 pronto: remoteproc@fb21b000 { 708 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 709 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 710 reg-names = "ccu", "dxe", "pmu"; 711 712 memory-region = <&wcnss_region>; 713 714 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 715 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 716 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 717 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 718 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 719 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 720 721 qcom,smem-states = <&wcnss_smp2p_out 0>; 722 qcom,smem-state-names = "stop"; 723 724 status = "disabled"; 725 726 iris { 727 compatible = "qcom,wcn3680"; 728 729 clocks = <&rpmcc RPM_SMD_CXO_A2>; 730 clock-names = "xo"; 731 }; 732 733 smd-edge { 734 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 735 736 qcom,ipc = <&apcs 8 17>; 737 qcom,smd-edge = <6>; 738 739 wcnss { 740 compatible = "qcom,wcnss"; 741 qcom,smd-channels = "WCNSS_CTRL"; 742 status = "disabled"; 743 744 qcom,mmio = <&pronto>; 745 746 bt { 747 compatible = "qcom,wcnss-bt"; 748 }; 749 750 wifi { 751 compatible = "qcom,wcnss-wlan"; 752 753 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 754 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 755 interrupt-names = "tx", "rx"; 756 757 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 758 qcom,smem-state-names = "tx-enable", 759 "tx-rings-empty"; 760 }; 761 }; 762 }; 763 }; 764 765 etf@fc307000 { 766 compatible = "arm,coresight-tmc", "arm,primecell"; 767 reg = <0xfc307000 0x1000>; 768 769 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 770 clock-names = "apb_pclk", "atclk"; 771 772 out-ports { 773 port { 774 etf_out: endpoint { 775 remote-endpoint = <&replicator_in>; 776 }; 777 }; 778 }; 779 780 in-ports { 781 port { 782 etf_in: endpoint { 783 remote-endpoint = <&merger_out>; 784 }; 785 }; 786 }; 787 }; 788 789 tpiu@fc318000 { 790 compatible = "arm,coresight-tpiu", "arm,primecell"; 791 reg = <0xfc318000 0x1000>; 792 793 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 794 clock-names = "apb_pclk", "atclk"; 795 796 in-ports { 797 port { 798 tpiu_in: endpoint { 799 remote-endpoint = <&replicator_out1>; 800 }; 801 }; 802 }; 803 }; 804 805 funnel@fc31a000 { 806 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 807 reg = <0xfc31a000 0x1000>; 808 809 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 810 clock-names = "apb_pclk", "atclk"; 811 812 in-ports { 813 #address-cells = <1>; 814 #size-cells = <0>; 815 816 /* 817 * Not described input ports: 818 * 0 - not-connected 819 * 1 - connected trought funnel to Multimedia CPU 820 * 2 - connected to Wireless CPU 821 * 3 - not-connected 822 * 4 - not-connected 823 * 6 - not-connected 824 * 7 - connected to STM 825 */ 826 port@5 { 827 reg = <5>; 828 funnel1_in5: endpoint { 829 remote-endpoint = <&kpss_out>; 830 }; 831 }; 832 }; 833 834 out-ports { 835 port { 836 funnel1_out: endpoint { 837 remote-endpoint = <&merger_in1>; 838 }; 839 }; 840 }; 841 }; 842 843 funnel@fc31b000 { 844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 845 reg = <0xfc31b000 0x1000>; 846 847 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 848 clock-names = "apb_pclk", "atclk"; 849 850 in-ports { 851 #address-cells = <1>; 852 #size-cells = <0>; 853 854 /* 855 * Not described input ports: 856 * 0 - connected trought funnel to Audio, Modem and 857 * Resource and Power Manager CPU's 858 * 2...7 - not-connected 859 */ 860 port@1 { 861 reg = <1>; 862 merger_in1: endpoint { 863 remote-endpoint = <&funnel1_out>; 864 }; 865 }; 866 }; 867 868 out-ports { 869 port { 870 merger_out: endpoint { 871 remote-endpoint = <&etf_in>; 872 }; 873 }; 874 }; 875 }; 876 877 replicator@fc31c000 { 878 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 879 reg = <0xfc31c000 0x1000>; 880 881 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 882 clock-names = "apb_pclk", "atclk"; 883 884 out-ports { 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 port@0 { 889 reg = <0>; 890 replicator_out0: endpoint { 891 remote-endpoint = <&etr_in>; 892 }; 893 }; 894 port@1 { 895 reg = <1>; 896 replicator_out1: endpoint { 897 remote-endpoint = <&tpiu_in>; 898 }; 899 }; 900 }; 901 902 in-ports { 903 port { 904 replicator_in: endpoint { 905 remote-endpoint = <&etf_out>; 906 }; 907 }; 908 }; 909 }; 910 911 etr@fc322000 { 912 compatible = "arm,coresight-tmc", "arm,primecell"; 913 reg = <0xfc322000 0x1000>; 914 915 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 916 clock-names = "apb_pclk", "atclk"; 917 918 in-ports { 919 port { 920 etr_in: endpoint { 921 remote-endpoint = <&replicator_out0>; 922 }; 923 }; 924 }; 925 }; 926 927 etm@fc33c000 { 928 compatible = "arm,coresight-etm4x", "arm,primecell"; 929 reg = <0xfc33c000 0x1000>; 930 931 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 932 clock-names = "apb_pclk", "atclk"; 933 934 cpu = <&CPU0>; 935 936 out-ports { 937 port { 938 etm0_out: endpoint { 939 remote-endpoint = <&kpss_in0>; 940 }; 941 }; 942 }; 943 }; 944 945 etm@fc33d000 { 946 compatible = "arm,coresight-etm4x", "arm,primecell"; 947 reg = <0xfc33d000 0x1000>; 948 949 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 950 clock-names = "apb_pclk", "atclk"; 951 952 cpu = <&CPU1>; 953 954 out-ports { 955 port { 956 etm1_out: endpoint { 957 remote-endpoint = <&kpss_in1>; 958 }; 959 }; 960 }; 961 }; 962 963 etm@fc33e000 { 964 compatible = "arm,coresight-etm4x", "arm,primecell"; 965 reg = <0xfc33e000 0x1000>; 966 967 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 968 clock-names = "apb_pclk", "atclk"; 969 970 cpu = <&CPU2>; 971 972 out-ports { 973 port { 974 etm2_out: endpoint { 975 remote-endpoint = <&kpss_in2>; 976 }; 977 }; 978 }; 979 }; 980 981 etm@fc33f000 { 982 compatible = "arm,coresight-etm4x", "arm,primecell"; 983 reg = <0xfc33f000 0x1000>; 984 985 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 986 clock-names = "apb_pclk", "atclk"; 987 988 cpu = <&CPU3>; 989 990 out-ports { 991 port { 992 etm3_out: endpoint { 993 remote-endpoint = <&kpss_in3>; 994 }; 995 }; 996 }; 997 }; 998 999 /* KPSS funnel, only 4 inputs are used */ 1000 funnel@fc345000 { 1001 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1002 reg = <0xfc345000 0x1000>; 1003 1004 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1005 clock-names = "apb_pclk", "atclk"; 1006 1007 in-ports { 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 1011 port@0 { 1012 reg = <0>; 1013 kpss_in0: endpoint { 1014 remote-endpoint = <&etm0_out>; 1015 }; 1016 }; 1017 port@1 { 1018 reg = <1>; 1019 kpss_in1: endpoint { 1020 remote-endpoint = <&etm1_out>; 1021 }; 1022 }; 1023 port@2 { 1024 reg = <2>; 1025 kpss_in2: endpoint { 1026 remote-endpoint = <&etm2_out>; 1027 }; 1028 }; 1029 port@3 { 1030 reg = <3>; 1031 kpss_in3: endpoint { 1032 remote-endpoint = <&etm3_out>; 1033 }; 1034 }; 1035 }; 1036 1037 out-ports { 1038 port { 1039 kpss_out: endpoint { 1040 remote-endpoint = <&funnel1_in5>; 1041 }; 1042 }; 1043 }; 1044 }; 1045 1046 gcc: clock-controller@fc400000 { 1047 compatible = "qcom,gcc-msm8974"; 1048 #clock-cells = <1>; 1049 #reset-cells = <1>; 1050 #power-domain-cells = <1>; 1051 reg = <0xfc400000 0x4000>; 1052 }; 1053 1054 rpm_msg_ram: memory@fc428000 { 1055 compatible = "qcom,rpm-msg-ram"; 1056 reg = <0xfc428000 0x4000>; 1057 }; 1058 1059 bimc: interconnect@fc380000 { 1060 reg = <0xfc380000 0x6a000>; 1061 compatible = "qcom,msm8974-bimc"; 1062 #interconnect-cells = <1>; 1063 clock-names = "bus", "bus_a"; 1064 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1065 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1066 }; 1067 1068 snoc: interconnect@fc460000 { 1069 reg = <0xfc460000 0x4000>; 1070 compatible = "qcom,msm8974-snoc"; 1071 #interconnect-cells = <1>; 1072 clock-names = "bus", "bus_a"; 1073 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1074 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1075 }; 1076 1077 pnoc: interconnect@fc468000 { 1078 reg = <0xfc468000 0x4000>; 1079 compatible = "qcom,msm8974-pnoc"; 1080 #interconnect-cells = <1>; 1081 clock-names = "bus", "bus_a"; 1082 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1083 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1084 }; 1085 1086 ocmemnoc: interconnect@fc470000 { 1087 reg = <0xfc470000 0x4000>; 1088 compatible = "qcom,msm8974-ocmemnoc"; 1089 #interconnect-cells = <1>; 1090 clock-names = "bus", "bus_a"; 1091 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1092 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1093 }; 1094 1095 mmssnoc: interconnect@fc478000 { 1096 reg = <0xfc478000 0x4000>; 1097 compatible = "qcom,msm8974-mmssnoc"; 1098 #interconnect-cells = <1>; 1099 clock-names = "bus", "bus_a"; 1100 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1101 <&mmcc MMSS_S0_AXI_CLK>; 1102 }; 1103 1104 cnoc: interconnect@fc480000 { 1105 reg = <0xfc480000 0x4000>; 1106 compatible = "qcom,msm8974-cnoc"; 1107 #interconnect-cells = <1>; 1108 clock-names = "bus", "bus_a"; 1109 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1110 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1111 }; 1112 1113 tsens: thermal-sensor@fc4a9000 { 1114 compatible = "qcom,msm8974-tsens"; 1115 reg = <0xfc4a9000 0x1000>, /* TM */ 1116 <0xfc4a8000 0x1000>; /* SROT */ 1117 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 1118 nvmem-cell-names = "calib", "calib_backup"; 1119 #qcom,sensors = <11>; 1120 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1121 interrupt-names = "uplow"; 1122 #thermal-sensor-cells = <1>; 1123 }; 1124 1125 restart@fc4ab000 { 1126 compatible = "qcom,pshold"; 1127 reg = <0xfc4ab000 0x4>; 1128 }; 1129 1130 qfprom: qfprom@fc4bc000 { 1131 #address-cells = <1>; 1132 #size-cells = <1>; 1133 compatible = "qcom,qfprom"; 1134 reg = <0xfc4bc000 0x1000>; 1135 tsens_calib: calib@d0 { 1136 reg = <0xd0 0x18>; 1137 }; 1138 tsens_backup: backup@440 { 1139 reg = <0x440 0x10>; 1140 }; 1141 }; 1142 1143 spmi_bus: spmi@fc4cf000 { 1144 compatible = "qcom,spmi-pmic-arb"; 1145 reg-names = "core", "intr", "cnfg"; 1146 reg = <0xfc4cf000 0x1000>, 1147 <0xfc4cb000 0x1000>, 1148 <0xfc4ca000 0x1000>; 1149 interrupt-names = "periph_irq"; 1150 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1151 qcom,ee = <0>; 1152 qcom,channel = <0>; 1153 #address-cells = <2>; 1154 #size-cells = <0>; 1155 interrupt-controller; 1156 #interrupt-cells = <4>; 1157 }; 1158 1159 remoteproc_mss: remoteproc@fc880000 { 1160 compatible = "qcom,msm8974-mss-pil"; 1161 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1162 reg-names = "qdsp6", "rmb"; 1163 1164 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1165 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1166 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1167 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1168 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1169 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1170 1171 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1172 <&gcc GCC_MSS_CFG_AHB_CLK>, 1173 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1174 <&xo_board>; 1175 clock-names = "iface", "bus", "mem", "xo"; 1176 1177 resets = <&gcc GCC_MSS_RESTART>; 1178 reset-names = "mss_restart"; 1179 1180 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; 1181 1182 qcom,smem-states = <&modem_smp2p_out 0>; 1183 qcom,smem-state-names = "stop"; 1184 1185 status = "disabled"; 1186 1187 mba { 1188 memory-region = <&mba_region>; 1189 }; 1190 1191 mpss { 1192 memory-region = <&mpss_region>; 1193 }; 1194 1195 smd-edge { 1196 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1197 1198 qcom,ipc = <&apcs 8 12>; 1199 qcom,smd-edge = <0>; 1200 1201 label = "modem"; 1202 }; 1203 }; 1204 1205 tcsr_mutex_block: syscon@fd484000 { 1206 compatible = "syscon"; 1207 reg = <0xfd484000 0x2000>; 1208 }; 1209 1210 tcsr: syscon@fd4a0000 { 1211 compatible = "syscon"; 1212 reg = <0xfd4a0000 0x10000>; 1213 }; 1214 1215 tlmm: pinctrl@fd510000 { 1216 compatible = "qcom,msm8974-pinctrl"; 1217 reg = <0xfd510000 0x4000>; 1218 gpio-controller; 1219 gpio-ranges = <&tlmm 0 0 146>; 1220 #gpio-cells = <2>; 1221 interrupt-controller; 1222 #interrupt-cells = <2>; 1223 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1224 1225 sdc1_off: sdc1-off { 1226 clk { 1227 pins = "sdc1_clk"; 1228 bias-disable; 1229 drive-strength = <2>; 1230 }; 1231 1232 cmd { 1233 pins = "sdc1_cmd"; 1234 bias-pull-up; 1235 drive-strength = <2>; 1236 }; 1237 1238 data { 1239 pins = "sdc1_data"; 1240 bias-pull-up; 1241 drive-strength = <2>; 1242 }; 1243 }; 1244 1245 sdc2_off: sdc2-off { 1246 clk { 1247 pins = "sdc2_clk"; 1248 bias-disable; 1249 drive-strength = <2>; 1250 }; 1251 1252 cmd { 1253 pins = "sdc2_cmd"; 1254 bias-pull-up; 1255 drive-strength = <2>; 1256 }; 1257 1258 data { 1259 pins = "sdc2_data"; 1260 bias-pull-up; 1261 drive-strength = <2>; 1262 }; 1263 1264 cd { 1265 pins = "gpio54"; 1266 bias-disable; 1267 drive-strength = <2>; 1268 }; 1269 }; 1270 1271 blsp1_uart2_default: blsp1-uart2-default { 1272 rx { 1273 pins = "gpio5"; 1274 function = "blsp_uart2"; 1275 drive-strength = <2>; 1276 bias-pull-up; 1277 }; 1278 1279 tx { 1280 pins = "gpio4"; 1281 function = "blsp_uart2"; 1282 drive-strength = <4>; 1283 bias-disable; 1284 }; 1285 }; 1286 1287 blsp2_uart1_default: blsp2-uart1-default { 1288 tx-rts { 1289 pins = "gpio41", "gpio44"; 1290 function = "blsp_uart7"; 1291 drive-strength = <2>; 1292 bias-disable; 1293 }; 1294 1295 rx-cts { 1296 pins = "gpio42", "gpio43"; 1297 function = "blsp_uart7"; 1298 drive-strength = <2>; 1299 bias-pull-up; 1300 }; 1301 }; 1302 1303 blsp2_uart1_sleep: blsp2-uart1-sleep { 1304 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1305 function = "gpio"; 1306 drive-strength = <2>; 1307 bias-pull-down; 1308 }; 1309 1310 blsp2_uart4_default: blsp2-uart4-default { 1311 tx-rts { 1312 pins = "gpio53", "gpio56"; 1313 function = "blsp_uart10"; 1314 drive-strength = <2>; 1315 bias-disable; 1316 }; 1317 1318 rx-cts { 1319 pins = "gpio54", "gpio55"; 1320 function = "blsp_uart10"; 1321 drive-strength = <2>; 1322 bias-pull-up; 1323 }; 1324 }; 1325 1326 blsp1_i2c1_default: blsp1-i2c1-default { 1327 pins = "gpio2", "gpio3"; 1328 function = "blsp_i2c1"; 1329 drive-strength = <2>; 1330 bias-disable; 1331 }; 1332 1333 blsp1_i2c1_sleep: blsp1-i2c1-sleep { 1334 pins = "gpio2", "gpio3"; 1335 function = "blsp_i2c1"; 1336 drive-strength = <2>; 1337 bias-pull-up; 1338 }; 1339 1340 blsp1_i2c2_default: blsp1-i2c2-default { 1341 pins = "gpio6", "gpio7"; 1342 function = "blsp_i2c2"; 1343 drive-strength = <2>; 1344 bias-disable; 1345 }; 1346 1347 blsp1_i2c2_sleep: blsp1-i2c2-sleep { 1348 pins = "gpio6", "gpio7"; 1349 function = "blsp_i2c2"; 1350 drive-strength = <2>; 1351 bias-pull-up; 1352 }; 1353 1354 blsp1_i2c3_default: blsp1-i2c3-default { 1355 pins = "gpio10", "gpio11"; 1356 function = "blsp_i2c3"; 1357 drive-strength = <2>; 1358 bias-disable; 1359 }; 1360 1361 blsp1_i2c3_sleep: blsp1-i2c3-sleep { 1362 pins = "gpio10", "gpio11"; 1363 function = "blsp_i2c3"; 1364 drive-strength = <2>; 1365 bias-pull-up; 1366 }; 1367 1368 /* BLSP1_I2C4 info is missing */ 1369 1370 /* BLSP1_I2C5 info is missing */ 1371 1372 blsp1_i2c6_default: blsp1-i2c6-default { 1373 pins = "gpio29", "gpio30"; 1374 function = "blsp_i2c6"; 1375 drive-strength = <2>; 1376 bias-disable; 1377 }; 1378 1379 blsp1_i2c6_sleep: blsp1-i2c6-sleep { 1380 pins = "gpio29", "gpio30"; 1381 function = "blsp_i2c6"; 1382 drive-strength = <2>; 1383 bias-pull-up; 1384 }; 1385 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1386 1387 /* BLSP2_I2C1 info is missing */ 1388 1389 blsp2_i2c2_default: blsp2-i2c2-default { 1390 pins = "gpio47", "gpio48"; 1391 function = "blsp_i2c8"; 1392 drive-strength = <2>; 1393 bias-disable; 1394 }; 1395 1396 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1397 pins = "gpio47", "gpio48"; 1398 function = "blsp_i2c8"; 1399 drive-strength = <2>; 1400 bias-pull-up; 1401 }; 1402 1403 /* BLSP2_I2C3 info is missing */ 1404 1405 /* BLSP2_I2C4 info is missing */ 1406 1407 blsp2_i2c5_default: blsp2-i2c5-default { 1408 pins = "gpio83", "gpio84"; 1409 function = "blsp_i2c11"; 1410 drive-strength = <2>; 1411 bias-disable; 1412 }; 1413 1414 blsp2_i2c5_sleep: blsp2-i2c5-sleep { 1415 pins = "gpio83", "gpio84"; 1416 function = "blsp_i2c11"; 1417 drive-strength = <2>; 1418 bias-pull-up; 1419 }; 1420 1421 blsp2_i2c6_default: blsp2-i2c6-default { 1422 pins = "gpio87", "gpio88"; 1423 function = "blsp_i2c12"; 1424 drive-strength = <2>; 1425 bias-disable; 1426 }; 1427 1428 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1429 pins = "gpio87", "gpio88"; 1430 function = "blsp_i2c12"; 1431 drive-strength = <2>; 1432 bias-pull-up; 1433 }; 1434 1435 spi8_default: spi8_default { 1436 mosi { 1437 pins = "gpio45"; 1438 function = "blsp_spi8"; 1439 }; 1440 miso { 1441 pins = "gpio46"; 1442 function = "blsp_spi8"; 1443 }; 1444 cs { 1445 pins = "gpio47"; 1446 function = "blsp_spi8"; 1447 }; 1448 clk { 1449 pins = "gpio48"; 1450 function = "blsp_spi8"; 1451 }; 1452 }; 1453 }; 1454 1455 mmcc: clock-controller@fd8c0000 { 1456 compatible = "qcom,mmcc-msm8974"; 1457 #clock-cells = <1>; 1458 #reset-cells = <1>; 1459 #power-domain-cells = <1>; 1460 reg = <0xfd8c0000 0x6000>; 1461 }; 1462 1463 mdss: mdss@fd900000 { 1464 compatible = "qcom,mdss"; 1465 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1466 reg-names = "mdss_phys", "vbif_phys"; 1467 1468 power-domains = <&mmcc MDSS_GDSC>; 1469 1470 clocks = <&mmcc MDSS_AHB_CLK>, 1471 <&mmcc MDSS_AXI_CLK>, 1472 <&mmcc MDSS_VSYNC_CLK>; 1473 clock-names = "iface", "bus", "vsync"; 1474 1475 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1476 1477 interrupt-controller; 1478 #interrupt-cells = <1>; 1479 1480 status = "disabled"; 1481 1482 #address-cells = <1>; 1483 #size-cells = <1>; 1484 ranges; 1485 1486 mdp: mdp@fd900000 { 1487 compatible = "qcom,mdp5"; 1488 reg = <0xfd900100 0x22000>; 1489 reg-names = "mdp_phys"; 1490 1491 interrupt-parent = <&mdss>; 1492 interrupts = <0>; 1493 1494 clocks = <&mmcc MDSS_AHB_CLK>, 1495 <&mmcc MDSS_AXI_CLK>, 1496 <&mmcc MDSS_MDP_CLK>, 1497 <&mmcc MDSS_VSYNC_CLK>; 1498 clock-names = "iface", "bus", "core", "vsync"; 1499 1500 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1501 interconnect-names = "mdp0-mem"; 1502 1503 ports { 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 1507 port@0 { 1508 reg = <0>; 1509 mdp5_intf1_out: endpoint { 1510 remote-endpoint = <&dsi0_in>; 1511 }; 1512 }; 1513 }; 1514 }; 1515 1516 dsi0: dsi@fd922800 { 1517 compatible = "qcom,mdss-dsi-ctrl"; 1518 reg = <0xfd922800 0x1f8>; 1519 reg-names = "dsi_ctrl"; 1520 1521 interrupt-parent = <&mdss>; 1522 interrupts = <4>; 1523 1524 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1525 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1526 1527 clocks = <&mmcc MDSS_MDP_CLK>, 1528 <&mmcc MDSS_AHB_CLK>, 1529 <&mmcc MDSS_AXI_CLK>, 1530 <&mmcc MDSS_BYTE0_CLK>, 1531 <&mmcc MDSS_PCLK0_CLK>, 1532 <&mmcc MDSS_ESC0_CLK>, 1533 <&mmcc MMSS_MISC_AHB_CLK>; 1534 clock-names = "mdp_core", 1535 "iface", 1536 "bus", 1537 "byte", 1538 "pixel", 1539 "core", 1540 "core_mmss"; 1541 1542 phys = <&dsi0_phy>; 1543 phy-names = "dsi-phy"; 1544 1545 status = "disabled"; 1546 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 1550 ports { 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 1554 port@0 { 1555 reg = <0>; 1556 dsi0_in: endpoint { 1557 remote-endpoint = <&mdp5_intf1_out>; 1558 }; 1559 }; 1560 1561 port@1 { 1562 reg = <1>; 1563 dsi0_out: endpoint { 1564 }; 1565 }; 1566 }; 1567 }; 1568 1569 dsi0_phy: dsi-phy@fd922a00 { 1570 compatible = "qcom,dsi-phy-28nm-hpm"; 1571 reg = <0xfd922a00 0xd4>, 1572 <0xfd922b00 0x280>, 1573 <0xfd922d80 0x30>; 1574 reg-names = "dsi_pll", 1575 "dsi_phy", 1576 "dsi_phy_regulator"; 1577 1578 #clock-cells = <1>; 1579 #phy-cells = <0>; 1580 1581 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1582 clock-names = "iface", "ref"; 1583 1584 status = "disabled"; 1585 }; 1586 }; 1587 1588 gpu: adreno@fdb00000 { 1589 compatible = "qcom,adreno-330.1", "qcom,adreno"; 1590 reg = <0xfdb00000 0x10000>; 1591 reg-names = "kgsl_3d0_reg_memory"; 1592 1593 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1594 interrupt-names = "kgsl_3d0_irq"; 1595 1596 clocks = <&mmcc OXILI_GFX3D_CLK>, 1597 <&mmcc OXILICX_AHB_CLK>, 1598 <&mmcc OXILICX_AXI_CLK>; 1599 clock-names = "core", "iface", "mem_iface"; 1600 1601 sram = <&gmu_sram>; 1602 power-domains = <&mmcc OXILICX_GDSC>; 1603 operating-points-v2 = <&gpu_opp_table>; 1604 1605 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 1606 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 1607 interconnect-names = "gfx-mem", "ocmem"; 1608 1609 // iommus = <&gpu_iommu 0>; 1610 1611 status = "disabled"; 1612 1613 gpu_opp_table: opp_table { 1614 compatible = "operating-points-v2"; 1615 1616 opp-320000000 { 1617 opp-hz = /bits/ 64 <320000000>; 1618 }; 1619 1620 opp-200000000 { 1621 opp-hz = /bits/ 64 <200000000>; 1622 }; 1623 1624 opp-27000000 { 1625 opp-hz = /bits/ 64 <27000000>; 1626 }; 1627 }; 1628 }; 1629 1630 ocmem@fdd00000 { 1631 compatible = "qcom,msm8974-ocmem"; 1632 reg = <0xfdd00000 0x2000>, 1633 <0xfec00000 0x180000>; 1634 reg-names = "ctrl", "mem"; 1635 ranges = <0 0xfec00000 0x180000>; 1636 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1637 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1638 clock-names = "core", "iface"; 1639 1640 #address-cells = <1>; 1641 #size-cells = <1>; 1642 1643 gmu_sram: gmu-sram@0 { 1644 reg = <0x0 0x100000>; 1645 }; 1646 }; 1647 1648 remoteproc_adsp: remoteproc@fe200000 { 1649 compatible = "qcom,msm8974-adsp-pil"; 1650 reg = <0xfe200000 0x100>; 1651 1652 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1653 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1654 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1655 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1656 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1657 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1658 1659 clocks = <&xo_board>; 1660 clock-names = "xo"; 1661 1662 memory-region = <&adsp_region>; 1663 1664 qcom,smem-states = <&adsp_smp2p_out 0>; 1665 qcom,smem-state-names = "stop"; 1666 1667 status = "disabled"; 1668 1669 smd-edge { 1670 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1671 1672 qcom,ipc = <&apcs 8 8>; 1673 qcom,smd-edge = <1>; 1674 label = "lpass"; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 }; 1678 }; 1679 1680 imem: imem@fe805000 { 1681 compatible = "syscon", "simple-mfd"; 1682 reg = <0xfe805000 0x1000>; 1683 1684 reboot-mode { 1685 compatible = "syscon-reboot-mode"; 1686 offset = <0x65c>; 1687 }; 1688 }; 1689 }; 1690 1691 tcsr_mutex: tcsr-mutex { 1692 compatible = "qcom,tcsr-mutex"; 1693 syscon = <&tcsr_mutex_block 0 0x80>; 1694 1695 #hwlock-cells = <1>; 1696 }; 1697 1698 thermal-zones { 1699 cpu0-thermal { 1700 polling-delay-passive = <250>; 1701 polling-delay = <1000>; 1702 1703 thermal-sensors = <&tsens 5>; 1704 1705 trips { 1706 cpu_alert0: trip0 { 1707 temperature = <75000>; 1708 hysteresis = <2000>; 1709 type = "passive"; 1710 }; 1711 cpu_crit0: trip1 { 1712 temperature = <110000>; 1713 hysteresis = <2000>; 1714 type = "critical"; 1715 }; 1716 }; 1717 }; 1718 1719 cpu1-thermal { 1720 polling-delay-passive = <250>; 1721 polling-delay = <1000>; 1722 1723 thermal-sensors = <&tsens 6>; 1724 1725 trips { 1726 cpu_alert1: trip0 { 1727 temperature = <75000>; 1728 hysteresis = <2000>; 1729 type = "passive"; 1730 }; 1731 cpu_crit1: trip1 { 1732 temperature = <110000>; 1733 hysteresis = <2000>; 1734 type = "critical"; 1735 }; 1736 }; 1737 }; 1738 1739 cpu2-thermal { 1740 polling-delay-passive = <250>; 1741 polling-delay = <1000>; 1742 1743 thermal-sensors = <&tsens 7>; 1744 1745 trips { 1746 cpu_alert2: trip0 { 1747 temperature = <75000>; 1748 hysteresis = <2000>; 1749 type = "passive"; 1750 }; 1751 cpu_crit2: trip1 { 1752 temperature = <110000>; 1753 hysteresis = <2000>; 1754 type = "critical"; 1755 }; 1756 }; 1757 }; 1758 1759 cpu3-thermal { 1760 polling-delay-passive = <250>; 1761 polling-delay = <1000>; 1762 1763 thermal-sensors = <&tsens 8>; 1764 1765 trips { 1766 cpu_alert3: trip0 { 1767 temperature = <75000>; 1768 hysteresis = <2000>; 1769 type = "passive"; 1770 }; 1771 cpu_crit3: trip1 { 1772 temperature = <110000>; 1773 hysteresis = <2000>; 1774 type = "critical"; 1775 }; 1776 }; 1777 }; 1778 1779 q6-dsp-thermal { 1780 polling-delay-passive = <250>; 1781 polling-delay = <1000>; 1782 1783 thermal-sensors = <&tsens 1>; 1784 1785 trips { 1786 q6_dsp_alert0: trip-point0 { 1787 temperature = <90000>; 1788 hysteresis = <2000>; 1789 type = "hot"; 1790 }; 1791 }; 1792 }; 1793 1794 modemtx-thermal { 1795 polling-delay-passive = <250>; 1796 polling-delay = <1000>; 1797 1798 thermal-sensors = <&tsens 2>; 1799 1800 trips { 1801 modemtx_alert0: trip-point0 { 1802 temperature = <90000>; 1803 hysteresis = <2000>; 1804 type = "hot"; 1805 }; 1806 }; 1807 }; 1808 1809 video-thermal { 1810 polling-delay-passive = <250>; 1811 polling-delay = <1000>; 1812 1813 thermal-sensors = <&tsens 3>; 1814 1815 trips { 1816 video_alert0: trip-point0 { 1817 temperature = <95000>; 1818 hysteresis = <2000>; 1819 type = "hot"; 1820 }; 1821 }; 1822 }; 1823 1824 wlan-thermal { 1825 polling-delay-passive = <250>; 1826 polling-delay = <1000>; 1827 1828 thermal-sensors = <&tsens 4>; 1829 1830 trips { 1831 wlan_alert0: trip-point0 { 1832 temperature = <105000>; 1833 hysteresis = <2000>; 1834 type = "hot"; 1835 }; 1836 }; 1837 }; 1838 1839 gpu-top-thermal { 1840 polling-delay-passive = <250>; 1841 polling-delay = <1000>; 1842 1843 thermal-sensors = <&tsens 9>; 1844 1845 trips { 1846 gpu1_alert0: trip-point0 { 1847 temperature = <90000>; 1848 hysteresis = <2000>; 1849 type = "hot"; 1850 }; 1851 }; 1852 }; 1853 1854 gpu-bottom-thermal { 1855 polling-delay-passive = <250>; 1856 polling-delay = <1000>; 1857 1858 thermal-sensors = <&tsens 10>; 1859 1860 trips { 1861 gpu2_alert0: trip-point0 { 1862 temperature = <90000>; 1863 hysteresis = <2000>; 1864 type = "hot"; 1865 }; 1866 }; 1867 }; 1868 }; 1869 1870 timer { 1871 compatible = "arm,armv7-timer"; 1872 interrupts = <GIC_PPI 2 0xf08>, 1873 <GIC_PPI 3 0xf08>, 1874 <GIC_PPI 4 0xf08>, 1875 <GIC_PPI 1 0xf08>; 1876 clock-frequency = <19200000>; 1877 }; 1878 1879 vreg_boost: vreg-boost { 1880 compatible = "regulator-fixed"; 1881 1882 regulator-name = "vreg-boost"; 1883 regulator-min-microvolt = <3150000>; 1884 regulator-max-microvolt = <3150000>; 1885 1886 regulator-always-on; 1887 regulator-boot-on; 1888 1889 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; 1890 enable-active-high; 1891 1892 pinctrl-names = "default"; 1893 pinctrl-0 = <&boost_bypass_n_pin>; 1894 }; 1895 1896 vreg_vph_pwr: vreg-vph-pwr { 1897 compatible = "regulator-fixed"; 1898 regulator-name = "vph-pwr"; 1899 1900 regulator-min-microvolt = <3600000>; 1901 regulator-max-microvolt = <3600000>; 1902 1903 regulator-always-on; 1904 }; 1905}; 1906