1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/mfd/qcom-rpm.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	model = "Qualcomm MSM8960";
13	compatible = "qcom,msm8960";
14	interrupt-parent = <&intc>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		interrupts = <1 14 0x304>;
20
21		cpu@0 {
22			compatible = "qcom,krait";
23			enable-method = "qcom,kpss-acc-v1";
24			device_type = "cpu";
25			reg = <0>;
26			next-level-cache = <&L2>;
27			qcom,acc = <&acc0>;
28			qcom,saw = <&saw0>;
29		};
30
31		cpu@1 {
32			compatible = "qcom,krait";
33			enable-method = "qcom,kpss-acc-v1";
34			device_type = "cpu";
35			reg = <1>;
36			next-level-cache = <&L2>;
37			qcom,acc = <&acc1>;
38			qcom,saw = <&saw1>;
39		};
40
41		L2: l2-cache {
42			compatible = "cache";
43			cache-level = <2>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x0 0x0>;
50	};
51
52	cpu-pmu {
53		compatible = "qcom,krait-pmu";
54		interrupts = <1 10 0x304>;
55		qcom,no-pc-write;
56	};
57
58	clocks {
59		cxo_board {
60			compatible = "fixed-clock";
61			#clock-cells = <0>;
62			clock-frequency = <19200000>;
63			clock-output-names = "cxo_board";
64		};
65
66		pxo_board {
67			compatible = "fixed-clock";
68			#clock-cells = <0>;
69			clock-frequency = <27000000>;
70			clock-output-names = "pxo_board";
71		};
72
73		sleep_clk {
74			compatible = "fixed-clock";
75			#clock-cells = <0>;
76			clock-frequency = <32768>;
77			clock-output-names = "sleep_clk";
78		};
79	};
80
81	/* Temporary fixed regulator */
82	vsdcc_fixed: vsdcc-regulator {
83		compatible = "regulator-fixed";
84		regulator-name = "SDCC Power";
85		regulator-min-microvolt = <2700000>;
86		regulator-max-microvolt = <2700000>;
87		regulator-always-on;
88	};
89
90	soc: soc {
91		#address-cells = <1>;
92		#size-cells = <1>;
93		ranges;
94		compatible = "simple-bus";
95
96		intc: interrupt-controller@2000000 {
97			compatible = "qcom,msm-qgic2";
98			interrupt-controller;
99			#interrupt-cells = <3>;
100			reg = <0x02000000 0x1000>,
101			      <0x02002000 0x1000>;
102		};
103
104		timer@200a000 {
105			compatible = "qcom,kpss-timer",
106				     "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
107			interrupts = <1 1 0x301>,
108				     <1 2 0x301>,
109				     <1 3 0x301>;
110			reg = <0x0200a000 0x100>;
111			clock-frequency = <27000000>,
112					  <32768>;
113			cpu-offset = <0x80000>;
114		};
115
116		msmgpio: pinctrl@800000 {
117			compatible = "qcom,msm8960-pinctrl";
118			gpio-controller;
119			gpio-ranges = <&msmgpio 0 0 152>;
120			#gpio-cells = <2>;
121			interrupts = <0 16 0x4>;
122			interrupt-controller;
123			#interrupt-cells = <2>;
124			reg = <0x800000 0x4000>;
125		};
126
127		gcc: clock-controller@900000 {
128			compatible = "qcom,gcc-msm8960";
129			#clock-cells = <1>;
130			#power-domain-cells = <1>;
131			#reset-cells = <1>;
132			reg = <0x900000 0x4000>;
133		};
134
135		lcc: clock-controller@28000000 {
136			compatible = "qcom,lcc-msm8960";
137			reg = <0x28000000 0x1000>;
138			#clock-cells = <1>;
139			#reset-cells = <1>;
140		};
141
142		clock-controller@4000000 {
143			compatible = "qcom,mmcc-msm8960";
144			reg = <0x4000000 0x1000>;
145			#clock-cells = <1>;
146			#power-domain-cells = <1>;
147			#reset-cells = <1>;
148		};
149
150		l2cc: clock-controller@2011000 {
151			compatible	= "qcom,kpss-gcc", "syscon";
152			reg		= <0x2011000 0x1000>;
153		};
154
155		rpm@108000 {
156			compatible	= "qcom,rpm-msm8960";
157			reg		= <0x108000 0x1000>;
158			qcom,ipc	= <&l2cc 0x8 2>;
159
160			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
161					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
162					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
163			interrupt-names	= "ack", "err", "wakeup";
164
165			regulators {
166				compatible = "qcom,rpm-pm8921-regulators";
167			};
168		};
169
170		acc0: clock-controller@2088000 {
171			compatible = "qcom,kpss-acc-v1";
172			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
173		};
174
175		acc1: clock-controller@2098000 {
176			compatible = "qcom,kpss-acc-v1";
177			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
178		};
179
180		saw0: regulator@2089000 {
181			compatible = "qcom,saw2";
182			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
183			regulator;
184		};
185
186		saw1: regulator@2099000 {
187			compatible = "qcom,saw2";
188			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
189			regulator;
190		};
191
192		gsbi5: gsbi@16400000 {
193			compatible = "qcom,gsbi-v1.0.0";
194			cell-index = <5>;
195			reg = <0x16400000 0x100>;
196			clocks = <&gcc GSBI5_H_CLK>;
197			clock-names = "iface";
198			#address-cells = <1>;
199			#size-cells = <1>;
200			ranges;
201
202			syscon-tcsr = <&tcsr>;
203
204			gsbi5_serial: serial@16440000 {
205				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
206				reg = <0x16440000 0x1000>,
207				      <0x16400000 0x1000>;
208				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
209				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
210				clock-names = "core", "iface";
211				status = "disabled";
212			};
213		};
214
215		qcom,ssbi@500000 {
216			compatible = "qcom,ssbi";
217			reg = <0x500000 0x1000>;
218			qcom,controller-type = "pmic-arbiter";
219
220			pmicintc: pmic@0 {
221				compatible = "qcom,pm8921";
222				interrupt-parent = <&msmgpio>;
223				interrupts = <104 8>;
224				#interrupt-cells = <2>;
225				interrupt-controller;
226				#address-cells = <1>;
227				#size-cells = <0>;
228
229				pwrkey@1c {
230					compatible = "qcom,pm8921-pwrkey";
231					reg = <0x1c>;
232					interrupt-parent = <&pmicintc>;
233					interrupts = <50 1>, <51 1>;
234					debounce = <15625>;
235					pull-up;
236				};
237
238				keypad@148 {
239					compatible = "qcom,pm8921-keypad";
240					reg = <0x148>;
241					interrupt-parent = <&pmicintc>;
242					interrupts = <74 1>, <75 1>;
243					debounce = <15>;
244					scan-delay = <32>;
245					row-hold = <91500>;
246				};
247
248				rtc@11d {
249					compatible = "qcom,pm8921-rtc";
250					interrupt-parent = <&pmicintc>;
251					interrupts = <39 1>;
252					reg = <0x11d>;
253					allow-set-time;
254				};
255			};
256		};
257
258		rng@1a500000 {
259			compatible = "qcom,prng";
260			reg = <0x1a500000 0x200>;
261			clocks = <&gcc PRNG_CLK>;
262			clock-names = "core";
263		};
264
265		amba {
266			compatible = "simple-bus";
267			#address-cells = <1>;
268			#size-cells = <1>;
269			ranges;
270			sdcc1: mmc@12400000 {
271				status		= "disabled";
272				compatible	= "arm,pl18x", "arm,primecell";
273				arm,primecell-periphid = <0x00051180>;
274				reg		= <0x12400000 0x8000>;
275				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
276				interrupt-names	= "cmd_irq";
277				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
278				clock-names	= "mclk", "apb_pclk";
279				bus-width	= <8>;
280				max-frequency	= <96000000>;
281				non-removable;
282				cap-sd-highspeed;
283				cap-mmc-highspeed;
284				vmmc-supply = <&vsdcc_fixed>;
285			};
286
287			sdcc3: mmc@12180000 {
288				compatible	= "arm,pl18x", "arm,primecell";
289				arm,primecell-periphid = <0x00051180>;
290				status		= "disabled";
291				reg		= <0x12180000 0x8000>;
292				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
293				interrupt-names	= "cmd_irq";
294				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
295				clock-names	= "mclk", "apb_pclk";
296				bus-width	= <4>;
297				cap-sd-highspeed;
298				cap-mmc-highspeed;
299				max-frequency	= <192000000>;
300				no-1-8-v;
301				vmmc-supply = <&vsdcc_fixed>;
302			};
303		};
304
305		tcsr: syscon@1a400000 {
306			compatible = "qcom,tcsr-msm8960", "syscon";
307			reg = <0x1a400000 0x100>;
308		};
309
310		gsbi@16000000 {
311			compatible = "qcom,gsbi-v1.0.0";
312			cell-index = <1>;
313			reg = <0x16000000 0x100>;
314			clocks = <&gcc GSBI1_H_CLK>;
315			clock-names = "iface";
316			#address-cells = <1>;
317			#size-cells = <1>;
318			ranges;
319
320			spi@16080000 {
321				compatible = "qcom,spi-qup-v1.1.1";
322				#address-cells = <1>;
323				#size-cells = <0>;
324				reg = <0x16080000 0x1000>;
325				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
326				spi-max-frequency = <24000000>;
327				cs-gpios = <&msmgpio 8 0>;
328
329				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
330				clock-names = "core", "iface";
331				status = "disabled";
332			};
333		};
334	};
335};
336