1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/qcom,gcc-msm8974.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/reset/qcom,gcc-msm8974.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16	interrupt-parent = <&intc>;
17
18	chosen { };
19
20	memory@0 {
21		device_type = "memory";
22		reg = <0x0 0x0>;
23	};
24
25	clocks {
26		xo_board: xo_board {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <19200000>;
30		};
31
32		sleep_clk: sleep_clk {
33			compatible = "fixed-clock";
34			#clock-cells = <0>;
35			clock-frequency = <32768>;
36		};
37	};
38
39	firmware {
40		scm {
41			compatible = "qcom,scm-msm8226", "qcom,scm";
42			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
43			clock-names = "core", "bus", "iface";
44		};
45	};
46
47	tcsr_mutex: hwlock {
48		compatible = "qcom,tcsr-mutex";
49		syscon = <&tcsr_mutex_block 0 0x80>;
50
51		#hwlock-cells = <1>;
52	};
53
54	reserved-memory {
55		#address-cells = <1>;
56		#size-cells = <1>;
57		ranges;
58
59		smem_region: smem@3000000 {
60			reg = <0x3000000 0x100000>;
61			no-map;
62		};
63	};
64
65	smd {
66		compatible = "qcom,smd";
67
68		rpm {
69			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
70			qcom,ipc = <&apcs 8 0>;
71			qcom,smd-edge = <15>;
72
73			rpm_requests: rpm-requests {
74				compatible = "qcom,rpm-msm8226";
75				qcom,smd-channels = "rpm_requests";
76
77				rpmpd: power-controller {
78					compatible = "qcom,msm8226-rpmpd";
79					#power-domain-cells = <1>;
80					operating-points-v2 = <&rpmpd_opp_table>;
81
82					rpmpd_opp_table: opp-table {
83						compatible = "operating-points-v2";
84
85						rpmpd_opp_ret: opp1 {
86							opp-level = <1>;
87						};
88						rpmpd_opp_svs_krait: opp2 {
89							opp-level = <2>;
90						};
91						rpmpd_opp_svs_soc: opp3 {
92							opp-level = <3>;
93						};
94						rpmpd_opp_nom: opp4 {
95							opp-level = <4>;
96						};
97						rpmpd_opp_turbo: opp5 {
98							opp-level = <5>;
99						};
100						rpmpd_opp_super_turbo: opp6 {
101							opp-level = <6>;
102						};
103					};
104				};
105			};
106		};
107	};
108
109	smem {
110		compatible = "qcom,smem";
111
112		memory-region = <&smem_region>;
113		qcom,rpm-msg-ram = <&rpm_msg_ram>;
114
115		hwlocks = <&tcsr_mutex 3>;
116	};
117
118	soc: soc {
119		compatible = "simple-bus";
120		#address-cells = <1>;
121		#size-cells = <1>;
122		ranges;
123
124		intc: interrupt-controller@f9000000 {
125			compatible = "qcom,msm-qgic2";
126			reg = <0xf9000000 0x1000>,
127			      <0xf9002000 0x1000>;
128			interrupt-controller;
129			#interrupt-cells = <3>;
130		};
131
132		apcs: syscon@f9011000 {
133			compatible = "syscon";
134			reg = <0xf9011000 0x1000>;
135		};
136
137		sdhc_1: sdhci@f9824900 {
138			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
139			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
140			reg-names = "hc_mem", "core_mem";
141			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
142				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
143			interrupt-names = "hc_irq", "pwr_irq";
144			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
145				 <&gcc GCC_SDCC1_AHB_CLK>,
146				 <&xo_board>;
147			clock-names = "core", "iface", "xo";
148			pinctrl-names = "default";
149			pinctrl-0 = <&sdhc1_default_state>;
150			status = "disabled";
151		};
152
153		sdhc_2: sdhci@f98a4900 {
154			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
155			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
156			reg-names = "hc_mem", "core_mem";
157			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
158				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
159			interrupt-names = "hc_irq", "pwr_irq";
160			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
161				 <&gcc GCC_SDCC2_AHB_CLK>,
162				 <&xo_board>;
163			clock-names = "core", "iface", "xo";
164			pinctrl-names = "default";
165			pinctrl-0 = <&sdhc2_default_state>;
166			status = "disabled";
167		};
168
169		sdhc_3: sdhci@f9864900 {
170			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
171			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
172			reg-names = "hc_mem", "core_mem";
173			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
174				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
175			interrupt-names = "hc_irq", "pwr_irq";
176			clocks = <&gcc GCC_SDCC3_APPS_CLK>,
177				 <&gcc GCC_SDCC3_AHB_CLK>,
178				 <&xo_board>;
179			clock-names = "core", "iface", "xo";
180			pinctrl-names = "default";
181			pinctrl-0 = <&sdhc3_default_state>;
182			status = "disabled";
183		};
184
185		blsp1_uart1: serial@f991d000 {
186			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
187			reg = <0xf991d000 0x1000>;
188			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
189			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
190			clock-names = "core", "iface";
191			status = "disabled";
192		};
193
194		blsp1_uart3: serial@f991f000 {
195			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
196			reg = <0xf991f000 0x1000>;
197			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
198			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
199			clock-names = "core", "iface";
200			status = "disabled";
201		};
202
203		blsp1_uart4: serial@f9920000 {
204			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
205			reg = <0xf9920000 0x1000>;
206			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
207			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
208			clock-names = "core", "iface";
209			status = "disabled";
210		};
211
212		blsp1_i2c1: i2c@f9923000 {
213			status = "disabled";
214			compatible = "qcom,i2c-qup-v2.1.1";
215			reg = <0xf9923000 0x1000>;
216			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
217			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
218			clock-names = "core", "iface";
219			pinctrl-names = "default";
220			pinctrl-0 = <&blsp1_i2c1_pins>;
221			#address-cells = <1>;
222			#size-cells = <0>;
223		};
224
225		blsp1_i2c2: i2c@f9924000 {
226			status = "disabled";
227			compatible = "qcom,i2c-qup-v2.1.1";
228			reg = <0xf9924000 0x1000>;
229			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
230			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
231			clock-names = "core", "iface";
232			pinctrl-names = "default";
233			pinctrl-0 = <&blsp1_i2c2_pins>;
234			#address-cells = <1>;
235			#size-cells = <0>;
236		};
237
238		blsp1_i2c3: i2c@f9925000 {
239			status = "disabled";
240			compatible = "qcom,i2c-qup-v2.1.1";
241			reg = <0xf9925000 0x1000>;
242			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
243			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
244			clock-names = "core", "iface";
245			pinctrl-names = "default";
246			pinctrl-0 = <&blsp1_i2c3_pins>;
247			#address-cells = <1>;
248			#size-cells = <0>;
249		};
250
251		blsp1_i2c4: i2c@f9926000 {
252			status = "disabled";
253			compatible = "qcom,i2c-qup-v2.1.1";
254			reg = <0xf9926000 0x1000>;
255			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
256			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
257			clock-names = "core", "iface";
258			pinctrl-names = "default";
259			pinctrl-0 = <&blsp1_i2c4_pins>;
260			#address-cells = <1>;
261			#size-cells = <0>;
262		};
263
264		blsp1_i2c5: i2c@f9927000 {
265			status = "disabled";
266			compatible = "qcom,i2c-qup-v2.1.1";
267			reg = <0xf9927000 0x1000>;
268			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
269			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
270			clock-names = "core", "iface";
271			pinctrl-names = "default";
272			pinctrl-0 = <&blsp1_i2c5_pins>;
273			#address-cells = <1>;
274			#size-cells = <0>;
275		};
276
277		usb: usb@f9a55000 {
278			compatible = "qcom,ci-hdrc";
279			reg = <0xf9a55000 0x200>,
280			      <0xf9a55200 0x200>;
281			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
282			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
283				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
284			clock-names = "iface", "core";
285			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
286			assigned-clock-rates = <75000000>;
287			resets = <&gcc GCC_USB_HS_BCR>;
288			reset-names = "core";
289			phy_type = "ulpi";
290			dr_mode = "otg";
291			hnp-disable;
292			srp-disable;
293			adp-disable;
294			ahb-burst-config = <0>;
295			phy-names = "usb-phy";
296			phys = <&usb_hs_phy>;
297			status = "disabled";
298			#reset-cells = <1>;
299
300			ulpi {
301				usb_hs_phy: phy {
302					compatible = "qcom,usb-hs-phy-msm8226",
303						     "qcom,usb-hs-phy";
304					#phy-cells = <0>;
305					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
306					clock-names = "ref", "sleep";
307					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
308					reset-names = "phy", "por";
309					qcom,init-seq = /bits/ 8 <0x0 0x44
310						0x1 0x68 0x2 0x24 0x3 0x13>;
311				};
312			};
313		};
314
315		gcc: clock-controller@fc400000 {
316			compatible = "qcom,gcc-msm8226";
317			reg = <0xfc400000 0x4000>;
318			#clock-cells = <1>;
319			#reset-cells = <1>;
320			#power-domain-cells = <1>;
321		};
322
323		tlmm: pinctrl@fd510000 {
324			compatible = "qcom,msm8226-pinctrl";
325			reg = <0xfd510000 0x4000>;
326			gpio-controller;
327			#gpio-cells = <2>;
328			gpio-ranges = <&tlmm 0 0 117>;
329			interrupt-controller;
330			#interrupt-cells = <2>;
331			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
332
333			blsp1_i2c1_pins: blsp1-i2c1 {
334				pins = "gpio2", "gpio3";
335				function = "blsp_i2c1";
336				drive-strength = <2>;
337				bias-disable;
338			};
339
340			blsp1_i2c2_pins: blsp1-i2c2 {
341				pins = "gpio6", "gpio7";
342				function = "blsp_i2c2";
343				drive-strength = <2>;
344				bias-disable;
345			};
346
347			blsp1_i2c3_pins: blsp1-i2c3 {
348				pins = "gpio10", "gpio11";
349				function = "blsp_i2c3";
350				drive-strength = <2>;
351				bias-disable;
352			};
353
354			blsp1_i2c4_pins: blsp1-i2c4 {
355				pins = "gpio14", "gpio15";
356				function = "blsp_i2c4";
357				drive-strength = <2>;
358				bias-disable;
359			};
360
361			blsp1_i2c5_pins: blsp1-i2c5 {
362				pins = "gpio18", "gpio19";
363				function = "blsp_i2c5";
364				drive-strength = <2>;
365				bias-disable;
366			};
367
368			sdhc1_default_state: sdhc1-default-state {
369				clk {
370					pins = "sdc1_clk";
371					drive-strength = <10>;
372					bias-disable;
373				};
374
375				cmd-data {
376					pins = "sdc1_cmd", "sdc1_data";
377					drive-strength = <10>;
378					bias-pull-up;
379				};
380			};
381
382			sdhc2_default_state: sdhc2-default-state {
383				clk {
384					pins = "sdc2_clk";
385					drive-strength = <10>;
386					bias-disable;
387				};
388
389				cmd-data {
390					pins = "sdc2_cmd", "sdc2_data";
391					drive-strength = <10>;
392					bias-pull-up;
393				};
394			};
395
396			sdhc3_default_state: sdhc3-default-state {
397				clk {
398					pins = "gpio44";
399					function = "sdc3";
400					drive-strength = <8>;
401					bias-disable;
402				};
403
404				cmd {
405					pins = "gpio43";
406					function = "sdc3";
407					drive-strength = <8>;
408					bias-pull-up;
409				};
410
411				data {
412					pins = "gpio39", "gpio40", "gpio41", "gpio42";
413					function = "sdc3";
414					drive-strength = <8>;
415					bias-pull-up;
416				};
417			};
418		};
419
420		restart@fc4ab000 {
421			compatible = "qcom,pshold";
422			reg = <0xfc4ab000 0x4>;
423		};
424
425		spmi_bus: spmi@fc4cf000 {
426			compatible = "qcom,spmi-pmic-arb";
427			reg-names = "core", "intr", "cnfg";
428			reg = <0xfc4cf000 0x1000>,
429			      <0xfc4cb000 0x1000>,
430			      <0xfc4ca000 0x1000>;
431			interrupt-names = "periph_irq";
432			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
433			qcom,ee = <0>;
434			qcom,channel = <0>;
435			#address-cells = <2>;
436			#size-cells = <0>;
437			interrupt-controller;
438			#interrupt-cells = <4>;
439		};
440
441		rng@f9bff000 {
442			compatible = "qcom,prng";
443			reg = <0xf9bff000 0x200>;
444			clocks = <&gcc GCC_PRNG_AHB_CLK>;
445			clock-names = "core";
446		};
447
448		timer@f9020000 {
449			compatible = "arm,armv7-timer-mem";
450			reg = <0xf9020000 0x1000>;
451			#address-cells = <1>;
452			#size-cells = <1>;
453			ranges;
454
455			frame@f9021000 {
456				frame-number = <0>;
457				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
458					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
459				reg = <0xf9021000 0x1000>,
460				      <0xf9022000 0x1000>;
461			};
462
463			frame@f9023000 {
464				frame-number = <1>;
465				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
466				reg = <0xf9023000 0x1000>;
467				status = "disabled";
468			};
469
470			frame@f9024000 {
471				frame-number = <2>;
472				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
473				reg = <0xf9024000 0x1000>;
474				status = "disabled";
475			};
476
477			frame@f9025000 {
478				frame-number = <3>;
479				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
480				reg = <0xf9025000 0x1000>;
481				status = "disabled";
482			};
483
484			frame@f9026000 {
485				frame-number = <4>;
486				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
487				reg = <0xf9026000 0x1000>;
488				status = "disabled";
489			};
490
491			frame@f9027000 {
492				frame-number = <5>;
493				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
494				reg = <0xf9027000 0x1000>;
495				status = "disabled";
496			};
497
498			frame@f9028000 {
499				frame-number = <6>;
500				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
501				reg = <0xf9028000 0x1000>;
502				status = "disabled";
503			};
504		};
505
506		rpm_msg_ram: memory@fc428000 {
507			compatible = "qcom,rpm-msg-ram";
508			reg = <0xfc428000 0x4000>;
509		};
510
511		tcsr_mutex_block: syscon@fd484000 {
512			compatible = "syscon";
513			reg = <0xfd484000 0x2000>;
514		};
515	};
516
517	timer {
518		compatible = "arm,armv7-timer";
519		interrupts = <GIC_PPI 2
520				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
521			     <GIC_PPI 3
522				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
523			     <GIC_PPI 4
524				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
525			     <GIC_PPI 1
526				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
527	};
528};
529