1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright (C) 2020 PHYTEC Messtechnik GmbH
4// Author: Jens Lang  <J.Lang@phytec.de>
5// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
6
7/dts-v1/;
8#include <dt-bindings/gpio/gpio.h>
9#include "imx7d.dtsi"
10
11/ {
12	model = "Storopack SMEGW01 board";
13	compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
14
15	aliases {
16		mmc0 = &usdhc1;
17		mmc1 = &usdhc3;
18		mmc2 = &usdhc2;
19		rtc0 = &i2c_rtc;
20		rtc1 = &snvs_rtc;
21	};
22
23	chosen {
24		stdout-path = &uart1;
25	};
26
27	memory@80000000 {
28		device_type = "memory";
29		reg = <0x80000000 0x20000000>;
30	};
31
32	reg_lte_on: regulator-lte-on {
33		compatible = "regulator-fixed";
34		pinctrl-names = "default";
35		pinctrl-0 = <&pinctrl_lte_on>;
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		regulator-name = "lte_on";
39		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41		regulator-always-on;
42	};
43
44	reg_lte_nreset: regulator-lte-nreset {
45		compatible = "regulator-fixed";
46		pinctrl-names = "default";
47		pinctrl-0 = <&pinctrl_lte_nreset>;
48		regulator-min-microvolt = <3300000>;
49		regulator-max-microvolt = <3300000>;
50		regulator-name = "LTE_nReset";
51		gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
52		enable-active-high;
53		regulator-always-on;
54	};
55
56	reg_wifi: regulator-wifi {
57		compatible = "regulator-fixed";
58		gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
59		enable-active-high;
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_wifi>;
62		regulator-name = "wifi_reg";
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65	};
66
67	reg_wlan_rfkill: regulator-wlan-rfkill {
68		compatible = "regulator-fixed";
69		pinctrl-names = "default";
70		pinctrl-2 = <&pinctrl_rfkill>;
71		regulator-min-microvolt = <3300000>;
72		regulator-max-microvolt = <3300000>;
73		regulator-name = "wlan_rfkill";
74		gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
75		enable-active-high;
76		regulator-always-on;
77	};
78
79	reg_usbotg_vbus: regulator-usbotg-vbus {
80		compatible = "regulator-fixed";
81		pinctrl-names = "default";
82		pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
83		regulator-name = "usb_otg_vbus";
84		regulator-min-microvolt = <5000000>;
85		regulator-max-microvolt = <5000000>;
86		gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
87		enable-active-high;
88	};
89};
90
91&ecspi1 {
92	pinctrl-names = "default";
93	pinctrl-0 = <&pinctrl_ecspi1>;
94	cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
95	status = "okay";
96
97	sram@0 {
98		compatible = "microchip,48l640";
99		reg = <0>;
100		#address-cells = <1>;
101		#size-cells = <1>;
102		spi-max-frequency = <16000000>;
103	};
104};
105
106&fec1 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_enet1>;
109	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
110			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
111	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
112	assigned-clock-rates = <0>, <100000000>;
113	phy-mode = "rgmii-id";
114	phy-handle = <&ethphy0>;
115	fsl,magic-packet;
116	status = "okay";
117
118	mdio: mdio {
119		#address-cells = <1>;
120		#size-cells = <0>;
121
122		ethphy0: ethernet-phy@1 {
123			compatible = "ethernet-phy-id0022.1622",
124				     "ethernet-phy-ieee802.3-c22";
125			reg = <1>;
126			reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
127		};
128
129		ethphy1: ethernet-phy@2 {
130			compatible = "ethernet-phy-id0022.1622",
131				     "ethernet-phy-ieee802.3-c22";
132			reg = <2>;
133		};
134	};
135};
136
137&fec2 {
138	pinctrl-names = "default";
139	pinctrl-0 = <&pinctrl_enet2>;
140	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
141			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
142	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
143	assigned-clock-rates = <0>, <100000000>;
144	phy-mode = "rgmii-id";
145	phy-handle = <&ethphy1>;
146	fsl,magic-packet;
147	status = "okay";
148};
149
150&i2c2 {
151	pinctrl-names = "default";
152	pinctrl-0 =<&pinctrl_i2c2>;
153	clock-frequency = <100000>;
154	status = "okay";
155
156	i2c_rtc: rtc@52 {
157		compatible = "microcrystal,rv3028";
158		pinctrl-names = "default";
159		pinctrl-0 = <&pinctrl_rtc_int>;
160		reg = <0x52>;
161		interrupt-parent = <&gpio2>;
162		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
163	};
164};
165
166&flexcan1 {
167	pinctrl-names = "default";
168	pinctrl-0 = <&pinctrl_flexcan1>;
169	status = "okay";
170};
171
172&flexcan2 {
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_flexcan2>;
175	status = "okay";
176};
177
178&uart1 {
179	pinctrl-names = "default";
180	pinctrl-0 = <&pinctrl_uart1>;
181	status = "okay";
182};
183
184&uart3 {
185	pinctrl-names = "default";
186	pinctrl-0 = <&pinctrl_uart3>;
187	status = "okay";
188};
189
190&usbotg1 {
191	pinctrl-names = "default";
192	pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
193	dr_mode = "otg";
194	vbus-supply = <&reg_usbotg_vbus>;
195	status = "okay";
196};
197
198&usbotg2 {
199	pinctrl-names = "default";
200	pinctrl-0 = <&pinctrl_usbotg2>;
201	dr_mode = "host";
202	status = "okay";
203};
204
205&usdhc1 {
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_usdhc1>;
208	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
209	no-1-8-v;
210	enable-sdio-wakeup;
211	keep-power-in-suspend;
212	status = "okay";
213};
214
215&usdhc2 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_usdhc2>;
218	bus-width = <4>;
219	no-1-8-v;
220	non-removable;
221	vmmc-supply = <&reg_wifi>;
222	enable-sdio-wakeup;
223	status = "okay";
224};
225
226&usdhc3 {
227	pinctrl-names = "default", "state_100mhz", "state_200mhz";
228	pinctrl-0 = <&pinctrl_usdhc3>;
229	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
230	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
231	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
232	assigned-clock-rates = <400000000>;
233	max-frequency = <200000000>;
234	bus-width = <8>;
235	fsl,tuning-step = <1>;
236	non-removable;
237	cap-mmc-highspeed;
238	cap-mmc-hw-reset;
239	mmc-hs200-1_8v;
240	mmc-ddr-1_8v;
241	status = "okay";
242};
243
244&wdog1 {
245	pinctrl-names = "default";
246	pinctrl-0 = <&pinctrl_wdog>;
247	fsl,ext-reset-output;
248	status = "okay";
249};
250
251&iomuxc {
252	pinctrl_ecspi1: ecspi1grp {
253		fsl,pins = <
254			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19	0x04
255			MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x04
256			MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x04
257			MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO	0x04
258		>;
259	};
260
261	pinctrl_enet1: enet1grp {
262		fsl,pins = <
263			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
264			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x5
265			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x5
266			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x5
267			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x5
268			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x5
269			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
270			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x5
271			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x5
272			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x5
273			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x5
274			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x5
275			MX7D_PAD_GPIO1_IO10__ENET1_MDIO		0x7
276			MX7D_PAD_GPIO1_IO11__ENET1_MDC		0x7
277		>;
278	};
279
280	pinctrl_enet2: enet2grp {
281		fsl,pins = <
282			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
283			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC	0x5
284			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0	0x5
285			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1	0x5
286			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2	0x5
287			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3	0x5
288			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0	0x5
289			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1	0x5
290			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2	0x5
291			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3	0x5
292			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
293			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC	0x5
294			MX7D_PAD_GPIO1_IO09__GPIO1_IO9	0x08
295		>;
296	};
297
298	pinctrl_i2c2: i2c2grp {
299		fsl,pins = <
300			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x40000004
301			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x40000004
302		>;
303	};
304
305	pinctrl_flexcan1: flexcan1grp {
306		fsl,pins = <
307			MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x0b0b0
308			MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x0b0b0
309		>;
310	};
311
312	pinctrl_flexcan2: flexcan2grp {
313		fsl,pins = <
314			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x0b0b0
315			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x0b0b0
316		>;
317	};
318
319	pinctrl_lte_on: lteongrp {
320		fsl,pins = <
321			MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12	0x17059
322		>;
323	};
324
325	pinctrl_lte_nreset: ltenresetgrp {
326		fsl,pins = <
327			MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21	0x17059
328		>;
329	};
330
331	pinctrl_rfkill: rfkillrp {
332		fsl,pins = <
333			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x17059
334		>;
335	};
336
337	pinctrl_rtc_int: rtcintgrp {
338		fsl,pins = <
339			MX7D_PAD_EPDC_DATA15__GPIO2_IO15	0x17059
340		>;
341	};
342
343	pinctrl_uart1: uart1grp {
344		fsl,pins = <
345			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x74
346			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x7c
347		>;
348	};
349
350	pinctrl_uart3: uart3grp {
351		fsl,pins = <
352			MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x7c
353			MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x74
354		>;
355	};
356
357	pinctrl_usbotg1_lpsr: usbotg1 {
358		fsl,pins = <
359			MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC	0x04
360		>;
361	};
362
363	pinctrl_usbotg1_pwr: usbotg1-pwr {
364		fsl,pins = <
365			MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR	0x04
366		>;
367	};
368
369	pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio {
370		fsl,pins = <
371			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x04
372		>;
373	};
374
375	pinctrl_usbotg2: usbotg2grp {
376		fsl,pins = <
377			MX7D_PAD_UART3_RTS_B__USB_OTG2_OC	0x04
378		>;
379	};
380
381	pinctrl_usdhc1: usdhc1grp {
382		fsl,pins = <
383			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59
384			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
385			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
386			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
387			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
388			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
389			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
390		>;
391	};
392
393	pinctrl_usdhc2: usdhc2grp {
394		fsl,pins = <
395			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
396			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
397			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
398			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
399			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
400			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
401			MX7D_PAD_SD2_CD_B__SD2_CD_B		0x08
402		>;
403	};
404
405	pinctrl_usdhc3: usdhc3grp {
406		fsl,pins = <
407			MX7D_PAD_SD3_CMD__SD3_CMD		0x5d
408			MX7D_PAD_SD3_CLK__SD3_CLK		0x1d
409			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5d
410			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5d
411			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5d
412			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5d
413			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5d
414			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5d
415			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5d
416			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5d
417			MX7D_PAD_SD3_STROBE__SD3_STROBE	0x1d
418		>;
419	};
420
421	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
422		fsl,pins = <
423			MX7D_PAD_SD3_CMD__SD3_CMD		0x5e
424			MX7D_PAD_SD3_CLK__SD3_CLK		0x1e
425			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5e
426			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5e
427			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5e
428			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5e
429			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5e
430			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5e
431			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5e
432			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5e
433			MX7D_PAD_SD3_STROBE__SD3_STROBE	0x1e
434		>;
435	};
436
437	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
438		fsl,pins = <
439			MX7D_PAD_SD3_CMD__SD3_CMD		0x5f
440			MX7D_PAD_SD3_CLK__SD3_CLK		0x0f
441			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5f
442			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5f
443			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5f
444			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5f
445			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5f
446			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5f
447			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5f
448			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5f
449			MX7D_PAD_SD3_STROBE__SD3_STROBE	0x1f
450		>;
451	};
452
453	pinctrl_wifi: wifigrp {
454		fsl,pins = <
455			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x04
456			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x04
457		>;
458	};
459};
460
461&iomuxc_lpsr {
462	pinctrl_wdog: wdoggrp {
463		fsl,pins = <
464			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
465		>;
466	};
467};
468