1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7/ {
8	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
9	compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
10
11	aliases {
12		rtc0 = &i2c_rtc;
13		rtc1 = &snvs_rtc;
14	};
15
16	reg_sound_1v8: regulator-1v8 {
17		compatible = "regulator-fixed";
18		regulator-name = "i2s-audio-1v8";
19		regulator-min-microvolt = <1800000>;
20		regulator-max-microvolt = <1800000>;
21		status = "disabled";
22	};
23
24	reg_sound_3v3: regulator-3v3 {
25		compatible = "regulator-fixed";
26		regulator-name = "i2s-audio-3v3";
27		regulator-min-microvolt = <3300000>;
28		regulator-max-microvolt = <3300000>;
29		status = "disabled";
30	};
31
32	reg_can1_en: regulator-can1 {
33		compatible = "regulator-fixed";
34		pinctrl-names = "default";
35		pinctrl-0 = <&princtrl_flexcan1_en>;
36		regulator-name = "Can";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41		status = "disabled";
42	};
43
44	reg_adc1_vref_3v3: regulator-vref-3v3 {
45		compatible = "regulator-fixed";
46		regulator-name = "vref-3v3";
47		regulator-min-microvolt = <3300000>;
48		regulator-max-microvolt = <3300000>;
49	};
50
51	sound: sound {
52		compatible = "simple-audio-card";
53		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
54		simple-audio-card,format = "i2s";
55		simple-audio-card,bitclock-master = <&dailink_master>;
56		simple-audio-card,frame-master = <&dailink_master>;
57		simple-audio-card,widgets =
58			"Line", "Line In",
59			"Line", "Line Out",
60			"Speaker", "Speaker";
61		simple-audio-card,routing =
62			"Line Out", "LLOUT",
63			"Line Out", "RLOUT",
64			"Speaker", "SPOP",
65			"Speaker", "SPOM",
66			"LINE1L", "Line In",
67			"LINE1R", "Line In";
68		status = "disabled";
69
70		simple-audio-card,cpu {
71			sound-dai = <&sai2>;
72		};
73
74		dailink_master: simple-audio-card,codec {
75			sound-dai = <&tlv320>;
76			clocks = <&clks IMX6UL_CLK_SAI2>;
77		};
78	};
79
80};
81
82&adc1 {
83	pinctrl-names = "default";
84	pinctrl-0 = <&pinctrl_adc1>;
85	vref-supply = <&reg_adc1_vref_3v3>;
86	/*
87	 * driver can not separate a specific channel so we request 4 channels
88	 * here - we need only the fourth channel
89	 */
90	num-channels = <4>;
91	status = "disabled";
92};
93
94&can1 {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_flexcan1>;
97	xceiver-supply = <&reg_can1_en>;
98	status = "disabled";
99};
100
101&clks {
102	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
103	assigned-clock-rates = <786432000>;
104};
105
106&ecspi3 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_ecspi3>;
109	cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
110	status = "disabled";
111};
112
113&fec2 {
114	pinctrl-names = "default";
115	pinctrl-0 = <&pinctrl_enet2>;
116	phy-mode = "rmii";
117	phy-handle = <&ethphy2>;
118	status = "disabled";
119};
120
121&i2c1 {
122	tlv320: codec@18 {
123		compatible = "ti,tlv320aic3007";
124		#sound-dai-cells = <0>;
125		reg = <0x18>;
126		AVDD-supply = <&reg_sound_3v3>;
127		IOVDD-supply = <&reg_sound_3v3>;
128		DRVDD-supply = <&reg_sound_3v3>;
129		DVDD-supply = <&reg_sound_1v8>;
130		status = "disabled";
131	};
132
133	i2c_rtc: rtc@68 {
134		pinctrl-names = "default";
135		pinctrl-0 = <&pinctrl_rtc_int>;
136		compatible = "microcrystal,rv4162";
137		reg = <0x68>;
138		interrupt-parent = <&gpio5>;
139		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
140		status = "disabled";
141	};
142};
143
144&mdio {
145	ethphy2: ethernet-phy@2 {
146		reg = <2>;
147		micrel,led-mode = <1>;
148		clocks = <&clks IMX6UL_CLK_ENET2_REF>;
149		clock-names = "rmii-ref";
150		status = "disabled";
151	};
152};
153
154&sai2 {
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_sai2>;
157	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
158			<&clks IMX6UL_CLK_SAI2>;
159	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
160	assigned-clock-rates = <0>, <19200000>;
161	fsl,sai-mclk-direction-output;
162	status = "disabled";
163};
164
165&uart5 {
166	pinctrl-names = "default";
167	pinctrl-0 = <&pinctrl_uart5>;
168	uart-has-rtscts;
169	status = "disabled";
170};
171
172&usbotg1 {
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_usb_otg1_id>;
175	dr_mode = "otg";
176	status = "disabled";
177};
178
179&usbotg2 {
180	dr_mode = "host";
181	disable-over-current;
182	status = "disabled";
183};
184
185&usdhc1 {
186	pinctrl-names = "default", "state_100mhz", "state_200mhz";
187	pinctrl-0 = <&pinctrl_usdhc1>;
188	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
189	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
190	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
191	no-1-8-v;
192	keep-power-in-suspend;
193	wakeup-source;
194	disable-wp;
195	status = "disabled";
196};
197
198&iomuxc {
199	pinctrl_adc1: adc1grp {
200		fsl,pins = <
201			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
202		>;
203	};
204
205	pinctrl_ecspi3: ecspi3grp {
206		fsl,pins = <
207			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
208			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
209			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
210			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0
211		>;
212	};
213
214	pinctrl_enet2: enet2grp {
215		fsl,pins = <
216			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
217			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
218			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
219			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
220			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b010
221			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b010
222			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b010
223			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b010
224		>;
225	};
226
227	pinctrl_flexcan1: flexcan1 {
228		fsl,pins = <
229			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
230			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
231		>;
232	};
233
234	princtrl_flexcan1_en: flexcan1engrp {
235		fsl,pins = <
236			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
237		>;
238	};
239
240	pinctrl_rtc_int: rtcintgrp {
241		fsl,pins = <
242			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
243		>;
244	};
245
246	pinctrl_sai2: sai2grp {
247		fsl,pins = <
248			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
249			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
250			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
251			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
252			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
253		>;
254	};
255
256	pinctrl_uart5: uart5grp {
257		fsl,pins = <
258			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
259			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
260			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
261			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
262		>;
263	};
264
265	pinctrl_usb_otg1_id: usbotg1idgrp {
266		fsl,pins = <
267			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
268		>;
269	};
270
271	pinctrl_usdhc1: usdhc1grp {
272		fsl,pins = <
273			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
274			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
275			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
276			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
277			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
278			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
279			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
280		>;
281	};
282
283	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
284		fsl,pins = <
285			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
286			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
287			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
288			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
289			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
290			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
291		>;
292	};
293
294	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
295		fsl,pins = <
296			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
297			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
298			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
299			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
300			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
301			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
302		>;
303	};
304};
305