1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright 2014-2020 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 model = "Toradex Apalis iMX6Q/D Module"; 12 compatible = "toradex,apalis_imx6q", "fsl,imx6q"; 13 14 /* Will be filled by the bootloader */ 15 memory@10000000 { 16 device_type = "memory"; 17 reg = <0x10000000 0>; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&pinctrl_gpio_bl_on>; 24 pwms = <&pwm4 0 5000000>; 25 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 26 status = "disabled"; 27 }; 28 29 reg_module_3v3: regulator-module-3v3 { 30 compatible = "regulator-fixed"; 31 regulator-name = "+V3.3"; 32 regulator-min-microvolt = <3300000>; 33 regulator-max-microvolt = <3300000>; 34 regulator-always-on; 35 }; 36 37 reg_module_3v3_audio: regulator-module-3v3-audio { 38 compatible = "regulator-fixed"; 39 regulator-name = "+V3.3_AUDIO"; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 regulator-always-on; 43 }; 44 45 reg_usb_otg_vbus: regulator-usb-otg-vbus { 46 compatible = "regulator-fixed"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; 49 regulator-name = "usb_otg_vbus"; 50 regulator-min-microvolt = <5000000>; 51 regulator-max-microvolt = <5000000>; 52 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 53 enable-active-high; 54 status = "disabled"; 55 }; 56 57 /* on module USB hub */ 58 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { 59 compatible = "regulator-fixed"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; 62 regulator-name = "usb_host_vbus_hub"; 63 regulator-min-microvolt = <5000000>; 64 regulator-max-microvolt = <5000000>; 65 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; 66 startup-delay-us = <2000>; 67 enable-active-high; 68 status = "okay"; 69 }; 70 71 reg_usb_host_vbus: regulator-usb-host-vbus { 72 compatible = "regulator-fixed"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 75 regulator-name = "usb_host_vbus"; 76 regulator-min-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>; 78 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 vin-supply = <®_usb_host_vbus_hub>; 81 status = "disabled"; 82 }; 83 84 sound { 85 compatible = "fsl,imx-audio-sgtl5000"; 86 model = "imx6q-apalis-sgtl5000"; 87 ssi-controller = <&ssi1>; 88 audio-codec = <&codec>; 89 audio-routing = 90 "LINE_IN", "Line In Jack", 91 "MIC_IN", "Mic Jack", 92 "Mic Jack", "Mic Bias", 93 "Headphone Jack", "HP_OUT"; 94 mux-int-port = <1>; 95 mux-ext-port = <4>; 96 }; 97 98 sound_spdif: sound-spdif { 99 compatible = "fsl,imx-audio-spdif"; 100 model = "imx-spdif"; 101 spdif-controller = <&spdif>; 102 spdif-in; 103 spdif-out; 104 status = "disabled"; 105 }; 106}; 107 108&audmux { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_audmux>; 111 status = "okay"; 112}; 113 114&can1 { 115 pinctrl-names = "default", "sleep"; 116 pinctrl-0 = <&pinctrl_flexcan1_default>; 117 pinctrl-1 = <&pinctrl_flexcan1_sleep>; 118 status = "disabled"; 119}; 120 121&can2 { 122 pinctrl-names = "default", "sleep"; 123 pinctrl-0 = <&pinctrl_flexcan2_default>; 124 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 125 status = "disabled"; 126}; 127 128/* Apalis SPI1 */ 129&ecspi1 { 130 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_ecspi1>; 133 status = "disabled"; 134}; 135 136/* Apalis SPI2 */ 137&ecspi2 { 138 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_ecspi2>; 141 status = "disabled"; 142}; 143 144&fec { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_enet>; 147 phy-mode = "rgmii-id"; 148 phy-handle = <ðphy>; 149 phy-reset-duration = <10>; 150 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 151 status = "okay"; 152 153 mdio { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 ethphy: ethernet-phy@7 { 158 interrupt-parent = <&gpio1>; 159 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 160 reg = <7>; 161 }; 162 }; 163}; 164 165&hdmi { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; 168 status = "disabled"; 169}; 170 171/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ 172&i2c1 { 173 clock-frequency = <100000>; 174 pinctrl-names = "default", "gpio"; 175 pinctrl-0 = <&pinctrl_i2c1>; 176 pinctrl-1 = <&pinctrl_i2c1_gpio>; 177 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 178 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 179 status = "disabled"; 180}; 181 182/* 183 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 184 * touch screen controller 185 */ 186&i2c2 { 187 clock-frequency = <100000>; 188 pinctrl-names = "default", "gpio"; 189 pinctrl-0 = <&pinctrl_i2c2>; 190 pinctrl-1 = <&pinctrl_i2c2_gpio>; 191 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 192 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 193 status = "okay"; 194 195 pmic: pfuze100@8 { 196 compatible = "fsl,pfuze100"; 197 reg = <0x08>; 198 199 regulators { 200 sw1a_reg: sw1ab { 201 regulator-min-microvolt = <300000>; 202 regulator-max-microvolt = <1875000>; 203 regulator-boot-on; 204 regulator-always-on; 205 regulator-ramp-delay = <6250>; 206 }; 207 208 sw1c_reg: sw1c { 209 regulator-min-microvolt = <300000>; 210 regulator-max-microvolt = <1875000>; 211 regulator-boot-on; 212 regulator-always-on; 213 regulator-ramp-delay = <6250>; 214 }; 215 216 sw3a_reg: sw3a { 217 regulator-min-microvolt = <400000>; 218 regulator-max-microvolt = <1975000>; 219 regulator-boot-on; 220 regulator-always-on; 221 }; 222 223 swbst_reg: swbst { 224 regulator-min-microvolt = <5000000>; 225 regulator-max-microvolt = <5150000>; 226 regulator-boot-on; 227 regulator-always-on; 228 }; 229 230 snvs_reg: vsnvs { 231 regulator-min-microvolt = <1000000>; 232 regulator-max-microvolt = <3000000>; 233 regulator-boot-on; 234 regulator-always-on; 235 }; 236 237 vref_reg: vrefddr { 238 regulator-boot-on; 239 regulator-always-on; 240 }; 241 242 vgen1_reg: vgen1 { 243 regulator-min-microvolt = <800000>; 244 regulator-max-microvolt = <1550000>; 245 regulator-boot-on; 246 regulator-always-on; 247 }; 248 249 vgen2_reg: vgen2 { 250 regulator-min-microvolt = <800000>; 251 regulator-max-microvolt = <1550000>; 252 regulator-boot-on; 253 regulator-always-on; 254 }; 255 256 vgen3_reg: vgen3 { 257 regulator-min-microvolt = <1800000>; 258 regulator-max-microvolt = <3300000>; 259 regulator-boot-on; 260 regulator-always-on; 261 }; 262 263 vgen4_reg: vgen4 { 264 regulator-min-microvolt = <1800000>; 265 regulator-max-microvolt = <1800000>; 266 regulator-boot-on; 267 regulator-always-on; 268 }; 269 270 vgen5_reg: vgen5 { 271 regulator-min-microvolt = <1800000>; 272 regulator-max-microvolt = <3300000>; 273 regulator-boot-on; 274 regulator-always-on; 275 }; 276 277 vgen6_reg: vgen6 { 278 regulator-min-microvolt = <1800000>; 279 regulator-max-microvolt = <3300000>; 280 regulator-boot-on; 281 regulator-always-on; 282 }; 283 }; 284 }; 285 286 codec: sgtl5000@a { 287 compatible = "fsl,sgtl5000"; 288 reg = <0x0a>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_sgtl5000>; 291 clocks = <&clks IMX6QDL_CLK_CKO>; 292 VDDA-supply = <®_module_3v3_audio>; 293 VDDIO-supply = <®_module_3v3>; 294 VDDD-supply = <&vgen4_reg>; 295 }; 296 297 /* STMPE811 touch screen controller */ 298 stmpe811@41 { 299 compatible = "st,stmpe811"; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_touch_int>; 302 reg = <0x41>; 303 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 304 interrupt-parent = <&gpio4>; 305 interrupt-controller; 306 id = <0>; 307 blocks = <0x5>; 308 irq-trigger = <0x1>; 309 /* 3.25 MHz ADC clock speed */ 310 st,adc-freq = <1>; 311 /* 12-bit ADC */ 312 st,mod-12b = <1>; 313 /* internal ADC reference */ 314 st,ref-sel = <0>; 315 /* ADC conversion time: 80 clocks */ 316 st,sample-time = <4>; 317 318 stmpe_touchscreen: stmpe_touchscreen { 319 compatible = "st,stmpe-ts"; 320 /* 8 sample average control */ 321 st,ave-ctrl = <3>; 322 /* 7 length fractional part in z */ 323 st,fraction-z = <7>; 324 /* 325 * 50 mA typical 80 mA max touchscreen drivers 326 * current limit value 327 */ 328 st,i-drive = <1>; 329 /* 1 ms panel driver settling time */ 330 st,settling = <3>; 331 /* 5 ms touch detect interrupt delay */ 332 st,touch-det-delay = <5>; 333 }; 334 335 stmpe_adc: stmpe_adc { 336 compatible = "st,stmpe-adc"; 337 /* forbid to use ADC channels 3-0 (touch) */ 338 st,norequest-mask = <0x0F>; 339 #io-channel-cells = <1>; 340 }; 341 }; 342}; 343 344/* 345 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier 346 * board) 347 */ 348&i2c3 { 349 clock-frequency = <100000>; 350 pinctrl-names = "default", "gpio"; 351 pinctrl-0 = <&pinctrl_i2c3>; 352 pinctrl-1 = <&pinctrl_i2c3_gpio>; 353 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 354 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 355 status = "disabled"; 356}; 357 358&pwm1 { 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_pwm1>; 361 status = "disabled"; 362}; 363 364&pwm2 { 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_pwm2>; 367 status = "disabled"; 368}; 369 370&pwm3 { 371 pinctrl-names = "default"; 372 pinctrl-0 = <&pinctrl_pwm3>; 373 status = "disabled"; 374}; 375 376&pwm4 { 377 #pwm-cells = <2>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_pwm4>; 380 status = "disabled"; 381}; 382 383&spdif { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_spdif>; 386 status = "disabled"; 387}; 388 389&ssi1 { 390 status = "okay"; 391}; 392 393&uart1 { 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 396 fsl,dte-mode; 397 uart-has-rtscts; 398 status = "disabled"; 399}; 400 401&uart2 { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_uart2_dte>; 404 fsl,dte-mode; 405 uart-has-rtscts; 406 status = "disabled"; 407}; 408 409&uart4 { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_uart4_dte>; 412 fsl,dte-mode; 413 status = "disabled"; 414}; 415 416&uart5 { 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pinctrl_uart5_dte>; 419 fsl,dte-mode; 420 status = "disabled"; 421}; 422 423&usbotg { 424 pinctrl-names = "default"; 425 pinctrl-0 = <&pinctrl_usbotg>; 426 disable-over-current; 427 status = "disabled"; 428}; 429 430/* MMC1 */ 431&usdhc1 { 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; 434 vqmmc-supply = <®_module_3v3>; 435 bus-width = <8>; 436 disable-wp; 437 no-1-8-v; 438 status = "disabled"; 439}; 440 441/* SD1 */ 442&usdhc2 { 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pinctrl_usdhc2>; 445 vqmmc-supply = <®_module_3v3>; 446 bus-width = <4>; 447 disable-wp; 448 no-1-8-v; 449 status = "disabled"; 450}; 451 452/* eMMC */ 453&usdhc3 { 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pinctrl_usdhc3>; 456 vqmmc-supply = <®_module_3v3>; 457 bus-width = <8>; 458 no-1-8-v; 459 non-removable; 460 status = "okay"; 461}; 462 463&weim { 464 status = "disabled"; 465}; 466 467&iomuxc { 468 pinctrl_apalis_gpio1: gpio2io04grp { 469 fsl,pins = < 470 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 471 >; 472 }; 473 474 pinctrl_apalis_gpio2: gpio2io05grp { 475 fsl,pins = < 476 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 477 >; 478 }; 479 480 pinctrl_apalis_gpio3: gpio2io06grp { 481 fsl,pins = < 482 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 483 >; 484 }; 485 486 pinctrl_apalis_gpio4: gpio2io07grp { 487 fsl,pins = < 488 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 489 >; 490 }; 491 492 pinctrl_apalis_gpio5: gpio6io10grp { 493 fsl,pins = < 494 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 495 >; 496 }; 497 498 pinctrl_apalis_gpio6: gpio6io09grp { 499 fsl,pins = < 500 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 501 >; 502 }; 503 504 pinctrl_apalis_gpio7: gpio1io02grp { 505 fsl,pins = < 506 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 507 >; 508 }; 509 510 pinctrl_apalis_gpio8: gpio1io06grp { 511 fsl,pins = < 512 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 513 >; 514 }; 515 516 pinctrl_audmux: audmuxgrp { 517 fsl,pins = < 518 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 519 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 520 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 521 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 522 >; 523 }; 524 525 pinctrl_cam_mclk: cammclkgrp { 526 fsl,pins = < 527 /* CAM sys_mclk */ 528 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 529 >; 530 }; 531 532 pinctrl_ecspi1: ecspi1grp { 533 fsl,pins = < 534 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 535 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 536 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 537 /* SPI1 cs */ 538 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 539 >; 540 }; 541 542 pinctrl_ecspi2: ecspi2grp { 543 fsl,pins = < 544 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 545 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 546 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 547 /* SPI2 cs */ 548 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 549 >; 550 }; 551 552 pinctrl_enet: enetgrp { 553 fsl,pins = < 554 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 555 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 556 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 557 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 558 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 559 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 560 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 561 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 562 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 563 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 564 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 565 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 566 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 567 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 568 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 569 /* Ethernet PHY reset */ 570 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 571 /* Ethernet PHY interrupt */ 572 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 573 >; 574 }; 575 576 pinctrl_flexcan1_default: flexcan1defgrp { 577 fsl,pins = < 578 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 579 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 580 >; 581 }; 582 583 pinctrl_flexcan1_sleep: flexcan1slpgrp { 584 fsl,pins = < 585 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 586 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 587 >; 588 }; 589 590 pinctrl_flexcan2_default: flexcan2defgrp { 591 fsl,pins = < 592 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 593 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 594 >; 595 }; 596 pinctrl_flexcan2_sleep: flexcan2slpgrp { 597 fsl,pins = < 598 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 599 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 600 >; 601 }; 602 603 pinctrl_gpio_bl_on: gpioblon { 604 fsl,pins = < 605 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 606 >; 607 }; 608 609 pinctrl_gpio_keys: gpio1io04grp { 610 fsl,pins = < 611 /* Power button */ 612 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 613 >; 614 }; 615 616 pinctrl_hdmi_cec: hdmicecgrp { 617 fsl,pins = < 618 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 619 >; 620 }; 621 622 pinctrl_hdmi_ddc: hdmiddcgrp { 623 fsl,pins = < 624 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 625 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 626 >; 627 }; 628 629 pinctrl_i2c1: i2c1grp { 630 fsl,pins = < 631 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 632 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 633 >; 634 }; 635 636 pinctrl_i2c1_gpio: i2c1gpiogrp { 637 fsl,pins = < 638 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 639 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 640 >; 641 }; 642 643 pinctrl_i2c2: i2c2grp { 644 fsl,pins = < 645 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 646 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 647 >; 648 }; 649 650 pinctrl_i2c2_gpio: i2c2gpiogrp { 651 fsl,pins = < 652 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 653 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 654 >; 655 }; 656 657 pinctrl_i2c3: i2c3grp { 658 fsl,pins = < 659 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 660 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 661 >; 662 }; 663 664 pinctrl_i2c3_gpio: i2c3gpiogrp { 665 fsl,pins = < 666 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 667 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 668 >; 669 }; 670 671 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ 672 fsl,pins = < 673 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 674 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 675 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 676 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 677 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 678 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 679 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 680 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 681 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 682 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 683 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 684 >; 685 }; 686 687 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 688 fsl,pins = < 689 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 690 /* DE */ 691 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 692 /* HSync */ 693 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 694 /* VSync */ 695 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 696 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 697 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 698 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 699 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 700 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 701 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 702 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 703 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 704 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 705 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 706 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 707 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 708 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 709 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 710 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 711 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 712 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 713 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 714 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 715 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 716 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 717 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 718 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 719 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 720 >; 721 }; 722 723 pinctrl_ipu2_vdac: ipu2vdacgrp { 724 fsl,pins = < 725 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 726 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 727 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 728 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 729 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 730 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 731 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 732 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 733 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 734 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 735 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 736 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 737 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 738 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 739 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 740 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 741 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 742 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 743 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 744 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 745 >; 746 }; 747 748 pinctrl_mmc_cd: gpiommccdgrp { 749 fsl,pins = < 750 /* MMC1 CD */ 751 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 752 >; 753 }; 754 755 pinctrl_pwm1: pwm1grp { 756 fsl,pins = < 757 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 758 >; 759 }; 760 761 pinctrl_pwm2: pwm2grp { 762 fsl,pins = < 763 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 764 >; 765 }; 766 767 pinctrl_pwm3: pwm3grp { 768 fsl,pins = < 769 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 770 >; 771 }; 772 773 pinctrl_pwm4: pwm4grp { 774 fsl,pins = < 775 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 776 >; 777 }; 778 779 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 780 fsl,pins = < 781 /* USBH_EN */ 782 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 783 >; 784 }; 785 786 pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { 787 fsl,pins = < 788 /* USBH_HUB_EN */ 789 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 790 >; 791 }; 792 793 pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { 794 fsl,pins = < 795 /* USBO1 power en */ 796 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 797 >; 798 }; 799 800 pinctrl_reset_moci: gpioresetmocigrp { 801 fsl,pins = < 802 /* RESET_MOCI control */ 803 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 804 >; 805 }; 806 807 pinctrl_sd_cd: gpiosdcdgrp { 808 fsl,pins = < 809 /* SD1 CD */ 810 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 811 >; 812 }; 813 814 pinctrl_sgtl5000: sgtl5000grp { 815 fsl,pins = < 816 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 817 >; 818 }; 819 820 pinctrl_spdif: spdifgrp { 821 fsl,pins = < 822 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 823 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 824 >; 825 }; 826 827 pinctrl_touch_int: gpiotouchintgrp { 828 fsl,pins = < 829 /* STMPE811 interrupt */ 830 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 831 >; 832 }; 833 834 pinctrl_uart1_dce: uart1dcegrp { 835 fsl,pins = < 836 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 837 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 838 >; 839 }; 840 841 /* DTE mode */ 842 pinctrl_uart1_dte: uart1dtegrp { 843 fsl,pins = < 844 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 845 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 846 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 847 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 848 >; 849 }; 850 851 /* Additional DTR, DSR, DCD */ 852 pinctrl_uart1_ctrl: uart1ctrlgrp { 853 fsl,pins = < 854 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 855 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 856 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 857 >; 858 }; 859 860 pinctrl_uart2_dce: uart2dcegrp { 861 fsl,pins = < 862 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 863 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 864 >; 865 }; 866 867 /* DTE mode */ 868 pinctrl_uart2_dte: uart2dtegrp { 869 fsl,pins = < 870 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 871 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 872 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 873 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 874 >; 875 }; 876 877 pinctrl_uart4_dce: uart4dcegrp { 878 fsl,pins = < 879 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 880 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 881 >; 882 }; 883 884 /* DTE mode */ 885 pinctrl_uart4_dte: uart4dtegrp { 886 fsl,pins = < 887 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 888 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 889 >; 890 }; 891 892 pinctrl_uart5_dce: uart5dcegrp { 893 fsl,pins = < 894 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 895 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 896 >; 897 }; 898 899 /* DTE mode */ 900 pinctrl_uart5_dte: uart5dtegrp { 901 fsl,pins = < 902 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 903 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 904 >; 905 }; 906 907 pinctrl_usbotg: usbotggrp { 908 fsl,pins = < 909 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 910 >; 911 }; 912 913 pinctrl_usdhc1_4bit: usdhc1grp_4bit { 914 fsl,pins = < 915 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 916 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 917 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 918 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 919 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 920 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 921 >; 922 }; 923 924 pinctrl_usdhc1_8bit: usdhc1grp_8bit { 925 fsl,pins = < 926 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 927 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 928 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 929 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 930 >; 931 }; 932 933 pinctrl_usdhc2: usdhc2grp { 934 fsl,pins = < 935 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 936 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 937 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 938 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 939 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 940 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 941 >; 942 }; 943 944 pinctrl_usdhc3: usdhc3grp { 945 fsl,pins = < 946 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 947 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 948 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 949 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 950 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 951 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 952 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 953 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 954 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 955 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 956 /* eMMC reset */ 957 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 958 >; 959 }; 960}; 961