1// SPDX-License-Identifier: GPL-2.0-or-later 2/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ 3/* Based on code by myd_c335x.dts, MYiRtech.com */ 4/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ 5 6/dts-v1/; 7 8#include "am335x-myirtech-myc.dtsi" 9 10#include <dt-bindings/display/tda998x.h> 11#include <dt-bindings/input/input.h> 12 13/ { 14 model = "MYIR MYD-AM335X"; 15 compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx"; 16 17 chosen { 18 stdout-path = &uart0; 19 }; 20 21 clk12m: clk12m { 22 compatible = "fixed-clock"; 23 clock-frequency = <12000000>; 24 25 #clock-cells = <0>; 26 }; 27 28 gpio_buttons: gpio_buttons { 29 compatible = "gpio-keys"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&gpio_buttons_pins>; 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 button1: button@0 { 36 reg = <0>; 37 label = "button1"; 38 linux,code = <BTN_1>; 39 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 40 }; 41 42 button2: button@1 { 43 reg = <1>; 44 label = "button2"; 45 linux,code = <BTN_2>; 46 gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; 47 }; 48 }; 49 50 sound: sound { 51 compatible = "simple-audio-card"; 52 simple-audio-card,format = "i2s"; 53 simple-audio-card,bitclock-master = <&master_codec>; 54 simple-audio-card,frame-master = <&master_codec>; 55 56 simple-audio-card,cpu { 57 sound-dai = <&mcasp0>; 58 }; 59 60 master_codec: simple-audio-card,codec@1 { 61 sound-dai = <&sgtl5000>; 62 }; 63 64 simple-audio-card,codec@2 { 65 sound-dai = <&tda9988>; 66 }; 67 }; 68 69 vdd_5v0: vdd_5v0_reg { 70 compatible = "regulator-fixed"; 71 regulator-name = "vdd_5v0"; 72 regulator-min-microvolt = <5000000>; 73 regulator-max-microvolt = <5000000>; 74 regulator-always-on; 75 regulator-boot-on; 76 }; 77 78 vdd_3v3: vdd_3v3_reg { 79 compatible = "regulator-fixed"; 80 regulator-name = "vdd-3v3"; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 regulator-always-on; 84 regulator-boot-on; 85 vin-supply = <&vdd_5v0>; 86 }; 87}; 88 89&cpsw_port2 { 90 status = "okay"; 91 phy-handle = <&phy1>; 92 phy-mode = "rgmii-id"; 93 ti,dual-emac-pvid = <2>; 94}; 95 96&davinci_mdio_sw { 97 phy1: ethernet-phy@6 { 98 reg = <6>; 99 eee-broken-1000t; 100 }; 101}; 102 103&mac_sw { 104 pinctrl-0 = <ð_slave1_pins_default>, <ð_slave2_pins_default>; 105 pinctrl-1 = <ð_slave1_pins_sleep>, <ð_slave2_pins_sleep>; 106 slaves = <2>; 107}; 108 109&dcan0 { 110 pinctrl-names = "default", "sleep"; 111 pinctrl-0 = <&dcan0_pins_default>; 112 pinctrl-1 = <&dcan0_pins_sleep>; 113 status = "okay"; 114}; 115 116&dcan1 { 117 pinctrl-names = "default", "sleep"; 118 pinctrl-0 = <&dcan1_pins_default>; 119 pinctrl-1 = <&dcan1_pins_sleep>; 120 status = "okay"; 121}; 122 123&ehrpwm0 { 124 pinctrl-names = "default", "sleep"; 125 pinctrl-0 = <&ehrpwm0_pins_default>; 126 pinctrl-1 = <&ehrpwm0_pins_sleep>; 127 status = "okay"; 128}; 129 130&epwmss0 { 131 status = "okay"; 132}; 133 134&i2c1 { 135 pinctrl-names = "default", "gpio", "sleep"; 136 pinctrl-0 = <&i2c1_pins_default>; 137 pinctrl-1 = <&i2c1_pins_gpio>; 138 pinctrl-2 = <&i2c1_pins_sleep>; 139 clock-frequency = <400000>; 140 scl-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 141 sda-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 142 status = "okay"; 143 144 sgtl5000: sgtl5000@a { 145 compatible = "fsl,sgtl5000"; 146 reg =<0xa>; 147 clocks = <&clk12m>; 148 micbias-resistor-k-ohms = <4>; 149 micbias-voltage-m-volts = <2250>; 150 VDDA-supply = <&vdd_3v3>; 151 VDDIO-supply = <&vdd_3v3>; 152 153 #sound-dai-cells = <0>; 154 }; 155 156 tda9988: tda9988@70 { 157 compatible = "nxp,tda998x"; 158 reg =<0x70>; 159 audio-ports = <TDA998x_I2S 1>; 160 161 #sound-dai-cells = <0>; 162 163 ports { 164 port@0 { 165 hdmi_0: endpoint@0 { 166 remote-endpoint = <&lcdc_0>; 167 }; 168 }; 169 }; 170 }; 171}; 172 173&lcdc { 174 pinctrl-names = "default", "sleep"; 175 pinctrl-0 = <&lcdc_pins_default>; 176 pinctrl-1 = <&lcdc_pins_sleep>; 177 blue-and-red-wiring = "straight"; 178 status = "okay"; 179 180 port { 181 lcdc_0: endpoint@0 { 182 remote-endpoint = <&hdmi_0>; 183 }; 184 }; 185}; 186 187&leds { 188 pinctrl-0 = <&led_mod_pins &leds_pins>; 189 190 led1: led1 { 191 label = "base:user1"; 192 gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; 193 color = <LED_COLOR_ID_GREEN>; 194 default-state = "off"; 195 }; 196 197 led2: led2 { 198 label = "base:user2"; 199 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 200 color = <LED_COLOR_ID_GREEN>; 201 default-state = "off"; 202 }; 203}; 204 205&mcasp0 { 206 pinctrl-names = "default", "sleep"; 207 pinctrl-0 = <&mcasp0_pins_default>; 208 pinctrl-1 = <&mcasp0_pins_sleep>; 209 op-mode = <0>; 210 tdm-slots = <2>; 211 serial-dir = <0 1 2 0>; 212 tx-num-evt = <32>; 213 rx-num-evt = <32>; 214 status = "okay"; 215 216 #sound-dai-cells = <0>; 217}; 218 219&mmc1 { 220 pinctrl-names = "default", "sleep"; 221 pinctrl-0 = <&mmc1_pins_default>; 222 pinctrl-1 = <&mmc1_pins_sleep>; 223 cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 224 bus-width = <4>; 225 vmmc-supply = <&vdd_3v3>; 226 status = "okay"; 227}; 228 229&nand0 { 230 nand_parts: partitions { 231 compatible = "fixed-partitions"; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 235 partition@0 { 236 label = "MLO"; 237 reg = <0x00000 0x20000>; 238 }; 239 240 partition@80000 { 241 label = "boot"; 242 reg = <0x80000 0x100000>; 243 }; 244 }; 245}; 246 247&tscadc { 248 status = "okay"; 249 250 adc: adc { 251 ti,adc-channels = <0 1 2 3 4 5 6>; 252 }; 253}; 254 255&uart0 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&uart0_pins>; 258 status = "okay"; 259}; 260 261&uart1 { 262 pinctrl-names = "default", "sleep"; 263 pinctrl-0 = <&uart1_pins_default>; 264 pinctrl-1 = <&uart1_pins_sleep>; 265 linux,rs485-enabled-at-boot-time; 266 status = "okay"; 267}; 268 269&uart2 { 270 pinctrl-names = "default", "sleep"; 271 pinctrl-0 = <&uart2_pins_default>; 272 pinctrl-1 = <&uart2_pins_sleep>; 273 status = "okay"; 274}; 275 276&usb { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&usb_pins>; 279}; 280 281&usb0 { 282 dr_mode = "otg"; 283}; 284 285&usb0_phy { 286 vcc-supply = <&vdd_5v0>; 287}; 288 289&usb1 { 290 dr_mode = "host"; 291}; 292 293&usb1_phy { 294 vcc-supply = <&vdd_5v0>; 295}; 296 297&vdd_mod { 298 vin-supply = <&vdd_3v3>; 299}; 300 301&am33xx_pinmux { 302 dcan0_pins_default: pinmux_dcan0_pins_default { 303 pinctrl-single,pins = < 304 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */ 305 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */ 306 >; 307 }; 308 309 dcan0_pins_sleep: pinmux_dcan0_pins_sleep { 310 pinctrl-single,pins = < 311 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 312 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 313 >; 314 }; 315 316 dcan1_pins_default: pinmux_dcan1_pins_default { 317 pinctrl-single,pins = < 318 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */ 319 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */ 320 >; 321 }; 322 323 dcan1_pins_sleep: pinmux_dcan1_pins_sleep { 324 pinctrl-single,pins = < 325 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 326 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 327 >; 328 }; 329 330 ehrpwm0_pins_default: pinmux_ehrpwm0_pins_default { 331 pinctrl-single,pins = < 332 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */ 333 >; 334 }; 335 336 ehrpwm0_pins_sleep: pinmux_ehrpwm0_pins_sleep { 337 pinctrl-single,pins = < 338 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 339 >; 340 }; 341 342 eth_slave2_pins_default: pinmux_eth_slave2_pins_default { 343 pinctrl-single,pins = < 344 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */ 345 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */ 346 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td3 */ 347 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td2 */ 348 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td1 */ 349 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td0 */ 350 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tclk */ 351 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rclk */ 352 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd3 */ 353 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd2 */ 354 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd1 */) 355 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 */) 356 >; 357 }; 358 359 eth_slave2_pins_sleep: pinmux_eth_slave2_pins_sleep { 360 pinctrl-single,pins = < 361 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) 362 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) 363 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) 364 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) 365 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) 366 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) 367 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) 368 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) 369 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) 370 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) 371 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) 372 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) 373 >; 374 }; 375 376 gpio_buttons_pins: pinmux_gpio_buttons_pins { 377 pinctrl-single,pins = < 378 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */ 379 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */ 380 >; 381 }; 382 383 i2c1_pins_default: pinmux_i2c1_pins_default { 384 pinctrl-single,pins = < 385 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */ 386 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */ 387 >; 388 }; 389 390 i2c1_pins_gpio: pinmux_i2c1_pins_gpio { 391 pinctrl-single,pins = < 392 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */ 393 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */ 394 >; 395 }; 396 397 i2c1_pins_sleep: pinmux_i2c1_pins_sleep { 398 pinctrl-single,pins = < 399 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7) 400 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7) 401 >; 402 }; 403 404 lcdc_pins_default: pinmux_lcdc_pins_default { 405 pinctrl-single,pins = < 406 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */ 407 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */ 408 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* lcd_data2 */ 409 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* lcd_data3 */ 410 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* lcd_data4 */ 411 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* lcd_data5 */ 412 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* lcd_data6 */ 413 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* lcd_data7 */ 414 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* lcd_data8 */ 415 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* lcd_data9 */ 416 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* lcd_data10 */ 417 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* lcd_data11 */ 418 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* lcd_data12 */ 419 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* lcd_data13 */ 420 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* lcd_data14 */ 421 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* lcd_data15 */ 422 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_vsync */ 423 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_hsync */ 424 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* lcd_pclk */ 425 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias_en */ 426 >; 427 }; 428 429 lcdc_pins_sleep: pinmux_lcdc_pins_sleep { 430 pinctrl-single,pins = < 431 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) 432 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) 433 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) 434 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) 435 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) 436 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) 437 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) 438 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) 439 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) 440 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) 441 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) 442 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) 443 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) 444 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) 445 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) 446 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) 447 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) 448 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) 449 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 450 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 451 >; 452 }; 453 454 leds_pins: pinmux_leds_pins { 455 pinctrl-single,pins = < 456 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */ 457 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */ 458 >; 459 }; 460 461 mcasp0_pins_default: pinmux_mcasp0_pins_default { 462 pinctrl-single,pins = < 463 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */ 464 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */ 465 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mcasp0_axr2_mux0 */ 466 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_axr1_mux0 */ 467 >; 468 }; 469 470 mcasp0_pins_sleep: pinmux_mcasp0_pins_sleep { 471 pinctrl-single,pins = < 472 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) 473 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7) 474 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) 475 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) 476 >; 477 }; 478 479 mmc1_pins_default: pinmux_mmc1_pins_default { 480 pinctrl-single,pins = < 481 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */ 482 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */ 483 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat1 */ 484 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat0 */ 485 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk */ 486 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd */ 487 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[21] */ 488 >; 489 }; 490 491 mmc1_pins_sleep: pinmux_mmc1_pins_sleep { 492 pinctrl-single,pins = < 493 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0) 494 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0) 495 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLDOWN, MUX_MODE0) 496 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLDOWN, MUX_MODE0) 497 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) 498 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLDOWN, MUX_MODE0) 499 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) 500 >; 501 }; 502 503 uart0_pins: pinmux_uart0_pins { 504 pinctrl-single,pins = < 505 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */ 506 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */ 507 >; 508 }; 509 510 uart1_pins_default: pinmux_uart1_pins_default { 511 pinctrl-single,pins = < 512 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */ 513 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */ 514 >; 515 }; 516 517 uart1_pins_sleep: pinmux_uart1_pins_sleep { 518 pinctrl-single,pins = < 519 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7) 520 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7) 521 >; 522 }; 523 524 uart2_pins_default: pinmux_uart2_pins_default { 525 pinctrl-single,pins = < 526 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */ 527 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */ 528 >; 529 }; 530 531 uart2_pins_sleep: pinmux_uart2_pins_sleep { 532 pinctrl-single,pins = < 533 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) 534 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) 535 >; 536 }; 537 538 usb_pins: pinmux_usb_pins { 539 pinctrl-single,pins = < 540 AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */ 541 AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */ 542 >; 543 }; 544}; 545