1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - renesas,r9a07g044-ssi  # RZ/G2{L,LC}
17          - renesas,r9a07g054-ssi  # RZ/V2L
18      - const: renesas,rz-ssi
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 4
25
26  interrupt-names:
27    items:
28      - const: int_req
29      - const: dma_rx
30      - const: dma_tx
31      - const: dma_rt
32
33  clocks:
34    maxItems: 4
35
36  clock-names:
37    items:
38      - const: ssi
39      - const: ssi_sfr
40      - const: audio_clk1
41      - const: audio_clk2
42
43  power-domains:
44    maxItems: 1
45
46  resets:
47    maxItems: 1
48
49  dmas:
50    minItems: 1
51    maxItems: 2
52    description:
53      The first cell represents a phandle to dmac
54      The second cell specifies the encoded MID/RID values of the SSI port
55      connected to the DMA client and the slave channel configuration
56      parameters.
57      bits[0:9]   - Specifies MID/RID value of a SSI channel as below
58                    MID/RID value of SSI rx0 = 0x256
59                    MID/RID value of SSI tx0 = 0x255
60                    MID/RID value of SSI rx1 = 0x25a
61                    MID/RID value of SSI tx1 = 0x259
62                    MID/RID value of SSI rt2 = 0x25f
63                    MID/RID value of SSI rx3 = 0x262
64                    MID/RID value of SSI tx3 = 0x261
65      bit[10]     - HIEN = 1, Detects a request in response to the rising edge
66                    of the signal
67      bit[11]     - LVL = 0, Detects based on the edge
68      bits[12:14] - AM = 2, Bus cycle mode
69      bit[15]     - TM = 0, Single transfer mode
70
71  dma-names:
72    oneOf:
73      - items:
74          - const: tx
75          - const: rx
76      - items:
77          - const: rt
78
79  '#sound-dai-cells':
80    const: 0
81
82required:
83  - compatible
84  - reg
85  - interrupts
86  - interrupt-names
87  - clocks
88  - clock-names
89  - resets
90  - '#sound-dai-cells'
91
92additionalProperties: false
93
94examples:
95  - |
96    #include <dt-bindings/interrupt-controller/arm-gic.h>
97    #include <dt-bindings/clock/r9a07g044-cpg.h>
98
99    ssi0: ssi@10049c00 {
100        compatible = "renesas,r9a07g044-ssi",
101                     "renesas,rz-ssi";
102            reg = <0x10049c00 0x400>;
103            interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
104                         <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
105                         <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
106                         <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
107            interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
108            clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
109                     <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
110                     <&audio_clk1>,
111                     <&audio_clk2>;
112            clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
113            power-domains = <&cpg>;
114            resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
115            dmas = <&dmac 0x2655>,
116                   <&dmac 0x2656>;
117            dma-names = "tx", "rx";
118            #sound-dai-cells = <0>;
119    };
120