1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm RPMH RSC 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: | 13 Resource Power Manager Hardened (RPMH) is the mechanism for communicating 14 with the hardened resource accelerators on Qualcomm SoCs. Requests to the 15 resources can be written to the Trigger Command Set (TCS) registers and 16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in 17 sequence over an internal bus. 18 19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity 20 (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and 21 active/wake resource requests. Multiple such DRVs can exist in a SoC and can 22 be written to from Linux. The structure of each DRV follows the same template 23 with a few variations that are captured by the properties here. 24 25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs 26 have powered off to facilitate idle power saving. TCS could be classified as:: 27 ACTIVE - Triggered by Linux 28 SLEEP - Triggered by F/W 29 WAKE - Triggered by F/W 30 CONTROL - Triggered by F/W 31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h> 32 33 The order in which they are described in the DT, should match the hardware 34 configuration. 35 36 Requests can be made for the state of a resource, when the subsystem is 37 active or idle. When all subsystems like Modem, GPU, CPU are idle, the 38 resource state will be an aggregate of the sleep votes from each of those 39 subsystems. Clients may request a sleep value for their shared resources in 40 addition to the active mode requests. 41 42 Drivers that want to use the RSC to communicate with RPMH must specify their 43 bindings as child nodes of the RSC controllers they wish to communicate with. 44 45properties: 46 compatible: 47 const: qcom,rpmh-rsc 48 49 interrupts: 50 minItems: 1 51 maxItems: 4 52 description: 53 The interrupt that trips when a message complete/response is received for 54 this DRV from the accelerators. 55 Number of interrupts must match number of DRV blocks. 56 57 label: 58 description: 59 Name for the RSC. The name would be used in trace logs. 60 61 qcom,drv-id: 62 $ref: /schemas/types.yaml#/definitions/uint32 63 description: 64 The ID of the DRV in the RSC block that will be used by this controller. 65 66 qcom,tcs-config: 67 $ref: /schemas/types.yaml#/definitions/uint32-matrix 68 items: 69 - items: 70 - description: TCS type 71 enum: [ 0, 1, 2, 3 ] 72 - description: Number of TCS 73 - items: 74 - description: TCS type 75 enum: [ 0, 1, 2, 3 ] 76 - description: Number of TCS 77 - items: 78 - description: TCS type 79 enum: [ 0, 1, 2, 3] 80 - description: Numbe r of TCS 81 - items: 82 - description: TCS type 83 enum: [ 0, 1, 2, 3 ] 84 - description: Number of TCS 85 description: | 86 The tuple defining the configuration of TCS. Must have two cells which 87 describe each TCS type. The order of the TCS must match the hardware 88 configuration. 89 Cell 1 (TCS Type):: TCS types to be specified:: 90 - ACTIVE_TCS 91 - SLEEP_TCS 92 - WAKE_TCS 93 - CONTROL_TCS 94 Cell 2 (Number of TCS):: <u32> 95 96 qcom,tcs-offset: 97 $ref: /schemas/types.yaml#/definitions/uint32 98 description: 99 The offset of the TCS blocks. 100 101 reg: 102 minItems: 1 103 maxItems: 4 104 105 reg-names: 106 minItems: 1 107 items: 108 - const: drv-0 109 - const: drv-1 110 - const: drv-2 111 - const: drv-3 112 113 bcm-voter: 114 $ref: /schemas/interconnect/qcom,bcm-voter.yaml# 115 116 clock-controller: 117 $ref: /schemas/clock/qcom,rpmhcc.yaml# 118 119 power-controller: 120 $ref: /schemas/power/qcom,rpmpd.yaml# 121 122patternProperties: 123 '-regulators$': 124 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# 125 126required: 127 - compatible 128 - interrupts 129 - qcom,drv-id 130 - qcom,tcs-config 131 - qcom,tcs-offset 132 - reg 133 - reg-names 134 135additionalProperties: false 136 137examples: 138 - | 139 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of 140 // 2, the register offsets for DRV2 start at 0D00, the register 141 // calculations are like this:: 142 // DRV0: 0x179C0000 143 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000 144 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 145 // TCS-OFFSET: 0xD00 146 #include <dt-bindings/interrupt-controller/arm-gic.h> 147 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 148 149 rsc@179c0000 { 150 compatible = "qcom,rpmh-rsc"; 151 reg = <0x179c0000 0x10000>, 152 <0x179d0000 0x10000>, 153 <0x179e0000 0x10000>; 154 reg-names = "drv-0", "drv-1", "drv-2"; 155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 158 label = "apps_rsc"; 159 qcom,tcs-offset = <0xd00>; 160 qcom,drv-id = <2>; 161 qcom,tcs-config = <ACTIVE_TCS 2>, 162 <SLEEP_TCS 3>, 163 <WAKE_TCS 3>, 164 <CONTROL_TCS 1>; 165 }; 166 167 - | 168 // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the 169 // register offsets for DRV0 start at 01C00, the register calculations are 170 // like this:: 171 // DRV0: 0xAF20000 172 // TCS-OFFSET: 0x1C00 173 #include <dt-bindings/interrupt-controller/arm-gic.h> 174 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 175 176 rsc@af20000 { 177 compatible = "qcom,rpmh-rsc"; 178 reg = <0xaf20000 0x10000>; 179 reg-names = "drv-0"; 180 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 181 label = "disp_rsc"; 182 qcom,tcs-offset = <0x1c00>; 183 qcom,drv-id = <0>; 184 qcom,tcs-config = <ACTIVE_TCS 0>, 185 <SLEEP_TCS 1>, 186 <WAKE_TCS 1>, 187 <CONTROL_TCS 0>; 188 }; 189 190 - | 191 #include <dt-bindings/interrupt-controller/arm-gic.h> 192 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 193 #include <dt-bindings/power/qcom-rpmpd.h> 194 195 rsc@18200000 { 196 compatible = "qcom,rpmh-rsc"; 197 reg = <0x18200000 0x10000>, 198 <0x18210000 0x10000>, 199 <0x18220000 0x10000>; 200 reg-names = "drv-0", "drv-1", "drv-2"; 201 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 204 label = "apps_rsc"; 205 qcom,tcs-offset = <0xd00>; 206 qcom,drv-id = <2>; 207 qcom,tcs-config = <ACTIVE_TCS 2>, 208 <SLEEP_TCS 3>, 209 <WAKE_TCS 3>, 210 <CONTROL_TCS 0>; 211 212 clock-controller { 213 compatible = "qcom,sm8350-rpmh-clk"; 214 #clock-cells = <1>; 215 clock-names = "xo"; 216 clocks = <&xo_board>; 217 }; 218 219 power-controller { 220 compatible = "qcom,sm8350-rpmhpd"; 221 #power-domain-cells = <1>; 222 operating-points-v2 = <&rpmhpd_opp_table>; 223 224 rpmhpd_opp_table: opp-table { 225 compatible = "operating-points-v2"; 226 227 rpmhpd_opp_ret: opp1 { 228 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 229 }; 230 231 rpmhpd_opp_min_svs: opp2 { 232 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 233 }; 234 235 rpmhpd_opp_low_svs: opp3 { 236 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 237 }; 238 239 rpmhpd_opp_svs: opp4 { 240 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 241 }; 242 243 rpmhpd_opp_svs_l1: opp5 { 244 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 245 }; 246 247 rpmhpd_opp_nom: opp6 { 248 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 249 }; 250 251 rpmhpd_opp_nom_l1: opp7 { 252 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 253 }; 254 255 rpmhpd_opp_nom_l2: opp8 { 256 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 257 }; 258 259 rpmhpd_opp_turbo: opp9 { 260 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 261 }; 262 263 rpmhpd_opp_turbo_l1: opp10 { 264 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 265 }; 266 }; 267 }; 268 269 bcm-voter { 270 compatible = "qcom,bcm-voter"; 271 }; 272 }; 273