1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT8192 Pin Controller 8 9maintainers: 10 - Sean Wang <sean.wang@mediatek.com> 11 12description: | 13 The Mediatek's Pin controller is used to control SoC pins. 14 15properties: 16 compatible: 17 const: mediatek,mt8192-pinctrl 18 19 gpio-controller: true 20 21 '#gpio-cells': 22 description: | 23 Number of cells in GPIO specifier. Since the generic GPIO binding is used, 24 the amount of cells must be specified as 2. See the below 25 mentioned gpio binding representation for description of particular cells. 26 const: 2 27 28 gpio-ranges: 29 description: gpio valid number range. 30 maxItems: 1 31 32 gpio-line-names: true 33 34 reg: 35 description: | 36 Physical address base for gpio base registers. There are 11 GPIO 37 physical address base in mt8192. 38 maxItems: 11 39 40 reg-names: 41 description: | 42 Gpio base register names. 43 maxItems: 11 44 45 interrupt-controller: true 46 47 '#interrupt-cells': 48 const: 2 49 50 interrupts: 51 description: The interrupt outputs to sysirq. 52 maxItems: 1 53 54#PIN CONFIGURATION NODES 55patternProperties: 56 '-pins$': 57 type: object 58 additionalProperties: false 59 patternProperties: 60 '^pins': 61 type: object 62 description: | 63 A pinctrl node should contain at least one subnodes representing the 64 pinctrl groups available on the machine. Each subnode will list the 65 pins it needs, and how they should be configured, with regard to muxer 66 configuration, pullups, drive strength, input enable/disable and 67 input schmitt. 68 $ref: "pinmux-node.yaml" 69 70 properties: 71 pinmux: 72 description: | 73 Integer array, represents gpio pin number and mux setting. 74 Supported pin number and mux varies for different SoCs, and are defined 75 as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 76 77 drive-strength: 78 description: | 79 It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See 80 dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. 81 enum: [2, 4, 6, 8, 10, 12, 14, 16] 82 83 drive-strength-microamp: 84 enum: [125, 250, 500, 1000] 85 86 bias-pull-down: 87 oneOf: 88 - type: boolean 89 description: normal pull down. 90 - enum: [100, 101, 102, 103] 91 description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ 92 defines in dt-bindings/pinctrl/mt65xx.h. 93 94 bias-pull-up: 95 oneOf: 96 - type: boolean 97 description: normal pull up. 98 - enum: [100, 101, 102, 103] 99 description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ 100 defines in dt-bindings/pinctrl/mt65xx.h. 101 102 bias-disable: true 103 104 output-high: true 105 106 output-low: true 107 108 input-enable: true 109 110 input-disable: true 111 112 input-schmitt-enable: true 113 114 input-schmitt-disable: true 115 116 required: 117 - pinmux 118 119 additionalProperties: false 120 121allOf: 122 - $ref: "pinctrl.yaml#" 123 124required: 125 - compatible 126 - reg 127 - interrupts 128 - interrupt-controller 129 - '#interrupt-cells' 130 - gpio-controller 131 - '#gpio-cells' 132 - gpio-ranges 133 134additionalProperties: false 135 136examples: 137 - | 138 #include <dt-bindings/pinctrl/mt8192-pinfunc.h> 139 #include <dt-bindings/interrupt-controller/arm-gic.h> 140 pio: pinctrl@10005000 { 141 compatible = "mediatek,mt8192-pinctrl"; 142 reg = <0x10005000 0x1000>, 143 <0x11c20000 0x1000>, 144 <0x11d10000 0x1000>, 145 <0x11d30000 0x1000>, 146 <0x11d40000 0x1000>, 147 <0x11e20000 0x1000>, 148 <0x11e70000 0x1000>, 149 <0x11ea0000 0x1000>, 150 <0x11f20000 0x1000>, 151 <0x11f30000 0x1000>, 152 <0x1000b000 0x1000>; 153 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 154 "iocfg_bl", "iocfg_br", "iocfg_lm", 155 "iocfg_lb", "iocfg_rt", "iocfg_lt", 156 "iocfg_tl", "eint"; 157 gpio-controller; 158 #gpio-cells = <2>; 159 gpio-ranges = <&pio 0 0 220>; 160 interrupt-controller; 161 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 162 #interrupt-cells = <2>; 163 164 spi1-default-pins { 165 pins-cs-mosi-clk { 166 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 167 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 168 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 169 bias-disable; 170 }; 171 172 pins-miso { 173 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 174 bias-pull-down; 175 }; 176 }; 177 }; 178