1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11  - Sekhar Nori <nsekhar@ti.com>
12
13description:
14  The 3-port switch gigabit ethernet subsystem provides ethernet packet
15  communication and can be configured as an ethernet switch. It provides the
16  gigabit media independent interface (GMII),reduced gigabit media
17  independent interface (RGMII), reduced media independent interface (RMII),
18  the management data input output (MDIO) for physical layer device (PHY)
19  management.
20
21properties:
22  compatible:
23    oneOf:
24      - const: ti,cpsw-switch
25      - items:
26          - const: ti,am335x-cpsw-switch
27          - const: ti,cpsw-switch
28      - items:
29          - const: ti,am4372-cpsw-switch
30          - const: ti,cpsw-switch
31      - items:
32          - const: ti,dra7-cpsw-switch
33          - const: ti,cpsw-switch
34
35  reg:
36    maxItems: 1
37    description:
38      The physical base address and size of full the CPSW module IO range
39
40  '#address-cells':
41    const: 1
42
43  '#size-cells':
44    const: 1
45
46  ranges: true
47
48  clocks:
49    maxItems: 1
50    description: CPSW functional clock
51
52  clock-names:
53    items:
54      - const: fck
55
56  interrupts:
57    items:
58      - description: RX_THRESH interrupt
59      - description: RX interrupt
60      - description: TX interrupt
61      - description: MISC interrupt
62
63  interrupt-names:
64    items:
65      - const: "rx_thresh"
66      - const: "rx"
67      - const: "tx"
68      - const: "misc"
69
70  pinctrl-names: true
71
72  syscon:
73    $ref: /schemas/types.yaml#/definitions/phandle
74    description:
75      Phandle to the system control device node which provides access to
76      efuse IO range with MAC addresses
77
78  ethernet-ports:
79    type: object
80    properties:
81      '#address-cells':
82        const: 1
83      '#size-cells':
84        const: 0
85
86    patternProperties:
87      "^port@[0-9]+$":
88        type: object
89        description: CPSW external ports
90
91        $ref: ethernet-controller.yaml#
92
93        properties:
94          reg:
95            items:
96              - enum: [1, 2]
97            description: CPSW port number
98
99          phys:
100            maxItems: 1
101            description: phandle on phy-gmii-sel PHY
102
103          label:
104            description: label associated with this port
105
106          ti,dual-emac-pvid:
107            $ref: /schemas/types.yaml#/definitions/uint32
108            minimum: 1
109            maximum: 1024
110            description:
111              Specifies default PORT VID to be used to segregate
112              ports. Default value - CPSW port number.
113
114        required:
115          - reg
116          - phys
117
118  cpts:
119    type: object
120    description:
121      The Common Platform Time Sync (CPTS) module
122
123    properties:
124      clocks:
125        maxItems: 1
126        description: CPTS reference clock
127
128      clock-names:
129        items:
130          - const: cpts
131
132      cpts_clock_mult:
133        $ref: /schemas/types.yaml#/definitions/uint32
134        description:
135          Numerator to convert input clock ticks into ns
136
137      cpts_clock_shift:
138        $ref: /schemas/types.yaml#/definitions/uint32
139        description:
140          Denominator to convert input clock ticks into ns.
141          Mult and shift will be calculated basing on CPTS rftclk frequency if
142          both cpts_clock_shift and cpts_clock_mult properties are not provided.
143
144    required:
145      - clocks
146      - clock-names
147
148patternProperties:
149  "^mdio@":
150    type: object
151    description:
152      CPSW MDIO bus.
153    $ref: "ti,davinci-mdio.yaml#"
154
155
156required:
157  - compatible
158  - reg
159  - ranges
160  - clocks
161  - clock-names
162  - interrupts
163  - interrupt-names
164  - '#address-cells'
165  - '#size-cells'
166
167additionalProperties: false
168
169examples:
170  - |
171    #include <dt-bindings/interrupt-controller/irq.h>
172    #include <dt-bindings/interrupt-controller/arm-gic.h>
173    #include <dt-bindings/clock/dra7.h>
174
175    mac_sw: switch@0 {
176        compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
177        reg = <0x0 0x4000>;
178        ranges = <0 0 0x4000>;
179        clocks = <&gmac_main_clk>;
180        clock-names = "fck";
181        #address-cells = <1>;
182        #size-cells = <1>;
183        syscon = <&scm_conf>;
184
185        interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
186                     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
187                     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
188                     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
189        interrupt-names = "rx_thresh", "rx", "tx", "misc";
190
191        ethernet-ports {
192                #address-cells = <1>;
193                #size-cells = <0>;
194
195                cpsw_port1: port@1 {
196                        reg = <1>;
197                        label = "port1";
198                        mac-address = [ 00 00 00 00 00 00 ];
199                        phys = <&phy_gmii_sel 1>;
200                        phy-handle = <&ethphy0_sw>;
201                        phy-mode = "rgmii";
202                        ti,dual-emac-pvid = <1>;
203                };
204
205                cpsw_port2: port@2 {
206                        reg = <2>;
207                        label = "wan";
208                        mac-address = [ 00 00 00 00 00 00 ];
209                        phys = <&phy_gmii_sel 2>;
210                        phy-handle = <&ethphy1_sw>;
211                        phy-mode = "rgmii";
212                        ti,dual-emac-pvid = <2>;
213                };
214        };
215
216        davinci_mdio_sw: mdio@1000 {
217                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
218                reg = <0x1000 0x100>;
219                clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
220                clock-names = "fck";
221                #address-cells = <1>;
222                #size-cells = <0>;
223                bus_freq = <1000000>;
224
225                ethphy0_sw: ethernet-phy@0 {
226                        reg = <0>;
227                };
228
229                ethphy1_sw: ethernet-phy@1 {
230                        reg = <1>;
231                };
232        };
233
234        cpts {
235                clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
236                clock-names = "cpts";
237        };
238    };
239