1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm SDHCI controller (sdhci-msm)
9
10maintainers:
11  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,msm8226-sdhci
27              - qcom,msm8953-sdhci
28              - qcom,msm8974-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
34      - items:
35          - enum:
36              - qcom,qcs404-sdhci
37              - qcom,sc7180-sdhci
38              - qcom,sc7280-sdhci
39              - qcom,sdm630-sdhci
40              - qcom,sdm845-sdhci
41              - qcom,sdx55-sdhci
42              - qcom,sdx65-sdhci
43              - qcom,sm6125-sdhci
44              - qcom,sm6350-sdhci
45              - qcom,sm8150-sdhci
46              - qcom,sm8250-sdhci
47          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
48
49  reg:
50    minItems: 1
51    items:
52      - description: Host controller register map
53      - description: SD Core register map
54      - description: CQE register map
55      - description: Inline Crypto Engine register map
56
57  reg-names:
58    minItems: 1
59    maxItems: 4
60    oneOf:
61      - items:
62          - const: hc_mem
63      - items:
64          - const: hc_mem
65          - const: core_mem
66      - items:
67          - const: hc_mem
68          - const: cqe_mem
69      - items:
70          - const: hc_mem
71          - const: cqe_mem
72          - const: ice_mem
73      - items:
74          - const: hc_mem
75          - const: core_mem
76          - const: cqe_mem
77          - const: ice_mem
78
79  clocks:
80    minItems: 3
81    items:
82      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
83      - description: SDC MMC clock, MCLK
84      - description: TCXO clock
85      - description: clock for Inline Crypto Engine
86      - description: SDCC bus voter clock
87      - description: reference clock for RCLK delay calibration
88      - description: sleep clock for RCLK delay calibration
89
90  clock-names:
91    minItems: 2
92    items:
93      - const: iface
94      - const: core
95      - const: xo
96      - const: ice
97      - const: bus
98      - const: cal
99      - const: sleep
100
101  interrupts:
102    maxItems: 2
103
104  interrupt-names:
105    items:
106      - const: hc_irq
107      - const: pwr_irq
108
109  pinctrl-names:
110    minItems: 1
111    items:
112      - const: default
113      - const: sleep
114
115  pinctrl-0:
116    description:
117      Should specify pin control groups used for this controller.
118
119  qcom,ddr-config:
120    $ref: /schemas/types.yaml#/definitions/uint32
121    description: platform specific settings for DDR_CONFIG reg.
122
123  qcom,dll-config:
124    $ref: /schemas/types.yaml#/definitions/uint32
125    description: platform specific settings for DLL_CONFIG reg.
126
127  iommus:
128    minItems: 1
129    maxItems: 8
130    description: |
131      phandle to apps_smmu node with sid mask.
132
133  interconnects:
134    items:
135      - description: data path, sdhc to ddr
136      - description: config path, cpu to sdhc
137
138  interconnect-names:
139    items:
140      - const: sdhc-ddr
141      - const: cpu-sdhc
142
143  power-domains:
144    description: A phandle to sdhci power domain node
145    maxItems: 1
146
147  mmc-ddr-1_8v: true
148
149  mmc-hs200-1_8v: true
150
151  mmc-hs400-1_8v: true
152
153  bus-width: true
154
155  max-frequency: true
156
157patternProperties:
158  '^opp-table(-[a-z0-9]+)?$':
159    if:
160      properties:
161        compatible:
162          const: operating-points-v2
163    then:
164      patternProperties:
165        '^opp-?[0-9]+$':
166          required:
167            - required-opps
168
169required:
170  - compatible
171  - reg
172  - clocks
173  - clock-names
174  - interrupts
175
176allOf:
177  - $ref: mmc-controller.yaml#
178
179unevaluatedProperties: false
180
181examples:
182  - |
183    #include <dt-bindings/interrupt-controller/arm-gic.h>
184    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
185    #include <dt-bindings/clock/qcom,rpmh.h>
186    #include <dt-bindings/power/qcom-rpmpd.h>
187
188    sdhc_2: mmc@8804000 {
189      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
190      reg = <0 0x08804000 0 0x1000>;
191
192      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
193                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
194      interrupt-names = "hc_irq", "pwr_irq";
195
196      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
197               <&gcc GCC_SDCC2_APPS_CLK>,
198               <&rpmhcc RPMH_CXO_CLK>;
199      clock-names = "iface", "core", "xo";
200      iommus = <&apps_smmu 0x4a0 0x0>;
201      qcom,dll-config = <0x0007642c>;
202      qcom,ddr-config = <0x80040868>;
203      power-domains = <&rpmhpd SM8250_CX>;
204
205      operating-points-v2 = <&sdhc2_opp_table>;
206
207      sdhc2_opp_table: opp-table {
208        compatible = "operating-points-v2";
209
210        opp-19200000 {
211          opp-hz = /bits/ 64 <19200000>;
212          required-opps = <&rpmhpd_opp_min_svs>;
213        };
214
215        opp-50000000 {
216          opp-hz = /bits/ 64 <50000000>;
217          required-opps = <&rpmhpd_opp_low_svs>;
218        };
219
220        opp-100000000 {
221          opp-hz = /bits/ 64 <100000000>;
222          required-opps = <&rpmhpd_opp_svs>;
223        };
224
225        opp-202000000 {
226          opp-hz = /bits/ 64 <202000000>;
227          required-opps = <&rpmhpd_opp_svs_l1>;
228        };
229      };
230    };
231