1PDC interrupt controller
2
3Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
4Power Domain Controller (PDC) that is on always-on domain. In addition to
5providing power control for the power domains, the hardware also has an
6interrupt controller that can be used to help detect edge low interrupts as
7well detect interrupts when the GIC is non-operational.
8
9GIC is parent interrupt controller at the highest level. Platform interrupt
10controller PDC is next in hierarchy, followed by others. Drivers requiring
11wakeup capabilities of their device interrupts routed through the PDC, must
12specify PDC as their interrupt controller and request the PDC port associated
13with the GIC interrupt. See example below.
14
15Properties:
16
17- compatible:
18	Usage: required
19	Value type: <string>
20	Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
21		    - "qcom,sc7180-pdc": For SC7180
22		    - "qcom,sc7280-pdc": For SC7280
23		    - "qcom,sdm845-pdc": For SDM845
24		    - "qcom,sm6350-pdc": For SM6350
25		    - "qcom,sm8150-pdc": For SM8150
26		    - "qcom,sm8250-pdc": For SM8250
27		    - "qcom,sm8350-pdc": For SM8350
28
29- reg:
30	Usage: required
31	Value type: <prop-encoded-array>
32	Definition: Specifies the base physical address for PDC hardware.
33
34- interrupt-cells:
35	Usage: required
36	Value type: <u32>
37	Definition: Specifies the number of cells needed to encode an interrupt
38		    source.
39		    Must be 2.
40		    The first element of the tuple is the PDC pin for the
41		    interrupt.
42		    The second element is the trigger type.
43
44- interrupt-controller:
45	Usage: required
46	Value type: <bool>
47	Definition: Identifies the node as an interrupt controller.
48
49- qcom,pdc-ranges:
50	Usage: required
51	Value type: <u32 array>
52	Definition: Specifies the PDC pin offset and the number of PDC ports.
53		    The tuples indicates the valid mapping of valid PDC ports
54		    and their hwirq mapping.
55		    The first element of the tuple is the starting PDC port.
56		    The second element is the GIC hwirq number for the PDC port.
57		    The third element is the number of interrupts in sequence.
58
59Example:
60
61	pdc: interrupt-controller@b220000 {
62		compatible = "qcom,sdm845-pdc";
63		reg = <0xb220000 0x30000>;
64		qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
65		#interrupt-cells = <2>;
66		interrupt-parent = <&intc>;
67		interrupt-controller;
68	};
69
70DT binding of a device that wants to use the GIC SPI 514 as a wakeup
71interrupt, must do -
72
73	wake-device {
74		interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
75	};
76
77In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
78the qcom,pdc-ranges property.
79