1 /*
2  * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
3  *
4  * Copyright (C) 2009 - 2011 Texas Instruments
5  *
6  * Author: Misael Lopez Cruz <misael.lopez@ti.com>
7  * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
8  *          Margarita Olaya <magi.olaya@ti.com>
9  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * version 2 as published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope that it will be useful, but
16  * WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23  * 02110-1301 USA
24  *
25  */
26 
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/interrupt.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/pcm_params.h>
40 #include <sound/soc.h>
41 
42 #include <plat/dma.h>
43 #include <plat/omap_hwmod.h>
44 #include "omap-mcpdm.h"
45 #include "omap-pcm.h"
46 
47 struct omap_mcpdm {
48 	struct device *dev;
49 	unsigned long phys_base;
50 	void __iomem *io_base;
51 	int irq;
52 
53 	struct mutex mutex;
54 
55 	/* channel data */
56 	u32 dn_channels;
57 	u32 up_channels;
58 
59 	/* McPDM FIFO thresholds */
60 	u32 dn_threshold;
61 	u32 up_threshold;
62 
63 	/* McPDM dn offsets for rx1, and 2 channels */
64 	u32 dn_rx_offset;
65 };
66 
67 /*
68  * Stream DMA parameters
69  */
70 static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
71 	{
72 		.name = "Audio playback",
73 		.dma_req = OMAP44XX_DMA_MCPDM_DL,
74 		.data_type = OMAP_DMA_DATA_TYPE_S32,
75 		.sync_mode = OMAP_DMA_SYNC_PACKET,
76 		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
77 	},
78 	{
79 		.name = "Audio capture",
80 		.dma_req = OMAP44XX_DMA_MCPDM_UP,
81 		.data_type = OMAP_DMA_DATA_TYPE_S32,
82 		.sync_mode = OMAP_DMA_SYNC_PACKET,
83 		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
84 	},
85 };
86 
omap_mcpdm_write(struct omap_mcpdm * mcpdm,u16 reg,u32 val)87 static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
88 {
89 	__raw_writel(val, mcpdm->io_base + reg);
90 }
91 
omap_mcpdm_read(struct omap_mcpdm * mcpdm,u16 reg)92 static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
93 {
94 	return __raw_readl(mcpdm->io_base + reg);
95 }
96 
97 #ifdef DEBUG
omap_mcpdm_reg_dump(struct omap_mcpdm * mcpdm)98 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
99 {
100 	dev_dbg(mcpdm->dev, "***********************\n");
101 	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
102 			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
103 	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
104 			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
105 	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
106 			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
107 	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
108 			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
109 	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
110 			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
111 	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
112 			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
113 	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
114 			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
115 	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
116 			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
117 	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
118 			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
119 	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
120 			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
121 	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
122 			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
123 	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
124 			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
125 	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
126 			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
127 	dev_dbg(mcpdm->dev, "***********************\n");
128 }
129 #else
omap_mcpdm_reg_dump(struct omap_mcpdm * mcpdm)130 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
131 #endif
132 
133 /*
134  * Enables the transfer through the PDM interface to/from the Phoenix
135  * codec by enabling the corresponding UP or DN channels.
136  */
omap_mcpdm_start(struct omap_mcpdm * mcpdm)137 static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
138 {
139 	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
140 
141 	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
142 	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
143 
144 	ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
145 	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
146 
147 	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
148 	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
149 }
150 
151 /*
152  * Disables the transfer through the PDM interface to/from the Phoenix
153  * codec by disabling the corresponding UP or DN channels.
154  */
omap_mcpdm_stop(struct omap_mcpdm * mcpdm)155 static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
156 {
157 	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
158 
159 	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
160 	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
161 
162 	ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
163 	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
164 
165 	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
166 	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
167 
168 }
169 
170 /*
171  * Is the physical McPDM interface active.
172  */
omap_mcpdm_active(struct omap_mcpdm * mcpdm)173 static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
174 {
175 	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
176 					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
177 }
178 
179 /*
180  * Configures McPDM uplink, and downlink for audio.
181  * This function should be called before omap_mcpdm_start.
182  */
omap_mcpdm_open_streams(struct omap_mcpdm * mcpdm)183 static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
184 {
185 	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
186 			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
187 			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
188 
189 	/* Enable DN RX1/2 offset cancellation feature, if configured */
190 	if (mcpdm->dn_rx_offset) {
191 		u32 dn_offset = mcpdm->dn_rx_offset;
192 
193 		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
194 		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
195 		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
196 	}
197 
198 	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
199 	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
200 
201 	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
202 			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
203 }
204 
205 /*
206  * Cleans McPDM uplink, and downlink configuration.
207  * This function should be called when the stream is closed.
208  */
omap_mcpdm_close_streams(struct omap_mcpdm * mcpdm)209 static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
210 {
211 	/* Disable irq request generation for downlink */
212 	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
213 			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
214 
215 	/* Disable DMA request generation for downlink */
216 	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
217 
218 	/* Disable irq request generation for uplink */
219 	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
220 			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
221 
222 	/* Disable DMA request generation for uplink */
223 	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
224 
225 	/* Disable RX1/2 offset cancellation */
226 	if (mcpdm->dn_rx_offset)
227 		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
228 }
229 
omap_mcpdm_irq_handler(int irq,void * dev_id)230 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
231 {
232 	struct omap_mcpdm *mcpdm = dev_id;
233 	int irq_status;
234 
235 	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
236 
237 	/* Acknowledge irq event */
238 	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
239 
240 	if (irq_status & MCPDM_DN_IRQ_FULL)
241 		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
242 
243 	if (irq_status & MCPDM_DN_IRQ_EMPTY)
244 		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
245 
246 	if (irq_status & MCPDM_DN_IRQ)
247 		dev_dbg(mcpdm->dev, "DN (playback) write request\n");
248 
249 	if (irq_status & MCPDM_UP_IRQ_FULL)
250 		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
251 
252 	if (irq_status & MCPDM_UP_IRQ_EMPTY)
253 		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
254 
255 	if (irq_status & MCPDM_UP_IRQ)
256 		dev_dbg(mcpdm->dev, "UP (capture) write request\n");
257 
258 	return IRQ_HANDLED;
259 }
260 
omap_mcpdm_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)261 static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
262 				  struct snd_soc_dai *dai)
263 {
264 	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
265 
266 	mutex_lock(&mcpdm->mutex);
267 
268 	if (!dai->active) {
269 		/* Enable watch dog for ES above ES 1.0 to avoid saturation */
270 		if (omap_rev() != OMAP4430_REV_ES1_0) {
271 			u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
272 
273 			omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
274 					 ctrl | MCPDM_WD_EN);
275 		}
276 		omap_mcpdm_open_streams(mcpdm);
277 	}
278 
279 	mutex_unlock(&mcpdm->mutex);
280 
281 	return 0;
282 }
283 
omap_mcpdm_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)284 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
285 				  struct snd_soc_dai *dai)
286 {
287 	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
288 
289 	mutex_lock(&mcpdm->mutex);
290 
291 	if (!dai->active) {
292 		if (omap_mcpdm_active(mcpdm)) {
293 			omap_mcpdm_stop(mcpdm);
294 			omap_mcpdm_close_streams(mcpdm);
295 		}
296 	}
297 
298 	mutex_unlock(&mcpdm->mutex);
299 }
300 
omap_mcpdm_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)301 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
302 				    struct snd_pcm_hw_params *params,
303 				    struct snd_soc_dai *dai)
304 {
305 	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
306 	int stream = substream->stream;
307 	struct omap_pcm_dma_data *dma_data;
308 	int channels;
309 	int link_mask = 0;
310 
311 	channels = params_channels(params);
312 	switch (channels) {
313 	case 5:
314 		if (stream == SNDRV_PCM_STREAM_CAPTURE)
315 			/* up to 3 channels for capture */
316 			return -EINVAL;
317 		link_mask |= 1 << 4;
318 	case 4:
319 		if (stream == SNDRV_PCM_STREAM_CAPTURE)
320 			/* up to 3 channels for capture */
321 			return -EINVAL;
322 		link_mask |= 1 << 3;
323 	case 3:
324 		link_mask |= 1 << 2;
325 	case 2:
326 		link_mask |= 1 << 1;
327 	case 1:
328 		link_mask |= 1 << 0;
329 		break;
330 	default:
331 		/* unsupported number of channels */
332 		return -EINVAL;
333 	}
334 
335 	dma_data = &omap_mcpdm_dai_dma_params[stream];
336 
337 	/* Configure McPDM channels, and DMA packet size */
338 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
339 		mcpdm->dn_channels = link_mask << 3;
340 		dma_data->packet_size =
341 			(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
342 	} else {
343 		mcpdm->up_channels = link_mask << 0;
344 		dma_data->packet_size = mcpdm->up_threshold * channels;
345 	}
346 
347 	snd_soc_dai_set_dma_data(dai, substream, dma_data);
348 
349 	return 0;
350 }
351 
omap_mcpdm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)352 static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
353 				  struct snd_soc_dai *dai)
354 {
355 	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
356 
357 	if (!omap_mcpdm_active(mcpdm)) {
358 		omap_mcpdm_start(mcpdm);
359 		omap_mcpdm_reg_dump(mcpdm);
360 	}
361 
362 	return 0;
363 }
364 
365 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
366 	.startup	= omap_mcpdm_dai_startup,
367 	.shutdown	= omap_mcpdm_dai_shutdown,
368 	.hw_params	= omap_mcpdm_dai_hw_params,
369 	.prepare	= omap_mcpdm_prepare,
370 };
371 
omap_mcpdm_probe(struct snd_soc_dai * dai)372 static int omap_mcpdm_probe(struct snd_soc_dai *dai)
373 {
374 	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
375 	int ret;
376 
377 	pm_runtime_enable(mcpdm->dev);
378 
379 	/* Disable lines while request is ongoing */
380 	pm_runtime_get_sync(mcpdm->dev);
381 	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
382 
383 	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
384 				0, "McPDM", (void *)mcpdm);
385 
386 	pm_runtime_put_sync(mcpdm->dev);
387 
388 	if (ret) {
389 		dev_err(mcpdm->dev, "Request for IRQ failed\n");
390 		pm_runtime_disable(mcpdm->dev);
391 	}
392 
393 	/* Configure McPDM threshold values */
394 	mcpdm->dn_threshold = 2;
395 	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
396 	return ret;
397 }
398 
omap_mcpdm_remove(struct snd_soc_dai * dai)399 static int omap_mcpdm_remove(struct snd_soc_dai *dai)
400 {
401 	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
402 
403 	free_irq(mcpdm->irq, (void *)mcpdm);
404 	pm_runtime_disable(mcpdm->dev);
405 
406 	return 0;
407 }
408 
409 #define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
410 #define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE
411 
412 static struct snd_soc_dai_driver omap_mcpdm_dai = {
413 	.probe = omap_mcpdm_probe,
414 	.remove = omap_mcpdm_remove,
415 	.probe_order = SND_SOC_COMP_ORDER_LATE,
416 	.remove_order = SND_SOC_COMP_ORDER_EARLY,
417 	.playback = {
418 		.channels_min = 1,
419 		.channels_max = 5,
420 		.rates = OMAP_MCPDM_RATES,
421 		.formats = OMAP_MCPDM_FORMATS,
422 		.sig_bits = 24,
423 	},
424 	.capture = {
425 		.channels_min = 1,
426 		.channels_max = 3,
427 		.rates = OMAP_MCPDM_RATES,
428 		.formats = OMAP_MCPDM_FORMATS,
429 		.sig_bits = 24,
430 	},
431 	.ops = &omap_mcpdm_dai_ops,
432 };
433 
omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime * rtd,u8 rx1,u8 rx2)434 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
435 				    u8 rx1, u8 rx2)
436 {
437 	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
438 
439 	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
440 }
441 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
442 
asoc_mcpdm_probe(struct platform_device * pdev)443 static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
444 {
445 	struct omap_mcpdm *mcpdm;
446 	struct resource *res;
447 	int ret = 0;
448 
449 	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
450 	if (!mcpdm)
451 		return -ENOMEM;
452 
453 	platform_set_drvdata(pdev, mcpdm);
454 
455 	mutex_init(&mcpdm->mutex);
456 
457 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 	if (res == NULL) {
459 		dev_err(&pdev->dev, "no resource\n");
460 		goto err_res;
461 	}
462 
463 	if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
464 		ret = -EBUSY;
465 		goto err_res;
466 	}
467 
468 	mcpdm->io_base = ioremap(res->start, resource_size(res));
469 	if (!mcpdm->io_base) {
470 		ret = -ENOMEM;
471 		goto err_iomap;
472 	}
473 
474 	mcpdm->irq = platform_get_irq(pdev, 0);
475 	if (mcpdm->irq < 0) {
476 		ret = mcpdm->irq;
477 		goto err_irq;
478 	}
479 
480 	mcpdm->dev = &pdev->dev;
481 
482 	ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
483 	if (!ret)
484 		return 0;
485 
486 err_irq:
487 	iounmap(mcpdm->io_base);
488 err_iomap:
489 	release_mem_region(res->start, resource_size(res));
490 err_res:
491 	kfree(mcpdm);
492 	return ret;
493 }
494 
asoc_mcpdm_remove(struct platform_device * pdev)495 static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
496 {
497 	struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
498 	struct resource *res;
499 
500 	snd_soc_unregister_dai(&pdev->dev);
501 
502 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
503 	iounmap(mcpdm->io_base);
504 	release_mem_region(res->start, resource_size(res));
505 
506 	kfree(mcpdm);
507 	return 0;
508 }
509 
510 static struct platform_driver asoc_mcpdm_driver = {
511 	.driver = {
512 		.name	= "omap-mcpdm",
513 		.owner	= THIS_MODULE,
514 	},
515 
516 	.probe	= asoc_mcpdm_probe,
517 	.remove	= __devexit_p(asoc_mcpdm_remove),
518 };
519 
520 module_platform_driver(asoc_mcpdm_driver);
521 
522 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
523 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
524 MODULE_LICENSE("GPL");
525