1 /*
2  * wm8978.c  --  WM8978 ALSA SoC Audio Codec driver
3  *
4  * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5  * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
6  * Copyright 2006-2009 Wolfson Microelectronics PLC.
7  * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <asm/div64.h>
30 
31 #include "wm8978.h"
32 
33 static const struct reg_default wm8978_reg_defaults[] = {
34 	{ 1, 0x0000 },
35 	{ 2, 0x0000 },
36 	{ 3, 0x0000 },
37 	{ 4, 0x0050 },
38 	{ 5, 0x0000 },
39 	{ 6, 0x0140 },
40 	{ 7, 0x0000 },
41 	{ 8, 0x0000 },
42 	{ 9, 0x0000 },
43 	{ 10, 0x0000 },
44 	{ 11, 0x00ff },
45 	{ 12, 0x00ff },
46 	{ 13, 0x0000 },
47 	{ 14, 0x0100 },
48 	{ 15, 0x00ff },
49 	{ 16, 0x00ff },
50 	{ 17, 0x0000 },
51 	{ 18, 0x012c },
52 	{ 19, 0x002c },
53 	{ 20, 0x002c },
54 	{ 21, 0x002c },
55 	{ 22, 0x002c },
56 	{ 23, 0x0000 },
57 	{ 24, 0x0032 },
58 	{ 25, 0x0000 },
59 	{ 26, 0x0000 },
60 	{ 27, 0x0000 },
61 	{ 28, 0x0000 },
62 	{ 29, 0x0000 },
63 	{ 30, 0x0000 },
64 	{ 31, 0x0000 },
65 	{ 32, 0x0038 },
66 	{ 33, 0x000b },
67 	{ 34, 0x0032 },
68 	{ 35, 0x0000 },
69 	{ 36, 0x0008 },
70 	{ 37, 0x000c },
71 	{ 38, 0x0093 },
72 	{ 39, 0x00e9 },
73 	{ 40, 0x0000 },
74 	{ 41, 0x0000 },
75 	{ 42, 0x0000 },
76 	{ 43, 0x0000 },
77 	{ 44, 0x0033 },
78 	{ 45, 0x0010 },
79 	{ 46, 0x0010 },
80 	{ 47, 0x0100 },
81 	{ 48, 0x0100 },
82 	{ 49, 0x0002 },
83 	{ 50, 0x0001 },
84 	{ 51, 0x0001 },
85 	{ 52, 0x0039 },
86 	{ 53, 0x0039 },
87 	{ 54, 0x0039 },
88 	{ 55, 0x0039 },
89 	{ 56, 0x0001 },
90 	{ 57, 0x0001 },
91 };
92 
wm8978_volatile(struct device * dev,unsigned int reg)93 static bool wm8978_volatile(struct device *dev, unsigned int reg)
94 {
95 	return reg == WM8978_RESET;
96 }
97 
98 /* codec private data */
99 struct wm8978_priv {
100 	struct regmap *regmap;
101 	unsigned int f_pllout;
102 	unsigned int f_mclk;
103 	unsigned int f_256fs;
104 	unsigned int f_opclk;
105 	int mclk_idx;
106 	enum wm8978_sysclk_src sysclk;
107 };
108 
109 static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
110 static const char *wm8978_eqmode[] = {"Capture", "Playback"};
111 static const char *wm8978_bw[] = {"Narrow", "Wide"};
112 static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
113 static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
114 static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
115 static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
116 static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
117 static const char *wm8978_alc3[] = {"ALC", "Limiter"};
118 static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
119 
120 static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
121 				  wm8978_companding);
122 static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
123 				  wm8978_companding);
124 static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
125 static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
126 static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
127 static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
128 static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
129 static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
130 static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
131 static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
132 static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
133 static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
134 static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
135 
136 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
137 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
138 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
139 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
140 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
141 static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
142 
143 static const struct snd_kcontrol_new wm8978_snd_controls[] = {
144 
145 	SOC_SINGLE("Digital Loopback Switch",
146 		WM8978_COMPANDING_CONTROL, 0, 1, 0),
147 
148 	SOC_ENUM("ADC Companding", adc_compand),
149 	SOC_ENUM("DAC Companding", dac_compand),
150 
151 	SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
152 
153 	SOC_DOUBLE_R_TLV("PCM Volume",
154 		WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
155 		0, 255, 0, digital_tlv),
156 
157 	SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
158 	SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
159 	SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
160 
161 	SOC_DOUBLE_R_TLV("ADC Volume",
162 		WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
163 		0, 255, 0, digital_tlv),
164 
165 	SOC_ENUM("Equaliser Function", eqmode),
166 	SOC_ENUM("EQ1 Cut Off", eq1),
167 	SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1,  0, 24, 1, eq_tlv),
168 
169 	SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw),
170 	SOC_ENUM("EQ2 Cut Off", eq2),
171 	SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2,  0, 24, 1, eq_tlv),
172 
173 	SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw),
174 	SOC_ENUM("EQ3 Cut Off", eq3),
175 	SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3,  0, 24, 1, eq_tlv),
176 
177 	SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw),
178 	SOC_ENUM("EQ4 Cut Off", eq4),
179 	SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4,  0, 24, 1, eq_tlv),
180 
181 	SOC_ENUM("EQ5 Cut Off", eq5),
182 	SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
183 
184 	SOC_SINGLE("DAC Playback Limiter Switch",
185 		WM8978_DAC_LIMITER_1, 8, 1, 0),
186 	SOC_SINGLE("DAC Playback Limiter Decay",
187 		WM8978_DAC_LIMITER_1, 4, 15, 0),
188 	SOC_SINGLE("DAC Playback Limiter Attack",
189 		WM8978_DAC_LIMITER_1, 0, 15, 0),
190 
191 	SOC_SINGLE("DAC Playback Limiter Threshold",
192 		WM8978_DAC_LIMITER_2, 4, 7, 0),
193 	SOC_SINGLE_TLV("DAC Playback Limiter Volume",
194 		WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
195 
196 	SOC_ENUM("ALC Enable Switch", alc1),
197 	SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
198 	SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
199 
200 	SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
201 	SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
202 
203 	SOC_ENUM("ALC Capture Mode", alc3),
204 	SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
205 	SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
206 
207 	SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
208 	SOC_SINGLE("ALC Capture Noise Gate Threshold",
209 		WM8978_NOISE_GATE, 0, 7, 0),
210 
211 	SOC_DOUBLE_R("Capture PGA ZC Switch",
212 		WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
213 		7, 1, 0),
214 
215 	/* OUT1 - Headphones */
216 	SOC_DOUBLE_R("Headphone Playback ZC Switch",
217 		WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
218 
219 	SOC_DOUBLE_R_TLV("Headphone Playback Volume",
220 		WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
221 		0, 63, 0, spk_tlv),
222 
223 	/* OUT2 - Speakers */
224 	SOC_DOUBLE_R("Speaker Playback ZC Switch",
225 		WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
226 
227 	SOC_DOUBLE_R_TLV("Speaker Playback Volume",
228 		WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
229 		0, 63, 0, spk_tlv),
230 
231 	/* OUT3/4 - Line Output */
232 	SOC_DOUBLE_R("Line Playback Switch",
233 		WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
234 
235 	/* Mixer #3: Boost (Input) mixer */
236 	SOC_DOUBLE_R("PGA Boost (+20dB)",
237 		WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
238 		8, 1, 0),
239 	SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
240 		WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
241 		4, 7, 0, boost_tlv),
242 	SOC_DOUBLE_R_TLV("Aux Boost Volume",
243 		WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
244 		0, 7, 0, boost_tlv),
245 
246 	/* Input PGA volume */
247 	SOC_DOUBLE_R_TLV("Input PGA Volume",
248 		WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
249 		0, 63, 0, inpga_tlv),
250 
251 	/* Headphone */
252 	SOC_DOUBLE_R("Headphone Switch",
253 		WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
254 
255 	/* Speaker */
256 	SOC_DOUBLE_R("Speaker Switch",
257 		WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
258 
259 	/* DAC / ADC oversampling */
260 	SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
261 		   5, 1, 0),
262 	SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
263 		   5, 1, 0),
264 };
265 
266 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
267 static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
268 	SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
269 	SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
270 	SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
271 };
272 
273 static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
274 	SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
275 	SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
276 	SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
277 };
278 
279 /* OUT3/OUT4 Mixer not implemented */
280 
281 /* Mixer #2: Input PGA Mute */
282 static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
283 	SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
284 	SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
285 	SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
286 };
287 static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
288 	SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
289 	SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
290 	SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
291 };
292 
293 static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
294 	SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
295 			 WM8978_POWER_MANAGEMENT_3, 0, 0),
296 	SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
297 			 WM8978_POWER_MANAGEMENT_3, 1, 0),
298 	SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
299 			 WM8978_POWER_MANAGEMENT_2, 0, 0),
300 	SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
301 			 WM8978_POWER_MANAGEMENT_2, 1, 0),
302 
303 	/* Mixer #1: OUT1,2 */
304 	SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
305 			2, 0, wm8978_left_out_mixer),
306 	SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
307 			3, 0, wm8978_right_out_mixer),
308 
309 	SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
310 			2, 0, wm8978_left_input_mixer),
311 	SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
312 			3, 0, wm8978_right_input_mixer),
313 
314 	SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
315 			 4, 0, NULL, 0),
316 	SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
317 			 5, 0, NULL, 0),
318 
319 	SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
320 			 6, 1, NULL, 0),
321 	SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
322 			 6, 1, NULL, 0),
323 
324 	SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
325 			 7, 0, NULL, 0),
326 	SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
327 			 8, 0, NULL, 0),
328 
329 	SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
330 			 6, 0, NULL, 0),
331 	SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
332 			 5, 0, NULL, 0),
333 
334 	SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
335 			   8, 0, NULL, 0),
336 
337 	SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
338 
339 	SND_SOC_DAPM_INPUT("LMICN"),
340 	SND_SOC_DAPM_INPUT("LMICP"),
341 	SND_SOC_DAPM_INPUT("RMICN"),
342 	SND_SOC_DAPM_INPUT("RMICP"),
343 	SND_SOC_DAPM_INPUT("LAUX"),
344 	SND_SOC_DAPM_INPUT("RAUX"),
345 	SND_SOC_DAPM_INPUT("L2"),
346 	SND_SOC_DAPM_INPUT("R2"),
347 	SND_SOC_DAPM_OUTPUT("LHP"),
348 	SND_SOC_DAPM_OUTPUT("RHP"),
349 	SND_SOC_DAPM_OUTPUT("LSPK"),
350 	SND_SOC_DAPM_OUTPUT("RSPK"),
351 };
352 
353 static const struct snd_soc_dapm_route wm8978_dapm_routes[] = {
354 	/* Output mixer */
355 	{"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
356 	{"Right Output Mixer", "Aux Playback Switch", "RAUX"},
357 	{"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
358 
359 	{"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
360 	{"Left Output Mixer", "Aux Playback Switch", "LAUX"},
361 	{"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
362 
363 	/* Outputs */
364 	{"Right Headphone Out", NULL, "Right Output Mixer"},
365 	{"RHP", NULL, "Right Headphone Out"},
366 
367 	{"Left Headphone Out", NULL, "Left Output Mixer"},
368 	{"LHP", NULL, "Left Headphone Out"},
369 
370 	{"Right Speaker Out", NULL, "Right Output Mixer"},
371 	{"RSPK", NULL, "Right Speaker Out"},
372 
373 	{"Left Speaker Out", NULL, "Left Output Mixer"},
374 	{"LSPK", NULL, "Left Speaker Out"},
375 
376 	/* Boost Mixer */
377 	{"Right ADC", NULL, "Right Boost Mixer"},
378 
379 	{"Right Boost Mixer", NULL, "RAUX"},
380 	{"Right Boost Mixer", NULL, "Right Capture PGA"},
381 	{"Right Boost Mixer", NULL, "R2"},
382 
383 	{"Left ADC", NULL, "Left Boost Mixer"},
384 
385 	{"Left Boost Mixer", NULL, "LAUX"},
386 	{"Left Boost Mixer", NULL, "Left Capture PGA"},
387 	{"Left Boost Mixer", NULL, "L2"},
388 
389 	/* Input PGA */
390 	{"Right Capture PGA", NULL, "Right Input Mixer"},
391 	{"Left Capture PGA", NULL, "Left Input Mixer"},
392 
393 	{"Right Input Mixer", "R2 Switch", "R2"},
394 	{"Right Input Mixer", "MicN Switch", "RMICN"},
395 	{"Right Input Mixer", "MicP Switch", "RMICP"},
396 
397 	{"Left Input Mixer", "L2 Switch", "L2"},
398 	{"Left Input Mixer", "MicN Switch", "LMICN"},
399 	{"Left Input Mixer", "MicP Switch", "LMICP"},
400 };
401 
402 /* PLL divisors */
403 struct wm8978_pll_div {
404 	u32 k;
405 	u8 n;
406 	u8 div2;
407 };
408 
409 #define FIXED_PLL_SIZE (1 << 24)
410 
pll_factors(struct snd_soc_codec * codec,struct wm8978_pll_div * pll_div,unsigned int target,unsigned int source)411 static void pll_factors(struct snd_soc_codec *codec,
412 		struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
413 {
414 	u64 k_part;
415 	unsigned int k, n_div, n_mod;
416 
417 	n_div = target / source;
418 	if (n_div < 6) {
419 		source >>= 1;
420 		pll_div->div2 = 1;
421 		n_div = target / source;
422 	} else {
423 		pll_div->div2 = 0;
424 	}
425 
426 	if (n_div < 6 || n_div > 12)
427 		dev_warn(codec->dev,
428 			 "WM8978 N value exceeds recommended range! N = %u\n",
429 			 n_div);
430 
431 	pll_div->n = n_div;
432 	n_mod = target - source * n_div;
433 	k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
434 
435 	do_div(k_part, source);
436 
437 	k = k_part & 0xFFFFFFFF;
438 
439 	pll_div->k = k;
440 }
441 
442 /* MCLK dividers */
443 static const int mclk_numerator[]	= {1, 3, 2, 3, 4, 6, 8, 12};
444 static const int mclk_denominator[]	= {1, 2, 1, 1, 1, 1, 1, 1};
445 
446 /*
447  * find index >= idx, such that, for a given f_out,
448  * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
449  * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
450  * generalised for f_opclk with suitable coefficient arrays, but currently
451  * the OPCLK divisor is calculated directly, not iteratively.
452  */
wm8978_enum_mclk(unsigned int f_out,unsigned int f_mclk,unsigned int * f_pllout)453 static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
454 			    unsigned int *f_pllout)
455 {
456 	int i;
457 
458 	for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
459 		unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
460 			mclk_denominator[i];
461 		if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
462 			*f_pllout = f_pllout_x4 / 4;
463 			return i;
464 		}
465 	}
466 
467 	return -EINVAL;
468 }
469 
470 /*
471  * Calculate internal frequencies and dividers, according to Figure 40
472  * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
473  */
wm8978_configure_pll(struct snd_soc_codec * codec)474 static int wm8978_configure_pll(struct snd_soc_codec *codec)
475 {
476 	struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
477 	struct wm8978_pll_div pll_div;
478 	unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
479 		f_256fs = wm8978->f_256fs;
480 	unsigned int f2;
481 
482 	if (!f_mclk)
483 		return -EINVAL;
484 
485 	if (f_opclk) {
486 		unsigned int opclk_div;
487 		/* Cannot set up MCLK divider now, do later */
488 		wm8978->mclk_idx = -1;
489 
490 		/*
491 		 * The user needs OPCLK. Choose OPCLKDIV to put
492 		 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
493 		 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
494 		 * prescale = 1, or prescale = 2. Prescale is calculated inside
495 		 * pll_factors(). We have to select f_PLLOUT, such that
496 		 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
497 		 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
498 		 */
499 		if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
500 			return -EINVAL;
501 
502 		if (4 * f_opclk < 3 * f_mclk)
503 			/* Have to use OPCLKDIV */
504 			opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
505 		else
506 			opclk_div = 1;
507 
508 		dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
509 
510 		snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
511 				    (opclk_div - 1) << 4);
512 
513 		wm8978->f_pllout = f_opclk * opclk_div;
514 	} else if (f_256fs) {
515 		/*
516 		 * Not using OPCLK, but PLL is used for the codec, choose R:
517 		 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
518 		 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
519 		 * prescale = 1, or prescale = 2. Prescale is calculated inside
520 		 * pll_factors(). We have to select f_PLLOUT, such that
521 		 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
522 		 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
523 		 * must be 3.781MHz <= f_MCLK <= 32.768MHz
524 		 */
525 		int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
526 		if (idx < 0)
527 			return idx;
528 
529 		wm8978->mclk_idx = idx;
530 
531 		/* GPIO1 into default mode as input - before configuring PLL */
532 		snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
533 	} else {
534 		return -EINVAL;
535 	}
536 
537 	f2 = wm8978->f_pllout * 4;
538 
539 	dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
540 		wm8978->f_mclk, wm8978->f_pllout);
541 
542 	pll_factors(codec, &pll_div, f2, wm8978->f_mclk);
543 
544 	dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
545 		__func__, pll_div.n, pll_div.k, pll_div.div2);
546 
547 	/* Turn PLL off for configuration... */
548 	snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
549 
550 	snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
551 	snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18);
552 	snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
553 	snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff);
554 
555 	/* ...and on again */
556 	snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
557 
558 	if (f_opclk)
559 		/* Output PLL (OPCLK) to GPIO1 */
560 		snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4);
561 
562 	return 0;
563 }
564 
565 /*
566  * Configure WM8978 clock dividers.
567  */
wm8978_set_dai_clkdiv(struct snd_soc_dai * codec_dai,int div_id,int div)568 static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
569 				 int div_id, int div)
570 {
571 	struct snd_soc_codec *codec = codec_dai->codec;
572 	struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
573 	int ret = 0;
574 
575 	switch (div_id) {
576 	case WM8978_OPCLKRATE:
577 		wm8978->f_opclk = div;
578 
579 		if (wm8978->f_mclk)
580 			/*
581 			 * We know the MCLK frequency, the user has requested
582 			 * OPCLK, configure the PLL based on that and start it
583 			 * and OPCLK immediately. We will configure PLL to match
584 			 * user-requested OPCLK frquency as good as possible.
585 			 * In fact, it is likely, that matching the sampling
586 			 * rate, when it becomes known, is more important, and
587 			 * we will not be reconfiguring PLL then, because we
588 			 * must not interrupt OPCLK. But it should be fine,
589 			 * because typically the user will request OPCLK to run
590 			 * at 256fs or 512fs, and for these cases we will also
591 			 * find an exact MCLK divider configuration - it will
592 			 * be equal to or double the OPCLK divisor.
593 			 */
594 			ret = wm8978_configure_pll(codec);
595 		break;
596 	case WM8978_BCLKDIV:
597 		if (div & ~0x1c)
598 			return -EINVAL;
599 		snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div);
600 		break;
601 	default:
602 		return -EINVAL;
603 	}
604 
605 	dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
606 
607 	return ret;
608 }
609 
610 /*
611  * @freq:	when .set_pll() us not used, freq is codec MCLK input frequency
612  */
wm8978_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)613 static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
614 				 unsigned int freq, int dir)
615 {
616 	struct snd_soc_codec *codec = codec_dai->codec;
617 	struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
618 	int ret = 0;
619 
620 	dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
621 
622 	if (freq) {
623 		wm8978->f_mclk = freq;
624 
625 		/* Even if MCLK is used for system clock, might have to drive OPCLK */
626 		if (wm8978->f_opclk)
627 			ret = wm8978_configure_pll(codec);
628 
629 		/* Our sysclk is fixed to 256 * fs, will configure in .hw_params()  */
630 
631 		if (!ret)
632 			wm8978->sysclk = clk_id;
633 	}
634 
635 	if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
636 		/* Clock CODEC directly from MCLK */
637 		snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
638 
639 		/* GPIO1 into default mode as input - before configuring PLL */
640 		snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
641 
642 		/* Turn off PLL */
643 		snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
644 		wm8978->sysclk = WM8978_MCLK;
645 		wm8978->f_pllout = 0;
646 		wm8978->f_opclk = 0;
647 	}
648 
649 	return ret;
650 }
651 
652 /*
653  * Set ADC and Voice DAC format.
654  */
wm8978_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)655 static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
656 {
657 	struct snd_soc_codec *codec = codec_dai->codec;
658 	/*
659 	 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
660 	 * Data Format mask = 0x18: all will be calculated anew
661 	 */
662 	u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198;
663 	u16 clk = snd_soc_read(codec, WM8978_CLOCKING);
664 
665 	dev_dbg(codec->dev, "%s\n", __func__);
666 
667 	/* set master/slave audio interface */
668 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
669 	case SND_SOC_DAIFMT_CBM_CFM:
670 		clk |= 1;
671 		break;
672 	case SND_SOC_DAIFMT_CBS_CFS:
673 		clk &= ~1;
674 		break;
675 	default:
676 		return -EINVAL;
677 	}
678 
679 	/* interface format */
680 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
681 	case SND_SOC_DAIFMT_I2S:
682 		iface |= 0x10;
683 		break;
684 	case SND_SOC_DAIFMT_RIGHT_J:
685 		break;
686 	case SND_SOC_DAIFMT_LEFT_J:
687 		iface |= 0x8;
688 		break;
689 	case SND_SOC_DAIFMT_DSP_A:
690 		iface |= 0x18;
691 		break;
692 	default:
693 		return -EINVAL;
694 	}
695 
696 	/* clock inversion */
697 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
698 	case SND_SOC_DAIFMT_NB_NF:
699 		break;
700 	case SND_SOC_DAIFMT_IB_IF:
701 		iface |= 0x180;
702 		break;
703 	case SND_SOC_DAIFMT_IB_NF:
704 		iface |= 0x100;
705 		break;
706 	case SND_SOC_DAIFMT_NB_IF:
707 		iface |= 0x80;
708 		break;
709 	default:
710 		return -EINVAL;
711 	}
712 
713 	snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface);
714 	snd_soc_write(codec, WM8978_CLOCKING, clk);
715 
716 	return 0;
717 }
718 
719 /*
720  * Set PCM DAI bit size and sample rate.
721  */
wm8978_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)722 static int wm8978_hw_params(struct snd_pcm_substream *substream,
723 			    struct snd_pcm_hw_params *params,
724 			    struct snd_soc_dai *dai)
725 {
726 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
727 	struct snd_soc_codec *codec = rtd->codec;
728 	struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
729 	/* Word length mask = 0x60 */
730 	u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
731 	/* Sampling rate mask = 0xe (for filters) */
732 	u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe;
733 	u16 clking = snd_soc_read(codec, WM8978_CLOCKING);
734 	enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
735 		WM8978_PLL : WM8978_MCLK;
736 	unsigned int f_sel, diff, diff_best = INT_MAX;
737 	int i, best = 0;
738 
739 	if (!wm8978->f_mclk)
740 		return -EINVAL;
741 
742 	/* bit size */
743 	switch (params_format(params)) {
744 	case SNDRV_PCM_FORMAT_S16_LE:
745 		break;
746 	case SNDRV_PCM_FORMAT_S20_3LE:
747 		iface_ctl |= 0x20;
748 		break;
749 	case SNDRV_PCM_FORMAT_S24_LE:
750 		iface_ctl |= 0x40;
751 		break;
752 	case SNDRV_PCM_FORMAT_S32_LE:
753 		iface_ctl |= 0x60;
754 		break;
755 	}
756 
757 	/* filter coefficient */
758 	switch (params_rate(params)) {
759 	case 8000:
760 		add_ctl |= 0x5 << 1;
761 		break;
762 	case 11025:
763 		add_ctl |= 0x4 << 1;
764 		break;
765 	case 16000:
766 		add_ctl |= 0x3 << 1;
767 		break;
768 	case 22050:
769 		add_ctl |= 0x2 << 1;
770 		break;
771 	case 32000:
772 		add_ctl |= 0x1 << 1;
773 		break;
774 	case 44100:
775 	case 48000:
776 		break;
777 	}
778 
779 	/* Sampling rate is known now, can configure the MCLK divider */
780 	wm8978->f_256fs = params_rate(params) * 256;
781 
782 	if (wm8978->sysclk == WM8978_MCLK) {
783 		wm8978->mclk_idx = -1;
784 		f_sel = wm8978->f_mclk;
785 	} else {
786 		if (!wm8978->f_opclk) {
787 			/* We only enter here, if OPCLK is not used */
788 			int ret = wm8978_configure_pll(codec);
789 			if (ret < 0)
790 				return ret;
791 		}
792 		f_sel = wm8978->f_pllout;
793 	}
794 
795 	if (wm8978->mclk_idx < 0) {
796 		/* Either MCLK is used directly, or OPCLK is used */
797 		if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
798 			return -EINVAL;
799 
800 		for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
801 			diff = abs(wm8978->f_256fs * 3 -
802 				   f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
803 
804 			if (diff < diff_best) {
805 				diff_best = diff;
806 				best = i;
807 			}
808 
809 			if (!diff)
810 				break;
811 		}
812 	} else {
813 		/* OPCLK not used, codec driven by PLL */
814 		best = wm8978->mclk_idx;
815 		diff = 0;
816 	}
817 
818 	if (diff)
819 		dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n",
820 			f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
821 			wm8978->sysclk == WM8978_MCLK ?
822 			", consider using PLL" : "");
823 
824 	dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__,
825 		params_format(params), params_rate(params), best);
826 
827 	/* MCLK divisor mask = 0xe0 */
828 	snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5);
829 
830 	snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl);
831 	snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl);
832 
833 	if (wm8978->sysclk != current_clk_id) {
834 		if (wm8978->sysclk == WM8978_PLL)
835 			/* Run CODEC from PLL instead of MCLK */
836 			snd_soc_update_bits(codec, WM8978_CLOCKING,
837 					    0x100, 0x100);
838 		else
839 			/* Clock CODEC directly from MCLK */
840 			snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
841 	}
842 
843 	return 0;
844 }
845 
wm8978_mute(struct snd_soc_dai * dai,int mute)846 static int wm8978_mute(struct snd_soc_dai *dai, int mute)
847 {
848 	struct snd_soc_codec *codec = dai->codec;
849 
850 	dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
851 
852 	if (mute)
853 		snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40);
854 	else
855 		snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0);
856 
857 	return 0;
858 }
859 
wm8978_set_bias_level(struct snd_soc_codec * codec,enum snd_soc_bias_level level)860 static int wm8978_set_bias_level(struct snd_soc_codec *codec,
861 				 enum snd_soc_bias_level level)
862 {
863 	u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3;
864 
865 	switch (level) {
866 	case SND_SOC_BIAS_ON:
867 	case SND_SOC_BIAS_PREPARE:
868 		power1 |= 1;  /* VMID 75k */
869 		snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
870 		break;
871 	case SND_SOC_BIAS_STANDBY:
872 		/* bit 3: enable bias, bit 2: enable I/O tie off buffer */
873 		power1 |= 0xc;
874 
875 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
876 			/* Initial cap charge at VMID 5k */
877 			snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
878 				      power1 | 0x3);
879 			mdelay(100);
880 		}
881 
882 		power1 |= 0x2;  /* VMID 500k */
883 		snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
884 		break;
885 	case SND_SOC_BIAS_OFF:
886 		/* Preserve PLL - OPCLK may be used by someone */
887 		snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
888 		snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0);
889 		snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0);
890 		break;
891 	}
892 
893 	dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
894 
895 	codec->dapm.bias_level = level;
896 	return 0;
897 }
898 
899 #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
900 	SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
901 
902 static const struct snd_soc_dai_ops wm8978_dai_ops = {
903 	.hw_params	= wm8978_hw_params,
904 	.digital_mute	= wm8978_mute,
905 	.set_fmt	= wm8978_set_dai_fmt,
906 	.set_clkdiv	= wm8978_set_dai_clkdiv,
907 	.set_sysclk	= wm8978_set_dai_sysclk,
908 };
909 
910 /* Also supports 12kHz */
911 static struct snd_soc_dai_driver wm8978_dai = {
912 	.name = "wm8978-hifi",
913 	.playback = {
914 		.stream_name = "Playback",
915 		.channels_min = 1,
916 		.channels_max = 2,
917 		.rates = SNDRV_PCM_RATE_8000_48000,
918 		.formats = WM8978_FORMATS,
919 	},
920 	.capture = {
921 		.stream_name = "Capture",
922 		.channels_min = 1,
923 		.channels_max = 2,
924 		.rates = SNDRV_PCM_RATE_8000_48000,
925 		.formats = WM8978_FORMATS,
926 	},
927 	.ops = &wm8978_dai_ops,
928 };
929 
wm8978_suspend(struct snd_soc_codec * codec)930 static int wm8978_suspend(struct snd_soc_codec *codec)
931 {
932 	struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
933 
934 	wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
935 	/* Also switch PLL off */
936 	snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
937 
938 	regcache_mark_dirty(wm8978->regmap);
939 
940 	return 0;
941 }
942 
wm8978_resume(struct snd_soc_codec * codec)943 static int wm8978_resume(struct snd_soc_codec *codec)
944 {
945 	struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
946 
947 	/* Sync reg_cache with the hardware */
948 	regcache_sync(wm8978->regmap);
949 
950 	wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
951 
952 	if (wm8978->f_pllout)
953 		/* Switch PLL on */
954 		snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
955 
956 	return 0;
957 }
958 
959 /*
960  * These registers contain an "update" bit - bit 8. This means, for example,
961  * that one can write new DAC digital volume for both channels, but only when
962  * the update bit is set, will also the volume be updated - simultaneously for
963  * both channels.
964  */
965 static const int update_reg[] = {
966 	WM8978_LEFT_DAC_DIGITAL_VOLUME,
967 	WM8978_RIGHT_DAC_DIGITAL_VOLUME,
968 	WM8978_LEFT_ADC_DIGITAL_VOLUME,
969 	WM8978_RIGHT_ADC_DIGITAL_VOLUME,
970 	WM8978_LEFT_INP_PGA_CONTROL,
971 	WM8978_RIGHT_INP_PGA_CONTROL,
972 	WM8978_LOUT1_HP_CONTROL,
973 	WM8978_ROUT1_HP_CONTROL,
974 	WM8978_LOUT2_SPK_CONTROL,
975 	WM8978_ROUT2_SPK_CONTROL,
976 };
977 
wm8978_probe(struct snd_soc_codec * codec)978 static int wm8978_probe(struct snd_soc_codec *codec)
979 {
980 	struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
981 	int ret = 0, i;
982 
983 	/*
984 	 * Set default system clock to PLL, it is more precise, this is also the
985 	 * default hardware setting
986 	 */
987 	wm8978->sysclk = WM8978_PLL;
988 	codec->control_data = wm8978->regmap;
989 	ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
990 	if (ret < 0) {
991 		dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
992 		return ret;
993 	}
994 
995 	/*
996 	 * Set the update bit in all registers, that have one. This way all
997 	 * writes to those registers will also cause the update bit to be
998 	 * written.
999 	 */
1000 	for (i = 0; i < ARRAY_SIZE(update_reg); i++)
1001 		snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100);
1002 
1003 	wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1004 
1005 	return 0;
1006 }
1007 
1008 /* power down chip */
wm8978_remove(struct snd_soc_codec * codec)1009 static int wm8978_remove(struct snd_soc_codec *codec)
1010 {
1011 	wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
1012 	return 0;
1013 }
1014 
1015 static struct snd_soc_codec_driver soc_codec_dev_wm8978 = {
1016 	.probe =	wm8978_probe,
1017 	.remove =	wm8978_remove,
1018 	.suspend =	wm8978_suspend,
1019 	.resume =	wm8978_resume,
1020 	.set_bias_level = wm8978_set_bias_level,
1021 
1022 	.controls = wm8978_snd_controls,
1023 	.num_controls = ARRAY_SIZE(wm8978_snd_controls),
1024 	.dapm_widgets = wm8978_dapm_widgets,
1025 	.num_dapm_widgets = ARRAY_SIZE(wm8978_dapm_widgets),
1026 	.dapm_routes = wm8978_dapm_routes,
1027 	.num_dapm_routes = ARRAY_SIZE(wm8978_dapm_routes),
1028 };
1029 
1030 static const struct regmap_config wm8978_regmap_config = {
1031 	.reg_bits = 7,
1032 	.val_bits = 9,
1033 
1034 	.max_register = WM8978_MAX_REGISTER,
1035 	.volatile_reg = wm8978_volatile,
1036 
1037 	.cache_type = REGCACHE_RBTREE,
1038 	.reg_defaults = wm8978_reg_defaults,
1039 	.num_reg_defaults = ARRAY_SIZE(wm8978_reg_defaults),
1040 };
1041 
wm8978_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1042 static __devinit int wm8978_i2c_probe(struct i2c_client *i2c,
1043 				      const struct i2c_device_id *id)
1044 {
1045 	struct wm8978_priv *wm8978;
1046 	int ret;
1047 
1048 	wm8978 = devm_kzalloc(&i2c->dev, sizeof(struct wm8978_priv),
1049 			      GFP_KERNEL);
1050 	if (wm8978 == NULL)
1051 		return -ENOMEM;
1052 
1053 	wm8978->regmap = regmap_init_i2c(i2c, &wm8978_regmap_config);
1054 	if (IS_ERR(wm8978->regmap)) {
1055 		ret = PTR_ERR(wm8978->regmap);
1056 		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1057 		return ret;
1058 	}
1059 
1060 	i2c_set_clientdata(i2c, wm8978);
1061 
1062 	/* Reset the codec */
1063 	ret = regmap_write(wm8978->regmap, WM8978_RESET, 0);
1064 	if (ret != 0) {
1065 		dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
1066 		goto err;
1067 	}
1068 
1069 	ret = snd_soc_register_codec(&i2c->dev,
1070 			&soc_codec_dev_wm8978, &wm8978_dai, 1);
1071 	if (ret != 0) {
1072 		dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1073 		goto err;
1074 	}
1075 
1076 	return 0;
1077 
1078 err:
1079 	regmap_exit(wm8978->regmap);
1080 	return ret;
1081 }
1082 
wm8978_i2c_remove(struct i2c_client * client)1083 static __devexit int wm8978_i2c_remove(struct i2c_client *client)
1084 {
1085 	struct wm8978_priv *wm8978 = i2c_get_clientdata(client);
1086 
1087 	snd_soc_unregister_codec(&client->dev);
1088 	regmap_exit(wm8978->regmap);
1089 
1090 	return 0;
1091 }
1092 
1093 static const struct i2c_device_id wm8978_i2c_id[] = {
1094 	{ "wm8978", 0 },
1095 	{ }
1096 };
1097 MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
1098 
1099 static struct i2c_driver wm8978_i2c_driver = {
1100 	.driver = {
1101 		.name = "wm8978",
1102 		.owner = THIS_MODULE,
1103 	},
1104 	.probe =    wm8978_i2c_probe,
1105 	.remove =   __devexit_p(wm8978_i2c_remove),
1106 	.id_table = wm8978_i2c_id,
1107 };
1108 
wm8978_modinit(void)1109 static int __init wm8978_modinit(void)
1110 {
1111 	int ret = 0;
1112 	ret = i2c_add_driver(&wm8978_i2c_driver);
1113 	if (ret != 0) {
1114 		printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n",
1115 		       ret);
1116 	}
1117 	return ret;
1118 }
1119 module_init(wm8978_modinit);
1120 
wm8978_exit(void)1121 static void __exit wm8978_exit(void)
1122 {
1123 	i2c_del_driver(&wm8978_i2c_driver);
1124 }
1125 module_exit(wm8978_exit);
1126 
1127 MODULE_DESCRIPTION("ASoC WM8978 codec driver");
1128 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1129 MODULE_LICENSE("GPL");
1130