1 /*
2  *   ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3  *
4  *      Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5  *                              Pilo Chambert <pilo.c@wanadoo.fr>
6  *
7  *      Thanks to :        Anders Torger <torger@ludd.luth.se>,
8  *                         Henk Hesselink <henk@anda.nl>
9  *                         for writing the digi96-driver
10  *                         and RME for all informations.
11  *
12  *   This program is free software; you can redistribute it and/or modify
13  *   it under the terms of the GNU General Public License as published by
14  *   the Free Software Foundation; either version 2 of the License, or
15  *   (at your option) any later version.
16  *
17  *   This program is distributed in the hope that it will be useful,
18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *   GNU General Public License for more details.
21  *
22  *   You should have received a copy of the GNU General Public License
23  *   along with this program; if not, write to the Free Software
24  *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25  *
26  *
27  * ****************************************************************************
28  *
29  * Note #1 "Sek'd models" ................................... martin 2002-12-07
30  *
31  * Identical soundcards by Sek'd were labeled:
32  * RME Digi 32     = Sek'd Prodif 32
33  * RME Digi 32 Pro = Sek'd Prodif 96
34  * RME Digi 32/8   = Sek'd Prodif Gold
35  *
36  * ****************************************************************************
37  *
38  * Note #2 "full duplex mode" ............................... martin 2002-12-07
39  *
40  * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41  * in this mode. Rec data and play data are using the same buffer therefore. At
42  * first you have got the playing bits in the buffer and then (after playing
43  * them) they were overwitten by the captured sound of the CS8412/14. Both
44  * modes (play/record) are running harmonically hand in hand in the same buffer
45  * and you have only one start bit plus one interrupt bit to control this
46  * paired action.
47  * This is opposite to the latter rme96 where playing and capturing is totally
48  * separated and so their full duplex mode is supported by alsa (using two
49  * start bits and two interrupts for two different buffers).
50  * But due to the wrong sequence of playing and capturing ALSA shows no solved
51  * full duplex support for the rme32 at the moment. That's bad, but I'm not
52  * able to solve it. Are you motivated enough to solve this problem now? Your
53  * patch would be welcome!
54  *
55  * ****************************************************************************
56  *
57  * "The story after the long seeking" -- tiwai
58  *
59  * Ok, the situation regarding the full duplex is now improved a bit.
60  * In the fullduplex mode (given by the module parameter), the hardware buffer
61  * is split to halves for read and write directions at the DMA pointer.
62  * That is, the half above the current DMA pointer is used for write, and
63  * the half below is used for read.  To mangle this strange behavior, an
64  * software intermediate buffer is introduced.  This is, of course, not good
65  * from the viewpoint of the data transfer efficiency.  However, this allows
66  * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67  *
68  * ****************************************************************************
69  */
70 
71 
72 #include <linux/delay.h>
73 #include <linux/gfp.h>
74 #include <linux/init.h>
75 #include <linux/interrupt.h>
76 #include <linux/pci.h>
77 #include <linux/module.h>
78 
79 #include <sound/core.h>
80 #include <sound/info.h>
81 #include <sound/control.h>
82 #include <sound/pcm.h>
83 #include <sound/pcm_params.h>
84 #include <sound/pcm-indirect.h>
85 #include <sound/asoundef.h>
86 #include <sound/initval.h>
87 
88 #include <asm/io.h>
89 
90 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
91 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
92 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
93 static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
94 
95 module_param_array(index, int, NULL, 0444);
96 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
97 module_param_array(id, charp, NULL, 0444);
98 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
99 module_param_array(enable, bool, NULL, 0444);
100 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
101 module_param_array(fullduplex, bool, NULL, 0444);
102 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
103 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
104 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
105 MODULE_LICENSE("GPL");
106 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
107 
108 /* Defines for RME Digi32 series */
109 #define RME32_SPDIF_NCHANNELS 2
110 
111 /* Playback and capture buffer size */
112 #define RME32_BUFFER_SIZE 0x20000
113 
114 /* IO area size */
115 #define RME32_IO_SIZE 0x30000
116 
117 /* IO area offsets */
118 #define RME32_IO_DATA_BUFFER        0x0
119 #define RME32_IO_CONTROL_REGISTER   0x20000
120 #define RME32_IO_GET_POS            0x20000
121 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
122 #define RME32_IO_RESET_POS          0x20100
123 
124 /* Write control register bits */
125 #define RME32_WCR_START     (1 << 0)    /* startbit */
126 #define RME32_WCR_MONO      (1 << 1)    /* 0=stereo, 1=mono
127                                            Setting the whole card to mono
128                                            doesn't seem to be very useful.
129                                            A software-solution can handle
130                                            full-duplex with one direction in
131                                            stereo and the other way in mono.
132                                            So, the hardware should work all
133                                            the time in stereo! */
134 #define RME32_WCR_MODE24    (1 << 2)    /* 0=16bit, 1=32bit */
135 #define RME32_WCR_SEL       (1 << 3)    /* 0=input on output, 1=normal playback/capture */
136 #define RME32_WCR_FREQ_0    (1 << 4)    /* frequency (play) */
137 #define RME32_WCR_FREQ_1    (1 << 5)
138 #define RME32_WCR_INP_0     (1 << 6)    /* input switch */
139 #define RME32_WCR_INP_1     (1 << 7)
140 #define RME32_WCR_RESET     (1 << 8)    /* Reset address */
141 #define RME32_WCR_MUTE      (1 << 9)    /* digital mute for output */
142 #define RME32_WCR_PRO       (1 << 10)   /* 1=professional, 0=consumer */
143 #define RME32_WCR_DS_BM     (1 << 11)	/* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
144 #define RME32_WCR_ADAT      (1 << 12)	/* Adat Mode (only Adat-Version) */
145 #define RME32_WCR_AUTOSYNC  (1 << 13)   /* AutoSync */
146 #define RME32_WCR_PD        (1 << 14)	/* DAC Reset (only PRO-Version) */
147 #define RME32_WCR_EMP       (1 << 15)	/* 1=Emphasis on (only PRO-Version) */
148 
149 #define RME32_WCR_BITPOS_FREQ_0 4
150 #define RME32_WCR_BITPOS_FREQ_1 5
151 #define RME32_WCR_BITPOS_INP_0 6
152 #define RME32_WCR_BITPOS_INP_1 7
153 
154 /* Read control register bits */
155 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
156 #define RME32_RCR_LOCK      (1 << 23)   /* 1=locked, 0=not locked */
157 #define RME32_RCR_ERF       (1 << 26)   /* 1=Error, 0=no Error */
158 #define RME32_RCR_FREQ_0    (1 << 27)   /* CS841x frequency (record) */
159 #define RME32_RCR_FREQ_1    (1 << 28)
160 #define RME32_RCR_FREQ_2    (1 << 29)
161 #define RME32_RCR_KMODE     (1 << 30)   /* card mode: 1=PLL, 0=quartz */
162 #define RME32_RCR_IRQ       (1 << 31)   /* interrupt */
163 
164 #define RME32_RCR_BITPOS_F0 27
165 #define RME32_RCR_BITPOS_F1 28
166 #define RME32_RCR_BITPOS_F2 29
167 
168 /* Input types */
169 #define RME32_INPUT_OPTICAL 0
170 #define RME32_INPUT_COAXIAL 1
171 #define RME32_INPUT_INTERNAL 2
172 #define RME32_INPUT_XLR 3
173 
174 /* Clock modes */
175 #define RME32_CLOCKMODE_SLAVE 0
176 #define RME32_CLOCKMODE_MASTER_32 1
177 #define RME32_CLOCKMODE_MASTER_44 2
178 #define RME32_CLOCKMODE_MASTER_48 3
179 
180 /* Block sizes in bytes */
181 #define RME32_BLOCK_SIZE 8192
182 
183 /* Software intermediate buffer (max) size */
184 #define RME32_MID_BUFFER_SIZE (1024*1024)
185 
186 /* Hardware revisions */
187 #define RME32_32_REVISION 192
188 #define RME32_328_REVISION_OLD 100
189 #define RME32_328_REVISION_NEW 101
190 #define RME32_PRO_REVISION_WITH_8412 192
191 #define RME32_PRO_REVISION_WITH_8414 150
192 
193 
194 struct rme32 {
195 	spinlock_t lock;
196 	int irq;
197 	unsigned long port;
198 	void __iomem *iobase;
199 
200 	u32 wcreg;		/* cached write control register value */
201 	u32 wcreg_spdif;	/* S/PDIF setup */
202 	u32 wcreg_spdif_stream;	/* S/PDIF setup (temporary) */
203 	u32 rcreg;		/* cached read control register value */
204 
205 	u8 rev;			/* card revision number */
206 
207 	struct snd_pcm_substream *playback_substream;
208 	struct snd_pcm_substream *capture_substream;
209 
210 	int playback_frlog;	/* log2 of framesize */
211 	int capture_frlog;
212 
213 	size_t playback_periodsize;	/* in bytes, zero if not used */
214 	size_t capture_periodsize;	/* in bytes, zero if not used */
215 
216 	unsigned int fullduplex_mode;
217 	int running;
218 
219 	struct snd_pcm_indirect playback_pcm;
220 	struct snd_pcm_indirect capture_pcm;
221 
222 	struct snd_card *card;
223 	struct snd_pcm *spdif_pcm;
224 	struct snd_pcm *adat_pcm;
225 	struct pci_dev *pci;
226 	struct snd_kcontrol *spdif_ctl;
227 };
228 
229 static DEFINE_PCI_DEVICE_TABLE(snd_rme32_ids) = {
230 	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
231 	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
232 	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
233 	{0,}
234 };
235 
236 MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
237 
238 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
239 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
240 
241 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
242 
243 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
244 
245 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
246 
247 static void snd_rme32_proc_init(struct rme32 * rme32);
248 
249 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
250 
snd_rme32_pcm_byteptr(struct rme32 * rme32)251 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
252 {
253 	return (readl(rme32->iobase + RME32_IO_GET_POS)
254 		& RME32_RCR_AUDIO_ADDR_MASK);
255 }
256 
257 /* silence callback for halfduplex mode */
snd_rme32_playback_silence(struct snd_pcm_substream * substream,int channel,snd_pcm_uframes_t pos,snd_pcm_uframes_t count)258 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
259 				      snd_pcm_uframes_t pos,
260 				      snd_pcm_uframes_t count)
261 {
262 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
263 	count <<= rme32->playback_frlog;
264 	pos <<= rme32->playback_frlog;
265 	memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
266 	return 0;
267 }
268 
269 /* copy callback for halfduplex mode */
snd_rme32_playback_copy(struct snd_pcm_substream * substream,int channel,snd_pcm_uframes_t pos,void __user * src,snd_pcm_uframes_t count)270 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
271 				   snd_pcm_uframes_t pos,
272 				   void __user *src, snd_pcm_uframes_t count)
273 {
274 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
275 	count <<= rme32->playback_frlog;
276 	pos <<= rme32->playback_frlog;
277 	if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
278 			    src, count))
279 		return -EFAULT;
280 	return 0;
281 }
282 
283 /* copy callback for halfduplex mode */
snd_rme32_capture_copy(struct snd_pcm_substream * substream,int channel,snd_pcm_uframes_t pos,void __user * dst,snd_pcm_uframes_t count)284 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
285 				  snd_pcm_uframes_t pos,
286 				  void __user *dst, snd_pcm_uframes_t count)
287 {
288 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
289 	count <<= rme32->capture_frlog;
290 	pos <<= rme32->capture_frlog;
291 	if (copy_to_user_fromio(dst,
292 			    rme32->iobase + RME32_IO_DATA_BUFFER + pos,
293 			    count))
294 		return -EFAULT;
295 	return 0;
296 }
297 
298 /*
299  * SPDIF I/O capabilities (half-duplex mode)
300  */
301 static struct snd_pcm_hardware snd_rme32_spdif_info = {
302 	.info =		(SNDRV_PCM_INFO_MMAP_IOMEM |
303 			 SNDRV_PCM_INFO_MMAP_VALID |
304 			 SNDRV_PCM_INFO_INTERLEAVED |
305 			 SNDRV_PCM_INFO_PAUSE |
306 			 SNDRV_PCM_INFO_SYNC_START),
307 	.formats =	(SNDRV_PCM_FMTBIT_S16_LE |
308 			 SNDRV_PCM_FMTBIT_S32_LE),
309 	.rates =	(SNDRV_PCM_RATE_32000 |
310 			 SNDRV_PCM_RATE_44100 |
311 			 SNDRV_PCM_RATE_48000),
312 	.rate_min =	32000,
313 	.rate_max =	48000,
314 	.channels_min =	2,
315 	.channels_max =	2,
316 	.buffer_bytes_max = RME32_BUFFER_SIZE,
317 	.period_bytes_min = RME32_BLOCK_SIZE,
318 	.period_bytes_max = RME32_BLOCK_SIZE,
319 	.periods_min =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
320 	.periods_max =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
321 	.fifo_size =	0,
322 };
323 
324 /*
325  * ADAT I/O capabilities (half-duplex mode)
326  */
327 static struct snd_pcm_hardware snd_rme32_adat_info =
328 {
329 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
330 			      SNDRV_PCM_INFO_MMAP_VALID |
331 			      SNDRV_PCM_INFO_INTERLEAVED |
332 			      SNDRV_PCM_INFO_PAUSE |
333 			      SNDRV_PCM_INFO_SYNC_START),
334 	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
335 	.rates =             (SNDRV_PCM_RATE_44100 |
336 			      SNDRV_PCM_RATE_48000),
337 	.rate_min =          44100,
338 	.rate_max =          48000,
339 	.channels_min =      8,
340 	.channels_max =	     8,
341 	.buffer_bytes_max =  RME32_BUFFER_SIZE,
342 	.period_bytes_min =  RME32_BLOCK_SIZE,
343 	.period_bytes_max =  RME32_BLOCK_SIZE,
344 	.periods_min =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
345 	.periods_max =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
346 	.fifo_size =	    0,
347 };
348 
349 /*
350  * SPDIF I/O capabilities (full-duplex mode)
351  */
352 static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
353 	.info =		(SNDRV_PCM_INFO_MMAP |
354 			 SNDRV_PCM_INFO_MMAP_VALID |
355 			 SNDRV_PCM_INFO_INTERLEAVED |
356 			 SNDRV_PCM_INFO_PAUSE |
357 			 SNDRV_PCM_INFO_SYNC_START),
358 	.formats =	(SNDRV_PCM_FMTBIT_S16_LE |
359 			 SNDRV_PCM_FMTBIT_S32_LE),
360 	.rates =	(SNDRV_PCM_RATE_32000 |
361 			 SNDRV_PCM_RATE_44100 |
362 			 SNDRV_PCM_RATE_48000),
363 	.rate_min =	32000,
364 	.rate_max =	48000,
365 	.channels_min =	2,
366 	.channels_max =	2,
367 	.buffer_bytes_max = RME32_MID_BUFFER_SIZE,
368 	.period_bytes_min = RME32_BLOCK_SIZE,
369 	.period_bytes_max = RME32_BLOCK_SIZE,
370 	.periods_min =	2,
371 	.periods_max =	RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
372 	.fifo_size =	0,
373 };
374 
375 /*
376  * ADAT I/O capabilities (full-duplex mode)
377  */
378 static struct snd_pcm_hardware snd_rme32_adat_fd_info =
379 {
380 	.info =		     (SNDRV_PCM_INFO_MMAP |
381 			      SNDRV_PCM_INFO_MMAP_VALID |
382 			      SNDRV_PCM_INFO_INTERLEAVED |
383 			      SNDRV_PCM_INFO_PAUSE |
384 			      SNDRV_PCM_INFO_SYNC_START),
385 	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
386 	.rates =             (SNDRV_PCM_RATE_44100 |
387 			      SNDRV_PCM_RATE_48000),
388 	.rate_min =          44100,
389 	.rate_max =          48000,
390 	.channels_min =      8,
391 	.channels_max =	     8,
392 	.buffer_bytes_max =  RME32_MID_BUFFER_SIZE,
393 	.period_bytes_min =  RME32_BLOCK_SIZE,
394 	.period_bytes_max =  RME32_BLOCK_SIZE,
395 	.periods_min =	    2,
396 	.periods_max =	    RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
397 	.fifo_size =	    0,
398 };
399 
snd_rme32_reset_dac(struct rme32 * rme32)400 static void snd_rme32_reset_dac(struct rme32 *rme32)
401 {
402         writel(rme32->wcreg | RME32_WCR_PD,
403                rme32->iobase + RME32_IO_CONTROL_REGISTER);
404         writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
405 }
406 
snd_rme32_playback_getrate(struct rme32 * rme32)407 static int snd_rme32_playback_getrate(struct rme32 * rme32)
408 {
409 	int rate;
410 
411 	rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
412 	       (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
413 	switch (rate) {
414 	case 1:
415 		rate = 32000;
416 		break;
417 	case 2:
418 		rate = 44100;
419 		break;
420 	case 3:
421 		rate = 48000;
422 		break;
423 	default:
424 		return -1;
425 	}
426 	return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
427 }
428 
snd_rme32_capture_getrate(struct rme32 * rme32,int * is_adat)429 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
430 {
431 	int n;
432 
433 	*is_adat = 0;
434 	if (rme32->rcreg & RME32_RCR_LOCK) {
435                 /* ADAT rate */
436                 *is_adat = 1;
437 	}
438 	if (rme32->rcreg & RME32_RCR_ERF) {
439 		return -1;
440 	}
441 
442         /* S/PDIF rate */
443 	n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
444 		(((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
445 		(((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
446 
447 	if (RME32_PRO_WITH_8414(rme32))
448 		switch (n) {	/* supporting the CS8414 */
449 		case 0:
450 		case 1:
451 		case 2:
452 			return -1;
453 		case 3:
454 			return 96000;
455 		case 4:
456 			return 88200;
457 		case 5:
458 			return 48000;
459 		case 6:
460 			return 44100;
461 		case 7:
462 			return 32000;
463 		default:
464 			return -1;
465 			break;
466 		}
467 	else
468 		switch (n) {	/* supporting the CS8412 */
469 		case 0:
470 			return -1;
471 		case 1:
472 			return 48000;
473 		case 2:
474 			return 44100;
475 		case 3:
476 			return 32000;
477 		case 4:
478 			return 48000;
479 		case 5:
480 			return 44100;
481 		case 6:
482 			return 44056;
483 		case 7:
484 			return 32000;
485 		default:
486 			break;
487 		}
488 	return -1;
489 }
490 
snd_rme32_playback_setrate(struct rme32 * rme32,int rate)491 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
492 {
493         int ds;
494 
495         ds = rme32->wcreg & RME32_WCR_DS_BM;
496 	switch (rate) {
497 	case 32000:
498 		rme32->wcreg &= ~RME32_WCR_DS_BM;
499 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
500 			~RME32_WCR_FREQ_1;
501 		break;
502 	case 44100:
503 		rme32->wcreg &= ~RME32_WCR_DS_BM;
504 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
505 			~RME32_WCR_FREQ_0;
506 		break;
507 	case 48000:
508 		rme32->wcreg &= ~RME32_WCR_DS_BM;
509 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
510 			RME32_WCR_FREQ_1;
511 		break;
512 	case 64000:
513 		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
514 			return -EINVAL;
515 		rme32->wcreg |= RME32_WCR_DS_BM;
516 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
517 			~RME32_WCR_FREQ_1;
518 		break;
519 	case 88200:
520 		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
521 			return -EINVAL;
522 		rme32->wcreg |= RME32_WCR_DS_BM;
523 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
524 			~RME32_WCR_FREQ_0;
525 		break;
526 	case 96000:
527 		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
528 			return -EINVAL;
529 		rme32->wcreg |= RME32_WCR_DS_BM;
530 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
531 			RME32_WCR_FREQ_1;
532 		break;
533 	default:
534 		return -EINVAL;
535 	}
536         if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
537             (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
538         {
539                 /* change to/from double-speed: reset the DAC (if available) */
540                 snd_rme32_reset_dac(rme32);
541         } else {
542                 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
543 	}
544 	return 0;
545 }
546 
snd_rme32_setclockmode(struct rme32 * rme32,int mode)547 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
548 {
549 	switch (mode) {
550 	case RME32_CLOCKMODE_SLAVE:
551 		/* AutoSync */
552 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
553 			~RME32_WCR_FREQ_1;
554 		break;
555 	case RME32_CLOCKMODE_MASTER_32:
556 		/* Internal 32.0kHz */
557 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
558 			~RME32_WCR_FREQ_1;
559 		break;
560 	case RME32_CLOCKMODE_MASTER_44:
561 		/* Internal 44.1kHz */
562 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
563 			RME32_WCR_FREQ_1;
564 		break;
565 	case RME32_CLOCKMODE_MASTER_48:
566 		/* Internal 48.0kHz */
567 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
568 			RME32_WCR_FREQ_1;
569 		break;
570 	default:
571 		return -EINVAL;
572 	}
573 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
574 	return 0;
575 }
576 
snd_rme32_getclockmode(struct rme32 * rme32)577 static int snd_rme32_getclockmode(struct rme32 * rme32)
578 {
579 	return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
580 	    (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
581 }
582 
snd_rme32_setinputtype(struct rme32 * rme32,int type)583 static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
584 {
585 	switch (type) {
586 	case RME32_INPUT_OPTICAL:
587 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
588 			~RME32_WCR_INP_1;
589 		break;
590 	case RME32_INPUT_COAXIAL:
591 		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
592 			~RME32_WCR_INP_1;
593 		break;
594 	case RME32_INPUT_INTERNAL:
595 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
596 			RME32_WCR_INP_1;
597 		break;
598 	case RME32_INPUT_XLR:
599 		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
600 			RME32_WCR_INP_1;
601 		break;
602 	default:
603 		return -EINVAL;
604 	}
605 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
606 	return 0;
607 }
608 
snd_rme32_getinputtype(struct rme32 * rme32)609 static int snd_rme32_getinputtype(struct rme32 * rme32)
610 {
611 	return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
612 	    (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
613 }
614 
615 static void
snd_rme32_setframelog(struct rme32 * rme32,int n_channels,int is_playback)616 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
617 {
618 	int frlog;
619 
620 	if (n_channels == 2) {
621 		frlog = 1;
622 	} else {
623 		/* assume 8 channels */
624 		frlog = 3;
625 	}
626 	if (is_playback) {
627 		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
628 		rme32->playback_frlog = frlog;
629 	} else {
630 		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
631 		rme32->capture_frlog = frlog;
632 	}
633 }
634 
snd_rme32_setformat(struct rme32 * rme32,int format)635 static int snd_rme32_setformat(struct rme32 * rme32, int format)
636 {
637 	switch (format) {
638 	case SNDRV_PCM_FORMAT_S16_LE:
639 		rme32->wcreg &= ~RME32_WCR_MODE24;
640 		break;
641 	case SNDRV_PCM_FORMAT_S32_LE:
642 		rme32->wcreg |= RME32_WCR_MODE24;
643 		break;
644 	default:
645 		return -EINVAL;
646 	}
647 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
648 	return 0;
649 }
650 
651 static int
snd_rme32_playback_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)652 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
653 			     struct snd_pcm_hw_params *params)
654 {
655 	int err, rate, dummy;
656 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
657 	struct snd_pcm_runtime *runtime = substream->runtime;
658 
659 	if (rme32->fullduplex_mode) {
660 		err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
661 		if (err < 0)
662 			return err;
663 	} else {
664 		runtime->dma_area = (void __force *)(rme32->iobase +
665 						     RME32_IO_DATA_BUFFER);
666 		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
667 		runtime->dma_bytes = RME32_BUFFER_SIZE;
668 	}
669 
670 	spin_lock_irq(&rme32->lock);
671 	if ((rme32->rcreg & RME32_RCR_KMODE) &&
672 	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
673 		/* AutoSync */
674 		if ((int)params_rate(params) != rate) {
675 			spin_unlock_irq(&rme32->lock);
676 			return -EIO;
677 		}
678 	} else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
679 		spin_unlock_irq(&rme32->lock);
680 		return err;
681 	}
682 	if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
683 		spin_unlock_irq(&rme32->lock);
684 		return err;
685 	}
686 
687 	snd_rme32_setframelog(rme32, params_channels(params), 1);
688 	if (rme32->capture_periodsize != 0) {
689 		if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
690 			spin_unlock_irq(&rme32->lock);
691 			return -EBUSY;
692 		}
693 	}
694 	rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
695 	/* S/PDIF setup */
696 	if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
697 		rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
698 		rme32->wcreg |= rme32->wcreg_spdif_stream;
699 		writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
700 	}
701 	spin_unlock_irq(&rme32->lock);
702 
703 	return 0;
704 }
705 
706 static int
snd_rme32_capture_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)707 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
708 			    struct snd_pcm_hw_params *params)
709 {
710 	int err, isadat, rate;
711 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
712 	struct snd_pcm_runtime *runtime = substream->runtime;
713 
714 	if (rme32->fullduplex_mode) {
715 		err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
716 		if (err < 0)
717 			return err;
718 	} else {
719 		runtime->dma_area = (void __force *)rme32->iobase +
720 					RME32_IO_DATA_BUFFER;
721 		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
722 		runtime->dma_bytes = RME32_BUFFER_SIZE;
723 	}
724 
725 	spin_lock_irq(&rme32->lock);
726 	/* enable AutoSync for record-preparing */
727 	rme32->wcreg |= RME32_WCR_AUTOSYNC;
728 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
729 
730 	if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
731 		spin_unlock_irq(&rme32->lock);
732 		return err;
733 	}
734 	if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
735 		spin_unlock_irq(&rme32->lock);
736 		return err;
737 	}
738 	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
739                 if ((int)params_rate(params) != rate) {
740 			spin_unlock_irq(&rme32->lock);
741                         return -EIO;
742                 }
743                 if ((isadat && runtime->hw.channels_min == 2) ||
744                     (!isadat && runtime->hw.channels_min == 8)) {
745 			spin_unlock_irq(&rme32->lock);
746                         return -EIO;
747                 }
748 	}
749 	/* AutoSync off for recording */
750 	rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
751 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
752 
753 	snd_rme32_setframelog(rme32, params_channels(params), 0);
754 	if (rme32->playback_periodsize != 0) {
755 		if (params_period_size(params) << rme32->capture_frlog !=
756 		    rme32->playback_periodsize) {
757 			spin_unlock_irq(&rme32->lock);
758 			return -EBUSY;
759 		}
760 	}
761 	rme32->capture_periodsize =
762 	    params_period_size(params) << rme32->capture_frlog;
763 	spin_unlock_irq(&rme32->lock);
764 
765 	return 0;
766 }
767 
snd_rme32_pcm_hw_free(struct snd_pcm_substream * substream)768 static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
769 {
770 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
771 	if (! rme32->fullduplex_mode)
772 		return 0;
773 	return snd_pcm_lib_free_pages(substream);
774 }
775 
snd_rme32_pcm_start(struct rme32 * rme32,int from_pause)776 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
777 {
778 	if (!from_pause) {
779 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
780 	}
781 
782 	rme32->wcreg |= RME32_WCR_START;
783 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
784 }
785 
snd_rme32_pcm_stop(struct rme32 * rme32,int to_pause)786 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
787 {
788 	/*
789 	 * Check if there is an unconfirmed IRQ, if so confirm it, or else
790 	 * the hardware will not stop generating interrupts
791 	 */
792 	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
793 	if (rme32->rcreg & RME32_RCR_IRQ) {
794 		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
795 	}
796 	rme32->wcreg &= ~RME32_WCR_START;
797 	if (rme32->wcreg & RME32_WCR_SEL)
798 		rme32->wcreg |= RME32_WCR_MUTE;
799 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
800 	if (! to_pause)
801 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
802 }
803 
snd_rme32_interrupt(int irq,void * dev_id)804 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
805 {
806 	struct rme32 *rme32 = (struct rme32 *) dev_id;
807 
808 	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
809 	if (!(rme32->rcreg & RME32_RCR_IRQ)) {
810 		return IRQ_NONE;
811 	} else {
812 		if (rme32->capture_substream) {
813 			snd_pcm_period_elapsed(rme32->capture_substream);
814 		}
815 		if (rme32->playback_substream) {
816 			snd_pcm_period_elapsed(rme32->playback_substream);
817 		}
818 		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
819 	}
820 	return IRQ_HANDLED;
821 }
822 
823 static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
824 
825 
826 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
827 	.count = ARRAY_SIZE(period_bytes),
828 	.list = period_bytes,
829 	.mask = 0
830 };
831 
snd_rme32_set_buffer_constraint(struct rme32 * rme32,struct snd_pcm_runtime * runtime)832 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
833 {
834 	if (! rme32->fullduplex_mode) {
835 		snd_pcm_hw_constraint_minmax(runtime,
836 					     SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
837 					     RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
838 		snd_pcm_hw_constraint_list(runtime, 0,
839 					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
840 					   &hw_constraints_period_bytes);
841 	}
842 }
843 
snd_rme32_playback_spdif_open(struct snd_pcm_substream * substream)844 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
845 {
846 	int rate, dummy;
847 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
848 	struct snd_pcm_runtime *runtime = substream->runtime;
849 
850 	snd_pcm_set_sync(substream);
851 
852 	spin_lock_irq(&rme32->lock);
853 	if (rme32->playback_substream != NULL) {
854 		spin_unlock_irq(&rme32->lock);
855 		return -EBUSY;
856 	}
857 	rme32->wcreg &= ~RME32_WCR_ADAT;
858 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
859 	rme32->playback_substream = substream;
860 	spin_unlock_irq(&rme32->lock);
861 
862 	if (rme32->fullduplex_mode)
863 		runtime->hw = snd_rme32_spdif_fd_info;
864 	else
865 		runtime->hw = snd_rme32_spdif_info;
866 	if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
867 		runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
868 		runtime->hw.rate_max = 96000;
869 	}
870 	if ((rme32->rcreg & RME32_RCR_KMODE) &&
871 	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
872 		/* AutoSync */
873 		runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
874 		runtime->hw.rate_min = rate;
875 		runtime->hw.rate_max = rate;
876 	}
877 
878 	snd_rme32_set_buffer_constraint(rme32, runtime);
879 
880 	rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
881 	rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
882 	snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
883 		       SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
884 	return 0;
885 }
886 
snd_rme32_capture_spdif_open(struct snd_pcm_substream * substream)887 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
888 {
889 	int isadat, rate;
890 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
891 	struct snd_pcm_runtime *runtime = substream->runtime;
892 
893 	snd_pcm_set_sync(substream);
894 
895 	spin_lock_irq(&rme32->lock);
896         if (rme32->capture_substream != NULL) {
897 		spin_unlock_irq(&rme32->lock);
898                 return -EBUSY;
899         }
900 	rme32->capture_substream = substream;
901 	spin_unlock_irq(&rme32->lock);
902 
903 	if (rme32->fullduplex_mode)
904 		runtime->hw = snd_rme32_spdif_fd_info;
905 	else
906 		runtime->hw = snd_rme32_spdif_info;
907 	if (RME32_PRO_WITH_8414(rme32)) {
908 		runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
909 		runtime->hw.rate_max = 96000;
910 	}
911 	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
912 		if (isadat) {
913 			return -EIO;
914 		}
915 		runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
916 		runtime->hw.rate_min = rate;
917 		runtime->hw.rate_max = rate;
918 	}
919 
920 	snd_rme32_set_buffer_constraint(rme32, runtime);
921 
922 	return 0;
923 }
924 
925 static int
snd_rme32_playback_adat_open(struct snd_pcm_substream * substream)926 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
927 {
928 	int rate, dummy;
929 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
930 	struct snd_pcm_runtime *runtime = substream->runtime;
931 
932 	snd_pcm_set_sync(substream);
933 
934 	spin_lock_irq(&rme32->lock);
935         if (rme32->playback_substream != NULL) {
936 		spin_unlock_irq(&rme32->lock);
937                 return -EBUSY;
938         }
939 	rme32->wcreg |= RME32_WCR_ADAT;
940 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
941 	rme32->playback_substream = substream;
942 	spin_unlock_irq(&rme32->lock);
943 
944 	if (rme32->fullduplex_mode)
945 		runtime->hw = snd_rme32_adat_fd_info;
946 	else
947 		runtime->hw = snd_rme32_adat_info;
948 	if ((rme32->rcreg & RME32_RCR_KMODE) &&
949 	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
950                 /* AutoSync */
951                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
952                 runtime->hw.rate_min = rate;
953                 runtime->hw.rate_max = rate;
954 	}
955 
956 	snd_rme32_set_buffer_constraint(rme32, runtime);
957 	return 0;
958 }
959 
960 static int
snd_rme32_capture_adat_open(struct snd_pcm_substream * substream)961 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
962 {
963 	int isadat, rate;
964 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
965 	struct snd_pcm_runtime *runtime = substream->runtime;
966 
967 	if (rme32->fullduplex_mode)
968 		runtime->hw = snd_rme32_adat_fd_info;
969 	else
970 		runtime->hw = snd_rme32_adat_info;
971 	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
972 		if (!isadat) {
973 			return -EIO;
974 		}
975                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
976                 runtime->hw.rate_min = rate;
977                 runtime->hw.rate_max = rate;
978         }
979 
980 	snd_pcm_set_sync(substream);
981 
982 	spin_lock_irq(&rme32->lock);
983 	if (rme32->capture_substream != NULL) {
984 		spin_unlock_irq(&rme32->lock);
985 		return -EBUSY;
986         }
987 	rme32->capture_substream = substream;
988 	spin_unlock_irq(&rme32->lock);
989 
990 	snd_rme32_set_buffer_constraint(rme32, runtime);
991 	return 0;
992 }
993 
snd_rme32_playback_close(struct snd_pcm_substream * substream)994 static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
995 {
996 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
997 	int spdif = 0;
998 
999 	spin_lock_irq(&rme32->lock);
1000 	rme32->playback_substream = NULL;
1001 	rme32->playback_periodsize = 0;
1002 	spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1003 	spin_unlock_irq(&rme32->lock);
1004 	if (spdif) {
1005 		rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1006 		snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1007 			       SNDRV_CTL_EVENT_MASK_INFO,
1008 			       &rme32->spdif_ctl->id);
1009 	}
1010 	return 0;
1011 }
1012 
snd_rme32_capture_close(struct snd_pcm_substream * substream)1013 static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1014 {
1015 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1016 
1017 	spin_lock_irq(&rme32->lock);
1018 	rme32->capture_substream = NULL;
1019 	rme32->capture_periodsize = 0;
1020 	spin_unlock_irq(&rme32->lock);
1021 	return 0;
1022 }
1023 
snd_rme32_playback_prepare(struct snd_pcm_substream * substream)1024 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1025 {
1026 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1027 
1028 	spin_lock_irq(&rme32->lock);
1029 	if (rme32->fullduplex_mode) {
1030 		memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1031 		rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1032 		rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1033 	} else {
1034 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1035 	}
1036 	if (rme32->wcreg & RME32_WCR_SEL)
1037 		rme32->wcreg &= ~RME32_WCR_MUTE;
1038 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1039 	spin_unlock_irq(&rme32->lock);
1040 	return 0;
1041 }
1042 
snd_rme32_capture_prepare(struct snd_pcm_substream * substream)1043 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1044 {
1045 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1046 
1047 	spin_lock_irq(&rme32->lock);
1048 	if (rme32->fullduplex_mode) {
1049 		memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1050 		rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1051 		rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1052 		rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1053 	} else {
1054 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1055 	}
1056 	spin_unlock_irq(&rme32->lock);
1057 	return 0;
1058 }
1059 
1060 static int
snd_rme32_pcm_trigger(struct snd_pcm_substream * substream,int cmd)1061 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1062 {
1063 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1064 	struct snd_pcm_substream *s;
1065 
1066 	spin_lock(&rme32->lock);
1067 	snd_pcm_group_for_each_entry(s, substream) {
1068 		if (s != rme32->playback_substream &&
1069 		    s != rme32->capture_substream)
1070 			continue;
1071 		switch (cmd) {
1072 		case SNDRV_PCM_TRIGGER_START:
1073 			rme32->running |= (1 << s->stream);
1074 			if (rme32->fullduplex_mode) {
1075 				/* remember the current DMA position */
1076 				if (s == rme32->playback_substream) {
1077 					rme32->playback_pcm.hw_io =
1078 					rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1079 				} else {
1080 					rme32->capture_pcm.hw_io =
1081 					rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1082 				}
1083 			}
1084 			break;
1085 		case SNDRV_PCM_TRIGGER_STOP:
1086 			rme32->running &= ~(1 << s->stream);
1087 			break;
1088 		}
1089 		snd_pcm_trigger_done(s, substream);
1090 	}
1091 
1092 	/* prefill playback buffer */
1093 	if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1094 		snd_pcm_group_for_each_entry(s, substream) {
1095 			if (s == rme32->playback_substream) {
1096 				s->ops->ack(s);
1097 				break;
1098 			}
1099 		}
1100 	}
1101 
1102 	switch (cmd) {
1103 	case SNDRV_PCM_TRIGGER_START:
1104 		if (rme32->running && ! RME32_ISWORKING(rme32))
1105 			snd_rme32_pcm_start(rme32, 0);
1106 		break;
1107 	case SNDRV_PCM_TRIGGER_STOP:
1108 		if (! rme32->running && RME32_ISWORKING(rme32))
1109 			snd_rme32_pcm_stop(rme32, 0);
1110 		break;
1111 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1112 		if (rme32->running && RME32_ISWORKING(rme32))
1113 			snd_rme32_pcm_stop(rme32, 1);
1114 		break;
1115 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1116 		if (rme32->running && ! RME32_ISWORKING(rme32))
1117 			snd_rme32_pcm_start(rme32, 1);
1118 		break;
1119 	}
1120 	spin_unlock(&rme32->lock);
1121 	return 0;
1122 }
1123 
1124 /* pointer callback for halfduplex mode */
1125 static snd_pcm_uframes_t
snd_rme32_playback_pointer(struct snd_pcm_substream * substream)1126 snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1127 {
1128 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1129 	return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1130 }
1131 
1132 static snd_pcm_uframes_t
snd_rme32_capture_pointer(struct snd_pcm_substream * substream)1133 snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1134 {
1135 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1136 	return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1137 }
1138 
1139 
1140 /* ack and pointer callbacks for fullduplex mode */
snd_rme32_pb_trans_copy(struct snd_pcm_substream * substream,struct snd_pcm_indirect * rec,size_t bytes)1141 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1142 				    struct snd_pcm_indirect *rec, size_t bytes)
1143 {
1144 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1145 	memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1146 		    substream->runtime->dma_area + rec->sw_data, bytes);
1147 }
1148 
snd_rme32_playback_fd_ack(struct snd_pcm_substream * substream)1149 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1150 {
1151 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1152 	struct snd_pcm_indirect *rec, *cprec;
1153 
1154 	rec = &rme32->playback_pcm;
1155 	cprec = &rme32->capture_pcm;
1156 	spin_lock(&rme32->lock);
1157 	rec->hw_queue_size = RME32_BUFFER_SIZE;
1158 	if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1159 		rec->hw_queue_size -= cprec->hw_ready;
1160 	spin_unlock(&rme32->lock);
1161 	snd_pcm_indirect_playback_transfer(substream, rec,
1162 					   snd_rme32_pb_trans_copy);
1163 	return 0;
1164 }
1165 
snd_rme32_cp_trans_copy(struct snd_pcm_substream * substream,struct snd_pcm_indirect * rec,size_t bytes)1166 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1167 				    struct snd_pcm_indirect *rec, size_t bytes)
1168 {
1169 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1170 	memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1171 		      rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1172 		      bytes);
1173 }
1174 
snd_rme32_capture_fd_ack(struct snd_pcm_substream * substream)1175 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1176 {
1177 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1178 	snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1179 					  snd_rme32_cp_trans_copy);
1180 	return 0;
1181 }
1182 
1183 static snd_pcm_uframes_t
snd_rme32_playback_fd_pointer(struct snd_pcm_substream * substream)1184 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1185 {
1186 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1187 	return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1188 						 snd_rme32_pcm_byteptr(rme32));
1189 }
1190 
1191 static snd_pcm_uframes_t
snd_rme32_capture_fd_pointer(struct snd_pcm_substream * substream)1192 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1193 {
1194 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1195 	return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1196 						snd_rme32_pcm_byteptr(rme32));
1197 }
1198 
1199 /* for halfduplex mode */
1200 static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1201 	.open =		snd_rme32_playback_spdif_open,
1202 	.close =	snd_rme32_playback_close,
1203 	.ioctl =	snd_pcm_lib_ioctl,
1204 	.hw_params =	snd_rme32_playback_hw_params,
1205 	.hw_free =	snd_rme32_pcm_hw_free,
1206 	.prepare =	snd_rme32_playback_prepare,
1207 	.trigger =	snd_rme32_pcm_trigger,
1208 	.pointer =	snd_rme32_playback_pointer,
1209 	.copy =		snd_rme32_playback_copy,
1210 	.silence =	snd_rme32_playback_silence,
1211 	.mmap =		snd_pcm_lib_mmap_iomem,
1212 };
1213 
1214 static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1215 	.open =		snd_rme32_capture_spdif_open,
1216 	.close =	snd_rme32_capture_close,
1217 	.ioctl =	snd_pcm_lib_ioctl,
1218 	.hw_params =	snd_rme32_capture_hw_params,
1219 	.hw_free =	snd_rme32_pcm_hw_free,
1220 	.prepare =	snd_rme32_capture_prepare,
1221 	.trigger =	snd_rme32_pcm_trigger,
1222 	.pointer =	snd_rme32_capture_pointer,
1223 	.copy =		snd_rme32_capture_copy,
1224 	.mmap =		snd_pcm_lib_mmap_iomem,
1225 };
1226 
1227 static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1228 	.open =		snd_rme32_playback_adat_open,
1229 	.close =	snd_rme32_playback_close,
1230 	.ioctl =	snd_pcm_lib_ioctl,
1231 	.hw_params =	snd_rme32_playback_hw_params,
1232 	.prepare =	snd_rme32_playback_prepare,
1233 	.trigger =	snd_rme32_pcm_trigger,
1234 	.pointer =	snd_rme32_playback_pointer,
1235 	.copy =		snd_rme32_playback_copy,
1236 	.silence =	snd_rme32_playback_silence,
1237 	.mmap =		snd_pcm_lib_mmap_iomem,
1238 };
1239 
1240 static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1241 	.open =		snd_rme32_capture_adat_open,
1242 	.close =	snd_rme32_capture_close,
1243 	.ioctl =	snd_pcm_lib_ioctl,
1244 	.hw_params =	snd_rme32_capture_hw_params,
1245 	.prepare =	snd_rme32_capture_prepare,
1246 	.trigger =	snd_rme32_pcm_trigger,
1247 	.pointer =	snd_rme32_capture_pointer,
1248 	.copy =		snd_rme32_capture_copy,
1249 	.mmap =		snd_pcm_lib_mmap_iomem,
1250 };
1251 
1252 /* for fullduplex mode */
1253 static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1254 	.open =		snd_rme32_playback_spdif_open,
1255 	.close =	snd_rme32_playback_close,
1256 	.ioctl =	snd_pcm_lib_ioctl,
1257 	.hw_params =	snd_rme32_playback_hw_params,
1258 	.hw_free =	snd_rme32_pcm_hw_free,
1259 	.prepare =	snd_rme32_playback_prepare,
1260 	.trigger =	snd_rme32_pcm_trigger,
1261 	.pointer =	snd_rme32_playback_fd_pointer,
1262 	.ack =		snd_rme32_playback_fd_ack,
1263 };
1264 
1265 static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1266 	.open =		snd_rme32_capture_spdif_open,
1267 	.close =	snd_rme32_capture_close,
1268 	.ioctl =	snd_pcm_lib_ioctl,
1269 	.hw_params =	snd_rme32_capture_hw_params,
1270 	.hw_free =	snd_rme32_pcm_hw_free,
1271 	.prepare =	snd_rme32_capture_prepare,
1272 	.trigger =	snd_rme32_pcm_trigger,
1273 	.pointer =	snd_rme32_capture_fd_pointer,
1274 	.ack =		snd_rme32_capture_fd_ack,
1275 };
1276 
1277 static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1278 	.open =		snd_rme32_playback_adat_open,
1279 	.close =	snd_rme32_playback_close,
1280 	.ioctl =	snd_pcm_lib_ioctl,
1281 	.hw_params =	snd_rme32_playback_hw_params,
1282 	.prepare =	snd_rme32_playback_prepare,
1283 	.trigger =	snd_rme32_pcm_trigger,
1284 	.pointer =	snd_rme32_playback_fd_pointer,
1285 	.ack =		snd_rme32_playback_fd_ack,
1286 };
1287 
1288 static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1289 	.open =		snd_rme32_capture_adat_open,
1290 	.close =	snd_rme32_capture_close,
1291 	.ioctl =	snd_pcm_lib_ioctl,
1292 	.hw_params =	snd_rme32_capture_hw_params,
1293 	.prepare =	snd_rme32_capture_prepare,
1294 	.trigger =	snd_rme32_pcm_trigger,
1295 	.pointer =	snd_rme32_capture_fd_pointer,
1296 	.ack =		snd_rme32_capture_fd_ack,
1297 };
1298 
snd_rme32_free(void * private_data)1299 static void snd_rme32_free(void *private_data)
1300 {
1301 	struct rme32 *rme32 = (struct rme32 *) private_data;
1302 
1303 	if (rme32 == NULL) {
1304 		return;
1305 	}
1306 	if (rme32->irq >= 0) {
1307 		snd_rme32_pcm_stop(rme32, 0);
1308 		free_irq(rme32->irq, (void *) rme32);
1309 		rme32->irq = -1;
1310 	}
1311 	if (rme32->iobase) {
1312 		iounmap(rme32->iobase);
1313 		rme32->iobase = NULL;
1314 	}
1315 	if (rme32->port) {
1316 		pci_release_regions(rme32->pci);
1317 		rme32->port = 0;
1318 	}
1319 	pci_disable_device(rme32->pci);
1320 }
1321 
snd_rme32_free_spdif_pcm(struct snd_pcm * pcm)1322 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1323 {
1324 	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1325 	rme32->spdif_pcm = NULL;
1326 }
1327 
1328 static void
snd_rme32_free_adat_pcm(struct snd_pcm * pcm)1329 snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1330 {
1331 	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1332 	rme32->adat_pcm = NULL;
1333 }
1334 
snd_rme32_create(struct rme32 * rme32)1335 static int __devinit snd_rme32_create(struct rme32 * rme32)
1336 {
1337 	struct pci_dev *pci = rme32->pci;
1338 	int err;
1339 
1340 	rme32->irq = -1;
1341 	spin_lock_init(&rme32->lock);
1342 
1343 	if ((err = pci_enable_device(pci)) < 0)
1344 		return err;
1345 
1346 	if ((err = pci_request_regions(pci, "RME32")) < 0)
1347 		return err;
1348 	rme32->port = pci_resource_start(rme32->pci, 0);
1349 
1350 	rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE);
1351 	if (!rme32->iobase) {
1352 		snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n",
1353 			   rme32->port, rme32->port + RME32_IO_SIZE - 1);
1354 		return -ENOMEM;
1355 	}
1356 
1357 	if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
1358 			KBUILD_MODNAME, rme32)) {
1359 		snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1360 		return -EBUSY;
1361 	}
1362 	rme32->irq = pci->irq;
1363 
1364 	/* read the card's revision number */
1365 	pci_read_config_byte(pci, 8, &rme32->rev);
1366 
1367 	/* set up ALSA pcm device for S/PDIF */
1368 	if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1369 		return err;
1370 	}
1371 	rme32->spdif_pcm->private_data = rme32;
1372 	rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1373 	strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1374 	if (rme32->fullduplex_mode) {
1375 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1376 				&snd_rme32_playback_spdif_fd_ops);
1377 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1378 				&snd_rme32_capture_spdif_fd_ops);
1379 		snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1380 						      snd_dma_continuous_data(GFP_KERNEL),
1381 						      0, RME32_MID_BUFFER_SIZE);
1382 		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1383 	} else {
1384 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1385 				&snd_rme32_playback_spdif_ops);
1386 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1387 				&snd_rme32_capture_spdif_ops);
1388 		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1389 	}
1390 
1391 	/* set up ALSA pcm device for ADAT */
1392 	if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1393 	    (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1394 		/* ADAT is not available on DIGI32 and DIGI32 Pro */
1395 		rme32->adat_pcm = NULL;
1396 	}
1397 	else {
1398 		if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1399 				       1, 1, &rme32->adat_pcm)) < 0)
1400 		{
1401 			return err;
1402 		}
1403 		rme32->adat_pcm->private_data = rme32;
1404 		rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1405 		strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1406 		if (rme32->fullduplex_mode) {
1407 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1408 					&snd_rme32_playback_adat_fd_ops);
1409 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1410 					&snd_rme32_capture_adat_fd_ops);
1411 			snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1412 							      snd_dma_continuous_data(GFP_KERNEL),
1413 							      0, RME32_MID_BUFFER_SIZE);
1414 			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1415 		} else {
1416 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1417 					&snd_rme32_playback_adat_ops);
1418 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1419 					&snd_rme32_capture_adat_ops);
1420 			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1421 		}
1422 	}
1423 
1424 
1425 	rme32->playback_periodsize = 0;
1426 	rme32->capture_periodsize = 0;
1427 
1428 	/* make sure playback/capture is stopped, if by some reason active */
1429 	snd_rme32_pcm_stop(rme32, 0);
1430 
1431         /* reset DAC */
1432         snd_rme32_reset_dac(rme32);
1433 
1434 	/* reset buffer pointer */
1435 	writel(0, rme32->iobase + RME32_IO_RESET_POS);
1436 
1437 	/* set default values in registers */
1438 	rme32->wcreg = RME32_WCR_SEL |	 /* normal playback */
1439 		RME32_WCR_INP_0 | /* input select */
1440 		RME32_WCR_MUTE;	 /* muting on */
1441 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1442 
1443 
1444 	/* init switch interface */
1445 	if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1446 		return err;
1447 	}
1448 
1449 	/* init proc interface */
1450 	snd_rme32_proc_init(rme32);
1451 
1452 	rme32->capture_substream = NULL;
1453 	rme32->playback_substream = NULL;
1454 
1455 	return 0;
1456 }
1457 
1458 /*
1459  * proc interface
1460  */
1461 
1462 static void
snd_rme32_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1463 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1464 {
1465 	int n;
1466 	struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1467 
1468 	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1469 
1470 	snd_iprintf(buffer, rme32->card->longname);
1471 	snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1472 
1473 	snd_iprintf(buffer, "\nGeneral settings\n");
1474 	if (rme32->fullduplex_mode)
1475 		snd_iprintf(buffer, "  Full-duplex mode\n");
1476 	else
1477 		snd_iprintf(buffer, "  Half-duplex mode\n");
1478 	if (RME32_PRO_WITH_8414(rme32)) {
1479 		snd_iprintf(buffer, "  receiver: CS8414\n");
1480 	} else {
1481 		snd_iprintf(buffer, "  receiver: CS8412\n");
1482 	}
1483 	if (rme32->wcreg & RME32_WCR_MODE24) {
1484 		snd_iprintf(buffer, "  format: 24 bit");
1485 	} else {
1486 		snd_iprintf(buffer, "  format: 16 bit");
1487 	}
1488 	if (rme32->wcreg & RME32_WCR_MONO) {
1489 		snd_iprintf(buffer, ", Mono\n");
1490 	} else {
1491 		snd_iprintf(buffer, ", Stereo\n");
1492 	}
1493 
1494 	snd_iprintf(buffer, "\nInput settings\n");
1495 	switch (snd_rme32_getinputtype(rme32)) {
1496 	case RME32_INPUT_OPTICAL:
1497 		snd_iprintf(buffer, "  input: optical");
1498 		break;
1499 	case RME32_INPUT_COAXIAL:
1500 		snd_iprintf(buffer, "  input: coaxial");
1501 		break;
1502 	case RME32_INPUT_INTERNAL:
1503 		snd_iprintf(buffer, "  input: internal");
1504 		break;
1505 	case RME32_INPUT_XLR:
1506 		snd_iprintf(buffer, "  input: XLR");
1507 		break;
1508 	}
1509 	if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1510 		snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1511 	} else {
1512 		if (n) {
1513 			snd_iprintf(buffer, " (8 channels)\n");
1514 		} else {
1515 			snd_iprintf(buffer, " (2 channels)\n");
1516 		}
1517 		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1518 			    snd_rme32_capture_getrate(rme32, &n));
1519 	}
1520 
1521 	snd_iprintf(buffer, "\nOutput settings\n");
1522 	if (rme32->wcreg & RME32_WCR_SEL) {
1523 		snd_iprintf(buffer, "  output signal: normal playback");
1524 	} else {
1525 		snd_iprintf(buffer, "  output signal: same as input");
1526 	}
1527 	if (rme32->wcreg & RME32_WCR_MUTE) {
1528 		snd_iprintf(buffer, " (muted)\n");
1529 	} else {
1530 		snd_iprintf(buffer, "\n");
1531 	}
1532 
1533 	/* master output frequency */
1534 	if (!
1535 	    ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1536 	     && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1537 		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1538 			    snd_rme32_playback_getrate(rme32));
1539 	}
1540 	if (rme32->rcreg & RME32_RCR_KMODE) {
1541 		snd_iprintf(buffer, "  sample clock source: AutoSync\n");
1542 	} else {
1543 		snd_iprintf(buffer, "  sample clock source: Internal\n");
1544 	}
1545 	if (rme32->wcreg & RME32_WCR_PRO) {
1546 		snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1547 	} else {
1548 		snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1549 	}
1550 	if (rme32->wcreg & RME32_WCR_EMP) {
1551 		snd_iprintf(buffer, "  emphasis: on\n");
1552 	} else {
1553 		snd_iprintf(buffer, "  emphasis: off\n");
1554 	}
1555 }
1556 
snd_rme32_proc_init(struct rme32 * rme32)1557 static void __devinit snd_rme32_proc_init(struct rme32 * rme32)
1558 {
1559 	struct snd_info_entry *entry;
1560 
1561 	if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1562 		snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1563 }
1564 
1565 /*
1566  * control interface
1567  */
1568 
1569 #define snd_rme32_info_loopback_control		snd_ctl_boolean_mono_info
1570 
1571 static int
snd_rme32_get_loopback_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1572 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1573 			       struct snd_ctl_elem_value *ucontrol)
1574 {
1575 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1576 
1577 	spin_lock_irq(&rme32->lock);
1578 	ucontrol->value.integer.value[0] =
1579 	    rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1580 	spin_unlock_irq(&rme32->lock);
1581 	return 0;
1582 }
1583 static int
snd_rme32_put_loopback_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1584 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1585 			       struct snd_ctl_elem_value *ucontrol)
1586 {
1587 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1588 	unsigned int val;
1589 	int change;
1590 
1591 	val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1592 	spin_lock_irq(&rme32->lock);
1593 	val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1594 	change = val != rme32->wcreg;
1595 	if (ucontrol->value.integer.value[0])
1596 		val &= ~RME32_WCR_MUTE;
1597 	else
1598 		val |= RME32_WCR_MUTE;
1599 	rme32->wcreg = val;
1600 	writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1601 	spin_unlock_irq(&rme32->lock);
1602 	return change;
1603 }
1604 
1605 static int
snd_rme32_info_inputtype_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1606 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1607 				 struct snd_ctl_elem_info *uinfo)
1608 {
1609 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1610 	static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1611 
1612 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1613 	uinfo->count = 1;
1614 	switch (rme32->pci->device) {
1615 	case PCI_DEVICE_ID_RME_DIGI32:
1616 	case PCI_DEVICE_ID_RME_DIGI32_8:
1617 		uinfo->value.enumerated.items = 3;
1618 		break;
1619 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1620 		uinfo->value.enumerated.items = 4;
1621 		break;
1622 	default:
1623 		snd_BUG();
1624 		break;
1625 	}
1626 	if (uinfo->value.enumerated.item >
1627 	    uinfo->value.enumerated.items - 1) {
1628 		uinfo->value.enumerated.item =
1629 		    uinfo->value.enumerated.items - 1;
1630 	}
1631 	strcpy(uinfo->value.enumerated.name,
1632 	       texts[uinfo->value.enumerated.item]);
1633 	return 0;
1634 }
1635 static int
snd_rme32_get_inputtype_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1636 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1637 				struct snd_ctl_elem_value *ucontrol)
1638 {
1639 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1640 	unsigned int items = 3;
1641 
1642 	spin_lock_irq(&rme32->lock);
1643 	ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1644 
1645 	switch (rme32->pci->device) {
1646 	case PCI_DEVICE_ID_RME_DIGI32:
1647 	case PCI_DEVICE_ID_RME_DIGI32_8:
1648 		items = 3;
1649 		break;
1650 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1651 		items = 4;
1652 		break;
1653 	default:
1654 		snd_BUG();
1655 		break;
1656 	}
1657 	if (ucontrol->value.enumerated.item[0] >= items) {
1658 		ucontrol->value.enumerated.item[0] = items - 1;
1659 	}
1660 
1661 	spin_unlock_irq(&rme32->lock);
1662 	return 0;
1663 }
1664 static int
snd_rme32_put_inputtype_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1665 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1666 				struct snd_ctl_elem_value *ucontrol)
1667 {
1668 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1669 	unsigned int val;
1670 	int change, items = 3;
1671 
1672 	switch (rme32->pci->device) {
1673 	case PCI_DEVICE_ID_RME_DIGI32:
1674 	case PCI_DEVICE_ID_RME_DIGI32_8:
1675 		items = 3;
1676 		break;
1677 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1678 		items = 4;
1679 		break;
1680 	default:
1681 		snd_BUG();
1682 		break;
1683 	}
1684 	val = ucontrol->value.enumerated.item[0] % items;
1685 
1686 	spin_lock_irq(&rme32->lock);
1687 	change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1688 	snd_rme32_setinputtype(rme32, val);
1689 	spin_unlock_irq(&rme32->lock);
1690 	return change;
1691 }
1692 
1693 static int
snd_rme32_info_clockmode_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1694 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1695 				 struct snd_ctl_elem_info *uinfo)
1696 {
1697 	static char *texts[4] = { "AutoSync",
1698 				  "Internal 32.0kHz",
1699 				  "Internal 44.1kHz",
1700 				  "Internal 48.0kHz" };
1701 
1702 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1703 	uinfo->count = 1;
1704 	uinfo->value.enumerated.items = 4;
1705 	if (uinfo->value.enumerated.item > 3) {
1706 		uinfo->value.enumerated.item = 3;
1707 	}
1708 	strcpy(uinfo->value.enumerated.name,
1709 	       texts[uinfo->value.enumerated.item]);
1710 	return 0;
1711 }
1712 static int
snd_rme32_get_clockmode_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1713 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1714 				struct snd_ctl_elem_value *ucontrol)
1715 {
1716 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1717 
1718 	spin_lock_irq(&rme32->lock);
1719 	ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1720 	spin_unlock_irq(&rme32->lock);
1721 	return 0;
1722 }
1723 static int
snd_rme32_put_clockmode_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1724 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1725 				struct snd_ctl_elem_value *ucontrol)
1726 {
1727 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1728 	unsigned int val;
1729 	int change;
1730 
1731 	val = ucontrol->value.enumerated.item[0] % 3;
1732 	spin_lock_irq(&rme32->lock);
1733 	change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1734 	snd_rme32_setclockmode(rme32, val);
1735 	spin_unlock_irq(&rme32->lock);
1736 	return change;
1737 }
1738 
snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)1739 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1740 {
1741 	u32 val = 0;
1742 	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1743 	if (val & RME32_WCR_PRO)
1744 		val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1745 	else
1746 		val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1747 	return val;
1748 }
1749 
snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes,u32 val)1750 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1751 {
1752 	aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1753 	if (val & RME32_WCR_PRO)
1754 		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1755 	else
1756 		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1757 }
1758 
snd_rme32_control_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1759 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1760 					struct snd_ctl_elem_info *uinfo)
1761 {
1762 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1763 	uinfo->count = 1;
1764 	return 0;
1765 }
1766 
snd_rme32_control_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1767 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1768 				       struct snd_ctl_elem_value *ucontrol)
1769 {
1770 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1771 
1772 	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1773 				 rme32->wcreg_spdif);
1774 	return 0;
1775 }
1776 
snd_rme32_control_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1777 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1778 				       struct snd_ctl_elem_value *ucontrol)
1779 {
1780 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1781 	int change;
1782 	u32 val;
1783 
1784 	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1785 	spin_lock_irq(&rme32->lock);
1786 	change = val != rme32->wcreg_spdif;
1787 	rme32->wcreg_spdif = val;
1788 	spin_unlock_irq(&rme32->lock);
1789 	return change;
1790 }
1791 
snd_rme32_control_spdif_stream_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1792 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1793 					       struct snd_ctl_elem_info *uinfo)
1794 {
1795 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1796 	uinfo->count = 1;
1797 	return 0;
1798 }
1799 
snd_rme32_control_spdif_stream_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1800 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1801 					      struct snd_ctl_elem_value *
1802 					      ucontrol)
1803 {
1804 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1805 
1806 	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1807 				 rme32->wcreg_spdif_stream);
1808 	return 0;
1809 }
1810 
snd_rme32_control_spdif_stream_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1811 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1812 					      struct snd_ctl_elem_value *
1813 					      ucontrol)
1814 {
1815 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1816 	int change;
1817 	u32 val;
1818 
1819 	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1820 	spin_lock_irq(&rme32->lock);
1821 	change = val != rme32->wcreg_spdif_stream;
1822 	rme32->wcreg_spdif_stream = val;
1823 	rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1824 	rme32->wcreg |= val;
1825 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1826 	spin_unlock_irq(&rme32->lock);
1827 	return change;
1828 }
1829 
snd_rme32_control_spdif_mask_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1830 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1831 					     struct snd_ctl_elem_info *uinfo)
1832 {
1833 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1834 	uinfo->count = 1;
1835 	return 0;
1836 }
1837 
snd_rme32_control_spdif_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1838 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1839 					    struct snd_ctl_elem_value *
1840 					    ucontrol)
1841 {
1842 	ucontrol->value.iec958.status[0] = kcontrol->private_value;
1843 	return 0;
1844 }
1845 
1846 static struct snd_kcontrol_new snd_rme32_controls[] = {
1847 	{
1848 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1849 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1850 		.info =	snd_rme32_control_spdif_info,
1851 		.get =	snd_rme32_control_spdif_get,
1852 		.put =	snd_rme32_control_spdif_put
1853 	},
1854 	{
1855 		.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1856 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1857 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1858 		.info =	snd_rme32_control_spdif_stream_info,
1859 		.get =	snd_rme32_control_spdif_stream_get,
1860 		.put =	snd_rme32_control_spdif_stream_put
1861 	},
1862 	{
1863 		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1864 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1865 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1866 		.info =	snd_rme32_control_spdif_mask_info,
1867 		.get =	snd_rme32_control_spdif_mask_get,
1868 		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1869 	},
1870 	{
1871 		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1872 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1873 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1874 		.info =	snd_rme32_control_spdif_mask_info,
1875 		.get =	snd_rme32_control_spdif_mask_get,
1876 		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1877 	},
1878 	{
1879 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1880 		.name =	"Input Connector",
1881 		.info =	snd_rme32_info_inputtype_control,
1882 		.get =	snd_rme32_get_inputtype_control,
1883 		.put =	snd_rme32_put_inputtype_control
1884 	},
1885 	{
1886 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1887 		.name =	"Loopback Input",
1888 		.info =	snd_rme32_info_loopback_control,
1889 		.get =	snd_rme32_get_loopback_control,
1890 		.put =	snd_rme32_put_loopback_control
1891 	},
1892 	{
1893 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1894 		.name =	"Sample Clock Source",
1895 		.info =	snd_rme32_info_clockmode_control,
1896 		.get =	snd_rme32_get_clockmode_control,
1897 		.put =	snd_rme32_put_clockmode_control
1898 	}
1899 };
1900 
snd_rme32_create_switches(struct snd_card * card,struct rme32 * rme32)1901 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1902 {
1903 	int idx, err;
1904 	struct snd_kcontrol *kctl;
1905 
1906 	for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1907 		if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1908 			return err;
1909 		if (idx == 1)	/* IEC958 (S/PDIF) Stream */
1910 			rme32->spdif_ctl = kctl;
1911 	}
1912 
1913 	return 0;
1914 }
1915 
1916 /*
1917  * Card initialisation
1918  */
1919 
snd_rme32_card_free(struct snd_card * card)1920 static void snd_rme32_card_free(struct snd_card *card)
1921 {
1922 	snd_rme32_free(card->private_data);
1923 }
1924 
1925 static int __devinit
snd_rme32_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1926 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1927 {
1928 	static int dev;
1929 	struct rme32 *rme32;
1930 	struct snd_card *card;
1931 	int err;
1932 
1933 	if (dev >= SNDRV_CARDS) {
1934 		return -ENODEV;
1935 	}
1936 	if (!enable[dev]) {
1937 		dev++;
1938 		return -ENOENT;
1939 	}
1940 
1941 	err = snd_card_create(index[dev], id[dev], THIS_MODULE,
1942 			      sizeof(struct rme32), &card);
1943 	if (err < 0)
1944 		return err;
1945 	card->private_free = snd_rme32_card_free;
1946 	rme32 = (struct rme32 *) card->private_data;
1947 	rme32->card = card;
1948 	rme32->pci = pci;
1949 	snd_card_set_dev(card, &pci->dev);
1950         if (fullduplex[dev])
1951 		rme32->fullduplex_mode = 1;
1952 	if ((err = snd_rme32_create(rme32)) < 0) {
1953 		snd_card_free(card);
1954 		return err;
1955 	}
1956 
1957 	strcpy(card->driver, "Digi32");
1958 	switch (rme32->pci->device) {
1959 	case PCI_DEVICE_ID_RME_DIGI32:
1960 		strcpy(card->shortname, "RME Digi32");
1961 		break;
1962 	case PCI_DEVICE_ID_RME_DIGI32_8:
1963 		strcpy(card->shortname, "RME Digi32/8");
1964 		break;
1965 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1966 		strcpy(card->shortname, "RME Digi32 PRO");
1967 		break;
1968 	}
1969 	sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1970 		card->shortname, rme32->rev, rme32->port, rme32->irq);
1971 
1972 	if ((err = snd_card_register(card)) < 0) {
1973 		snd_card_free(card);
1974 		return err;
1975 	}
1976 	pci_set_drvdata(pci, card);
1977 	dev++;
1978 	return 0;
1979 }
1980 
snd_rme32_remove(struct pci_dev * pci)1981 static void __devexit snd_rme32_remove(struct pci_dev *pci)
1982 {
1983 	snd_card_free(pci_get_drvdata(pci));
1984 	pci_set_drvdata(pci, NULL);
1985 }
1986 
1987 static struct pci_driver driver = {
1988 	.name =		KBUILD_MODNAME,
1989 	.id_table =	snd_rme32_ids,
1990 	.probe =	snd_rme32_probe,
1991 	.remove =	__devexit_p(snd_rme32_remove),
1992 };
1993 
alsa_card_rme32_init(void)1994 static int __init alsa_card_rme32_init(void)
1995 {
1996 	return pci_register_driver(&driver);
1997 }
1998 
alsa_card_rme32_exit(void)1999 static void __exit alsa_card_rme32_exit(void)
2000 {
2001 	pci_unregister_driver(&driver);
2002 }
2003 
2004 module_init(alsa_card_rme32_init)
2005 module_exit(alsa_card_rme32_exit)
2006