1 /* 2 * Marvell MBUS common definitions. 3 * 4 * Copyright (C) 2008 Marvell Semiconductor 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __LINUX_MBUS_H 12 #define __LINUX_MBUS_H 13 14 struct mbus_dram_target_info 15 { 16 /* 17 * The 4-bit MBUS target ID of the DRAM controller. 18 */ 19 u8 mbus_dram_target_id; 20 21 /* 22 * The base address, size, and MBUS attribute ID for each 23 * of the possible DRAM chip selects. Peripherals are 24 * required to support at least 4 decode windows. 25 */ 26 int num_cs; 27 struct mbus_dram_window { 28 u8 cs_index; 29 u8 mbus_attr; 30 u32 base; 31 u32 size; 32 } cs[4]; 33 }; 34 35 /* 36 * The Marvell mbus is to be found only on SOCs from the Orion family 37 * at the moment. Provide a dummy stub for other architectures. 38 */ 39 #ifdef CONFIG_PLAT_ORION 40 extern const struct mbus_dram_target_info *mv_mbus_dram_info(void); 41 #else mv_mbus_dram_info(void)42static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void) 43 { 44 return NULL; 45 } 46 #endif 47 #endif 48