1 /*
2  * Marvell 88SE94xx hardware specific head file
3  *
4  * Copyright 2007 Red Hat, Inc.
5  * Copyright 2008 Marvell. <kewei@marvell.com>
6  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
7  *
8  * This file is licensed under GPLv2.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; version 2 of the
13  * License.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23  * USA
24 */
25 
26 #ifndef _MVS94XX_REG_H_
27 #define _MVS94XX_REG_H_
28 
29 #include <linux/types.h>
30 
31 #define MAX_LINK_RATE		SAS_LINK_RATE_6_0_GBPS
32 
33 enum VANIR_REVISION_ID {
34 	VANIR_A0_REV		= 0xA0,
35 	VANIR_B0_REV		= 0x01,
36 	VANIR_C0_REV		= 0x02,
37 	VANIR_C1_REV		= 0x03,
38 	VANIR_C2_REV		= 0xC2,
39 };
40 
41 enum hw_registers {
42 	MVS_GBL_CTL		= 0x04,  /* global control */
43 	MVS_GBL_INT_STAT	= 0x00,  /* global irq status */
44 	MVS_GBL_PI		= 0x0C,  /* ports implemented bitmask */
45 
46 	MVS_PHY_CTL		= 0x40,  /* SOC PHY Control */
47 	MVS_PORTS_IMP		= 0x9C,  /* SOC Port Implemented */
48 
49 	MVS_GBL_PORT_TYPE	= 0xa0,  /* port type */
50 
51 	MVS_CTL			= 0x100, /* SAS/SATA port configuration */
52 	MVS_PCS			= 0x104, /* SAS/SATA port control/status */
53 	MVS_CMD_LIST_LO		= 0x108, /* cmd list addr */
54 	MVS_CMD_LIST_HI		= 0x10C,
55 	MVS_RX_FIS_LO		= 0x110, /* RX FIS list addr */
56 	MVS_RX_FIS_HI		= 0x114,
57 	MVS_STP_REG_SET_0	= 0x118, /* STP/SATA Register Set Enable */
58 	MVS_STP_REG_SET_1	= 0x11C,
59 	MVS_TX_CFG		= 0x120, /* TX configuration */
60 	MVS_TX_LO		= 0x124, /* TX (delivery) ring addr */
61 	MVS_TX_HI		= 0x128,
62 
63 	MVS_TX_PROD_IDX		= 0x12C, /* TX producer pointer */
64 	MVS_TX_CONS_IDX		= 0x130, /* TX consumer pointer (RO) */
65 	MVS_RX_CFG		= 0x134, /* RX configuration */
66 	MVS_RX_LO		= 0x138, /* RX (completion) ring addr */
67 	MVS_RX_HI		= 0x13C,
68 	MVS_RX_CONS_IDX		= 0x140, /* RX consumer pointer (RO) */
69 
70 	MVS_INT_COAL		= 0x148, /* Int coalescing config */
71 	MVS_INT_COAL_TMOUT	= 0x14C, /* Int coalescing timeout */
72 	MVS_INT_STAT		= 0x150, /* Central int status */
73 	MVS_INT_MASK		= 0x154, /* Central int enable */
74 	MVS_INT_STAT_SRS_0	= 0x158, /* SATA register set status */
75 	MVS_INT_MASK_SRS_0	= 0x15C,
76 	MVS_INT_STAT_SRS_1	= 0x160,
77 	MVS_INT_MASK_SRS_1	= 0x164,
78 	MVS_NON_NCQ_ERR_0	= 0x168, /* SRS Non-specific NCQ Error */
79 	MVS_NON_NCQ_ERR_1	= 0x16C,
80 	MVS_CMD_ADDR		= 0x170, /* Command register port (addr) */
81 	MVS_CMD_DATA		= 0x174, /* Command register port (data) */
82 	MVS_MEM_PARITY_ERR	= 0x178, /* Memory parity error */
83 
84 					 /* ports 1-3 follow after this */
85 	MVS_P0_INT_STAT		= 0x180, /* port0 interrupt status */
86 	MVS_P0_INT_MASK		= 0x184, /* port0 interrupt mask */
87 					 /* ports 5-7 follow after this */
88 	MVS_P4_INT_STAT		= 0x1A0, /* Port4 interrupt status */
89 	MVS_P4_INT_MASK		= 0x1A4, /* Port4 interrupt enable mask */
90 
91 					 /* ports 1-3 follow after this */
92 	MVS_P0_SER_CTLSTAT	= 0x1D0, /* port0 serial control/status */
93 					 /* ports 5-7 follow after this */
94 	MVS_P4_SER_CTLSTAT	= 0x1E0, /* port4 serial control/status */
95 
96 					 /* ports 1-3 follow after this */
97 	MVS_P0_CFG_ADDR		= 0x200, /* port0 phy register address */
98 	MVS_P0_CFG_DATA		= 0x204, /* port0 phy register data */
99 					 /* ports 5-7 follow after this */
100 	MVS_P4_CFG_ADDR		= 0x220, /* Port4 config address */
101 	MVS_P4_CFG_DATA		= 0x224, /* Port4 config data */
102 
103 					 /* phys 1-3 follow after this */
104 	MVS_P0_VSR_ADDR		= 0x250, /* phy0 VSR address */
105 	MVS_P0_VSR_DATA		= 0x254, /* phy0 VSR data */
106 					 /* phys 1-3 follow after this */
107 					 /* multiplexing */
108 	MVS_P4_VSR_ADDR 	= 0x250, /* phy4 VSR address */
109 	MVS_P4_VSR_DATA 	= 0x254, /* phy4 VSR data */
110 	MVS_PA_VSR_ADDR		= 0x290, /* All port VSR addr */
111 	MVS_PA_VSR_PORT		= 0x294, /* All port VSR data */
112 	MVS_COMMAND_ACTIVE	= 0x300,
113 };
114 
115 enum pci_cfg_registers {
116 	PCR_PHY_CTL		= 0x40,
117 	PCR_PHY_CTL2		= 0x90,
118 	PCR_DEV_CTRL		= 0x78,
119 	PCR_LINK_STAT		= 0x82,
120 };
121 
122 /*  SAS/SATA Vendor Specific Port Registers */
123 enum sas_sata_vsp_regs {
124 	VSR_PHY_STAT		= 0x00 * 4, /* Phy Interrupt Status */
125 	VSR_PHY_MODE1		= 0x01 * 4, /* phy Interrupt Enable */
126 	VSR_PHY_MODE2		= 0x02 * 4, /* Phy Configuration */
127 	VSR_PHY_MODE3		= 0x03 * 4, /* Phy Status */
128 	VSR_PHY_MODE4		= 0x04 * 4, /* Phy Counter 0 */
129 	VSR_PHY_MODE5		= 0x05 * 4, /* Phy Counter 1 */
130 	VSR_PHY_MODE6		= 0x06 * 4, /* Event Counter Control */
131 	VSR_PHY_MODE7		= 0x07 * 4, /* Event Counter Select */
132 	VSR_PHY_MODE8		= 0x08 * 4, /* Event Counter 0 */
133 	VSR_PHY_MODE9		= 0x09 * 4, /* Event Counter 1 */
134 	VSR_PHY_MODE10		= 0x0A * 4, /* Event Counter 2 */
135 	VSR_PHY_MODE11		= 0x0B * 4, /* Event Counter 3 */
136 	VSR_PHY_ACT_LED		= 0x0C * 4, /* Activity LED control */
137 
138 	VSR_PHY_FFE_CONTROL	= 0x10C,
139 	VSR_PHY_DFE_UPDATE_CRTL	= 0x110,
140 	VSR_REF_CLOCK_CRTL	= 0x1A0,
141 };
142 
143 enum chip_register_bits {
144 	PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
145 	PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
146 	PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
147 	PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
148 			(0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
149 };
150 
151 enum pci_interrupt_cause {
152 	/*  MAIN_IRQ_CAUSE (R10200) Bits*/
153 	IRQ_COM_IN_I2O_IOP0            = (1 << 0),
154 	IRQ_COM_IN_I2O_IOP1            = (1 << 1),
155 	IRQ_COM_IN_I2O_IOP2            = (1 << 2),
156 	IRQ_COM_IN_I2O_IOP3            = (1 << 3),
157 	IRQ_COM_OUT_I2O_HOS0           = (1 << 4),
158 	IRQ_COM_OUT_I2O_HOS1           = (1 << 5),
159 	IRQ_COM_OUT_I2O_HOS2           = (1 << 6),
160 	IRQ_COM_OUT_I2O_HOS3           = (1 << 7),
161 	IRQ_PCIF_TO_CPU_DRBL0          = (1 << 8),
162 	IRQ_PCIF_TO_CPU_DRBL1          = (1 << 9),
163 	IRQ_PCIF_TO_CPU_DRBL2          = (1 << 10),
164 	IRQ_PCIF_TO_CPU_DRBL3          = (1 << 11),
165 	IRQ_PCIF_DRBL0                 = (1 << 12),
166 	IRQ_PCIF_DRBL1                 = (1 << 13),
167 	IRQ_PCIF_DRBL2                 = (1 << 14),
168 	IRQ_PCIF_DRBL3                 = (1 << 15),
169 	IRQ_XOR_A                      = (1 << 16),
170 	IRQ_XOR_B                      = (1 << 17),
171 	IRQ_SAS_A                      = (1 << 18),
172 	IRQ_SAS_B                      = (1 << 19),
173 	IRQ_CPU_CNTRL                  = (1 << 20),
174 	IRQ_GPIO                       = (1 << 21),
175 	IRQ_UART                       = (1 << 22),
176 	IRQ_SPI                        = (1 << 23),
177 	IRQ_I2C                        = (1 << 24),
178 	IRQ_SGPIO                      = (1 << 25),
179 	IRQ_COM_ERR                    = (1 << 29),
180 	IRQ_I2O_ERR                    = (1 << 30),
181 	IRQ_PCIE_ERR                   = (1 << 31),
182 };
183 
184 union reg_phy_cfg {
185 	u32 v;
186 	struct {
187 		u32 phy_reset:1;
188 		u32 sas_support:1;
189 		u32 sata_support:1;
190 		u32 sata_host_mode:1;
191 		/*
192 		 * bit 2: 6Gbps support
193 		 * bit 1: 3Gbps support
194 		 * bit 0: 1.5Gbps support
195 		 */
196 		u32 speed_support:3;
197 		u32 snw_3_support:1;
198 		u32 tx_lnk_parity:1;
199 		/*
200 		 * bit 5: G1 (1.5Gbps) Without SSC
201 		 * bit 4: G1 (1.5Gbps) with SSC
202 		 * bit 3: G2 (3.0Gbps) Without SSC
203 		 * bit 2: G2 (3.0Gbps) with SSC
204 		 * bit 1: G3 (6.0Gbps) without SSC
205 		 * bit 0: G3 (6.0Gbps) with SSC
206 		 */
207 		u32 tx_spt_phs_lnk_rate:6;
208 		/* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
209 		u32 tx_lgcl_lnk_rate:4;
210 		u32 tx_ssc_type:1;
211 		u32 sata_spin_up_spt:1;
212 		u32 sata_spin_up_en:1;
213 		u32 bypass_oob:1;
214 		u32 disable_phy:1;
215 		u32 rsvd:8;
216 	} u;
217 };
218 
219 #define MAX_SG_ENTRY		255
220 
221 struct mvs_prd_imt {
222 #ifndef __BIG_ENDIAN
223 	__le32			len:22;
224 	u8			_r_a:2;
225 	u8			misc_ctl:4;
226 	u8			inter_sel:4;
227 #else
228 	u32			inter_sel:4;
229 	u32			misc_ctl:4;
230 	u32			_r_a:2;
231 	u32			len:22;
232 #endif
233 };
234 
235 struct mvs_prd {
236 	/* 64-bit buffer address */
237 	__le64			addr;
238 	/* 22-bit length */
239 	__le32			im_len;
240 } __attribute__ ((packed));
241 
242 /*
243  * these registers are accessed through port vendor
244  * specific address/data registers
245  */
246 enum sas_sata_phy_regs {
247 	GENERATION_1_SETTING		= 0x118,
248 	GENERATION_1_2_SETTING		= 0x11C,
249 	GENERATION_2_3_SETTING		= 0x120,
250 	GENERATION_3_4_SETTING		= 0x124,
251 };
252 
253 #define SPI_CTRL_REG_94XX           	0xc800
254 #define SPI_ADDR_REG_94XX            	0xc804
255 #define SPI_WR_DATA_REG_94XX         0xc808
256 #define SPI_RD_DATA_REG_94XX         	0xc80c
257 #define SPI_CTRL_READ_94XX         	(1U << 2)
258 #define SPI_ADDR_VLD_94XX         	(1U << 1)
259 #define SPI_CTRL_SpiStart_94XX     	(1U << 0)
260 
261 static inline int
mv_ffc64(u64 v)262 mv_ffc64(u64 v)
263 {
264 	u64 x = ~v;
265 	return x ? __ffs64(x) : -1;
266 }
267 
268 #define r_reg_set_enable(i) \
269 	(((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
270 	mr32(MVS_STP_REG_SET_0))
271 
272 #define w_reg_set_enable(i, tmp) \
273 	(((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
274 	mw32(MVS_STP_REG_SET_0, tmp))
275 
276 extern const struct mvs_dispatch mvs_94xx_dispatch;
277 #endif
278 
279