1 /*
2 * DaVinci MDIO Module driver
3 *
4 * Copyright (C) 2010 Texas Instruments.
5 *
6 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
7 *
8 * Copyright (C) 2009 Texas Instruments.
9 *
10 * ---------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ---------------------------------------------------------------------------
26 */
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/io.h>
37 #include <linux/davinci_emac.h>
38
39 /*
40 * This timeout definition is a worst-case ultra defensive measure against
41 * unexpected controller lock ups. Ideally, we should never ever hit this
42 * scenario in practice.
43 */
44 #define MDIO_TIMEOUT 100 /* msecs */
45
46 #define PHY_REG_MASK 0x1f
47 #define PHY_ID_MASK 0x1f
48
49 #define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
50
51 struct davinci_mdio_regs {
52 u32 version;
53 u32 control;
54 #define CONTROL_IDLE BIT(31)
55 #define CONTROL_ENABLE BIT(30)
56 #define CONTROL_MAX_DIV (0xffff)
57
58 u32 alive;
59 u32 link;
60 u32 linkintraw;
61 u32 linkintmasked;
62 u32 __reserved_0[2];
63 u32 userintraw;
64 u32 userintmasked;
65 u32 userintmaskset;
66 u32 userintmaskclr;
67 u32 __reserved_1[20];
68
69 struct {
70 u32 access;
71 #define USERACCESS_GO BIT(31)
72 #define USERACCESS_WRITE BIT(30)
73 #define USERACCESS_ACK BIT(29)
74 #define USERACCESS_READ (0)
75 #define USERACCESS_DATA (0xffff)
76
77 u32 physel;
78 } user[0];
79 };
80
81 struct mdio_platform_data default_pdata = {
82 .bus_freq = DEF_OUT_FREQ,
83 };
84
85 struct davinci_mdio_data {
86 struct mdio_platform_data pdata;
87 struct davinci_mdio_regs __iomem *regs;
88 spinlock_t lock;
89 struct clk *clk;
90 struct device *dev;
91 struct mii_bus *bus;
92 bool suspended;
93 unsigned long access_time; /* jiffies */
94 };
95
__davinci_mdio_reset(struct davinci_mdio_data * data)96 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
97 {
98 u32 mdio_in, div, mdio_out_khz, access_time;
99
100 mdio_in = clk_get_rate(data->clk);
101 div = (mdio_in / data->pdata.bus_freq) - 1;
102 if (div > CONTROL_MAX_DIV)
103 div = CONTROL_MAX_DIV;
104
105 /* set enable and clock divider */
106 __raw_writel(div | CONTROL_ENABLE, &data->regs->control);
107
108 /*
109 * One mdio transaction consists of:
110 * 32 bits of preamble
111 * 32 bits of transferred data
112 * 24 bits of bus yield (not needed unless shared?)
113 */
114 mdio_out_khz = mdio_in / (1000 * (div + 1));
115 access_time = (88 * 1000) / mdio_out_khz;
116
117 /*
118 * In the worst case, we could be kicking off a user-access immediately
119 * after the mdio bus scan state-machine triggered its own read. If
120 * so, our request could get deferred by one access cycle. We
121 * defensively allow for 4 access cycles.
122 */
123 data->access_time = usecs_to_jiffies(access_time * 4);
124 if (!data->access_time)
125 data->access_time = 1;
126 }
127
davinci_mdio_reset(struct mii_bus * bus)128 static int davinci_mdio_reset(struct mii_bus *bus)
129 {
130 struct davinci_mdio_data *data = bus->priv;
131 u32 phy_mask, ver;
132
133 __davinci_mdio_reset(data);
134
135 /* wait for scan logic to settle */
136 msleep(PHY_MAX_ADDR * data->access_time);
137
138 /* dump hardware version info */
139 ver = __raw_readl(&data->regs->version);
140 dev_info(data->dev, "davinci mdio revision %d.%d\n",
141 (ver >> 8) & 0xff, ver & 0xff);
142
143 /* get phy mask from the alive register */
144 phy_mask = __raw_readl(&data->regs->alive);
145 if (phy_mask) {
146 /* restrict mdio bus to live phys only */
147 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
148 phy_mask = ~phy_mask;
149 } else {
150 /* desperately scan all phys */
151 dev_warn(data->dev, "no live phy, scanning all\n");
152 phy_mask = 0;
153 }
154 data->bus->phy_mask = phy_mask;
155
156 return 0;
157 }
158
159 /* wait until hardware is ready for another user access */
wait_for_user_access(struct davinci_mdio_data * data)160 static inline int wait_for_user_access(struct davinci_mdio_data *data)
161 {
162 struct davinci_mdio_regs __iomem *regs = data->regs;
163 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
164 u32 reg;
165
166 while (time_after(timeout, jiffies)) {
167 reg = __raw_readl(®s->user[0].access);
168 if ((reg & USERACCESS_GO) == 0)
169 return 0;
170
171 reg = __raw_readl(®s->control);
172 if ((reg & CONTROL_IDLE) == 0)
173 continue;
174
175 /*
176 * An emac soft_reset may have clobbered the mdio controller's
177 * state machine. We need to reset and retry the current
178 * operation
179 */
180 dev_warn(data->dev, "resetting idled controller\n");
181 __davinci_mdio_reset(data);
182 return -EAGAIN;
183 }
184
185 reg = __raw_readl(®s->user[0].access);
186 if ((reg & USERACCESS_GO) == 0)
187 return 0;
188
189 dev_err(data->dev, "timed out waiting for user access\n");
190 return -ETIMEDOUT;
191 }
192
193 /* wait until hardware state machine is idle */
wait_for_idle(struct davinci_mdio_data * data)194 static inline int wait_for_idle(struct davinci_mdio_data *data)
195 {
196 struct davinci_mdio_regs __iomem *regs = data->regs;
197 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
198
199 while (time_after(timeout, jiffies)) {
200 if (__raw_readl(®s->control) & CONTROL_IDLE)
201 return 0;
202 }
203 dev_err(data->dev, "timed out waiting for idle\n");
204 return -ETIMEDOUT;
205 }
206
davinci_mdio_read(struct mii_bus * bus,int phy_id,int phy_reg)207 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
208 {
209 struct davinci_mdio_data *data = bus->priv;
210 u32 reg;
211 int ret;
212
213 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
214 return -EINVAL;
215
216 spin_lock(&data->lock);
217
218 if (data->suspended) {
219 spin_unlock(&data->lock);
220 return -ENODEV;
221 }
222
223 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
224 (phy_id << 16));
225
226 while (1) {
227 ret = wait_for_user_access(data);
228 if (ret == -EAGAIN)
229 continue;
230 if (ret < 0)
231 break;
232
233 __raw_writel(reg, &data->regs->user[0].access);
234
235 ret = wait_for_user_access(data);
236 if (ret == -EAGAIN)
237 continue;
238 if (ret < 0)
239 break;
240
241 reg = __raw_readl(&data->regs->user[0].access);
242 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
243 break;
244 }
245
246 spin_unlock(&data->lock);
247
248 return ret;
249 }
250
davinci_mdio_write(struct mii_bus * bus,int phy_id,int phy_reg,u16 phy_data)251 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
252 int phy_reg, u16 phy_data)
253 {
254 struct davinci_mdio_data *data = bus->priv;
255 u32 reg;
256 int ret;
257
258 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
259 return -EINVAL;
260
261 spin_lock(&data->lock);
262
263 if (data->suspended) {
264 spin_unlock(&data->lock);
265 return -ENODEV;
266 }
267
268 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
269 (phy_id << 16) | (phy_data & USERACCESS_DATA));
270
271 while (1) {
272 ret = wait_for_user_access(data);
273 if (ret == -EAGAIN)
274 continue;
275 if (ret < 0)
276 break;
277
278 __raw_writel(reg, &data->regs->user[0].access);
279
280 ret = wait_for_user_access(data);
281 if (ret == -EAGAIN)
282 continue;
283 break;
284 }
285
286 spin_unlock(&data->lock);
287
288 return 0;
289 }
290
davinci_mdio_probe(struct platform_device * pdev)291 static int __devinit davinci_mdio_probe(struct platform_device *pdev)
292 {
293 struct mdio_platform_data *pdata = pdev->dev.platform_data;
294 struct device *dev = &pdev->dev;
295 struct davinci_mdio_data *data;
296 struct resource *res;
297 struct phy_device *phy;
298 int ret, addr;
299
300 data = kzalloc(sizeof(*data), GFP_KERNEL);
301 if (!data) {
302 dev_err(dev, "failed to alloc device data\n");
303 return -ENOMEM;
304 }
305
306 data->pdata = pdata ? (*pdata) : default_pdata;
307
308 data->bus = mdiobus_alloc();
309 if (!data->bus) {
310 dev_err(dev, "failed to alloc mii bus\n");
311 ret = -ENOMEM;
312 goto bail_out;
313 }
314
315 data->bus->name = dev_name(dev);
316 data->bus->read = davinci_mdio_read,
317 data->bus->write = davinci_mdio_write,
318 data->bus->reset = davinci_mdio_reset,
319 data->bus->parent = dev;
320 data->bus->priv = data;
321 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
322 pdev->name, pdev->id);
323
324 data->clk = clk_get(dev, NULL);
325 if (IS_ERR(data->clk)) {
326 dev_err(dev, "failed to get device clock\n");
327 ret = PTR_ERR(data->clk);
328 data->clk = NULL;
329 goto bail_out;
330 }
331
332 clk_enable(data->clk);
333
334 dev_set_drvdata(dev, data);
335 data->dev = dev;
336 spin_lock_init(&data->lock);
337
338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339 if (!res) {
340 dev_err(dev, "could not find register map resource\n");
341 ret = -ENOENT;
342 goto bail_out;
343 }
344
345 res = devm_request_mem_region(dev, res->start, resource_size(res),
346 dev_name(dev));
347 if (!res) {
348 dev_err(dev, "could not allocate register map resource\n");
349 ret = -ENXIO;
350 goto bail_out;
351 }
352
353 data->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
354 if (!data->regs) {
355 dev_err(dev, "could not map mdio registers\n");
356 ret = -ENOMEM;
357 goto bail_out;
358 }
359
360 /* register the mii bus */
361 ret = mdiobus_register(data->bus);
362 if (ret)
363 goto bail_out;
364
365 /* scan and dump the bus */
366 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
367 phy = data->bus->phy_map[addr];
368 if (phy) {
369 dev_info(dev, "phy[%d]: device %s, driver %s\n",
370 phy->addr, dev_name(&phy->dev),
371 phy->drv ? phy->drv->name : "unknown");
372 }
373 }
374
375 return 0;
376
377 bail_out:
378 if (data->bus)
379 mdiobus_free(data->bus);
380
381 if (data->clk) {
382 clk_disable(data->clk);
383 clk_put(data->clk);
384 }
385
386 kfree(data);
387
388 return ret;
389 }
390
davinci_mdio_remove(struct platform_device * pdev)391 static int __devexit davinci_mdio_remove(struct platform_device *pdev)
392 {
393 struct device *dev = &pdev->dev;
394 struct davinci_mdio_data *data = dev_get_drvdata(dev);
395
396 if (data->bus)
397 mdiobus_free(data->bus);
398
399 if (data->clk) {
400 clk_disable(data->clk);
401 clk_put(data->clk);
402 }
403
404 dev_set_drvdata(dev, NULL);
405
406 kfree(data);
407
408 return 0;
409 }
410
davinci_mdio_suspend(struct device * dev)411 static int davinci_mdio_suspend(struct device *dev)
412 {
413 struct davinci_mdio_data *data = dev_get_drvdata(dev);
414 u32 ctrl;
415
416 spin_lock(&data->lock);
417
418 /* shutdown the scan state machine */
419 ctrl = __raw_readl(&data->regs->control);
420 ctrl &= ~CONTROL_ENABLE;
421 __raw_writel(ctrl, &data->regs->control);
422 wait_for_idle(data);
423
424 if (data->clk)
425 clk_disable(data->clk);
426
427 data->suspended = true;
428 spin_unlock(&data->lock);
429
430 return 0;
431 }
432
davinci_mdio_resume(struct device * dev)433 static int davinci_mdio_resume(struct device *dev)
434 {
435 struct davinci_mdio_data *data = dev_get_drvdata(dev);
436 u32 ctrl;
437
438 spin_lock(&data->lock);
439 if (data->clk)
440 clk_enable(data->clk);
441
442 /* restart the scan state machine */
443 ctrl = __raw_readl(&data->regs->control);
444 ctrl |= CONTROL_ENABLE;
445 __raw_writel(ctrl, &data->regs->control);
446
447 data->suspended = false;
448 spin_unlock(&data->lock);
449
450 return 0;
451 }
452
453 static const struct dev_pm_ops davinci_mdio_pm_ops = {
454 .suspend = davinci_mdio_suspend,
455 .resume = davinci_mdio_resume,
456 };
457
458 static struct platform_driver davinci_mdio_driver = {
459 .driver = {
460 .name = "davinci_mdio",
461 .owner = THIS_MODULE,
462 .pm = &davinci_mdio_pm_ops,
463 },
464 .probe = davinci_mdio_probe,
465 .remove = __devexit_p(davinci_mdio_remove),
466 };
467
davinci_mdio_init(void)468 static int __init davinci_mdio_init(void)
469 {
470 return platform_driver_register(&davinci_mdio_driver);
471 }
472 device_initcall(davinci_mdio_init);
473
davinci_mdio_exit(void)474 static void __exit davinci_mdio_exit(void)
475 {
476 platform_driver_unregister(&davinci_mdio_driver);
477 }
478 module_exit(davinci_mdio_exit);
479
480 MODULE_LICENSE("GPL");
481 MODULE_DESCRIPTION("DaVinci MDIO driver");
482