1config STMMAC_ETH
2	tristate "STMicroelectronics 10/100/1000 Ethernet driver"
3	depends on HAS_IOMEM
4	select NET_CORE
5	select MII
6	select PHYLIB
7	select CRC32
8	---help---
9	  This is the driver for the Ethernet IPs are built around a
10	  Synopsys IP Core and only tested on the STMicroelectronics
11	  platforms.
12
13if STMMAC_ETH
14
15config STMMAC_PLATFORM
16	tristate "STMMAC platform bus support"
17	depends on STMMAC_ETH
18	default y
19	---help---
20	  This selects the platform specific bus support for
21	  the stmmac device driver. This is the driver used
22	  on many embedded STM platforms based on ARM and SuperH
23	  processors.
24	  If you have a controller with this interface, say Y or M here.
25
26	  If unsure, say N.
27
28config STMMAC_PCI
29	tristate "STMMAC support on PCI bus (EXPERIMENTAL)"
30	depends on STMMAC_ETH && PCI && EXPERIMENTAL
31	---help---
32	  This is to select the Synopsys DWMAC available on PCI devices,
33	  if you have a controller with this interface, say Y or M here.
34
35	  This PCI support is tested on XLINX XC2V3000 FF1152AMT0221
36	  D1215994A VIRTEX FPGA board.
37
38	  If unsure, say N.
39
40config STMMAC_DEBUG_FS
41	bool "Enable monitoring via sysFS "
42	default n
43	depends on STMMAC_ETH && DEBUG_FS
44	---help---
45	  The stmmac entry in /sys reports DMA TX/RX rings
46	  or (if supported) the HW cap register.
47
48config STMMAC_DA
49	bool "STMMAC DMA arbitration scheme"
50	default n
51	---help---
52	  Selecting this option, rx has priority over Tx (only for Giga
53	  Ethernet device).
54	  By default, the DMA arbitration scheme is based on Round-robin
55	  (rx:tx priority is 1:1).
56
57config STMMAC_TIMER
58	bool "STMMAC Timer optimisation"
59	default n
60	depends on RTC_HCTOSYS_DEVICE
61	---help---
62	  Use an external timer for mitigating the number of network
63	  interrupts. Currently, for SH architectures, it is possible
64	  to use the TMU channel 2 and the SH-RTC device.
65
66choice
67        prompt "Select Timer device"
68        depends on STMMAC_TIMER
69
70config STMMAC_TMU_TIMER
71        bool "TMU channel 2"
72        depends on CPU_SH4
73	---help---
74
75config STMMAC_RTC_TIMER
76        bool "Real time clock"
77        depends on RTC_CLASS
78	---help---
79
80endchoice
81
82choice
83	prompt "Select the DMA TX/RX descriptor operating modes"
84	depends on STMMAC_ETH
85	---help---
86	  This driver supports DMA descriptor to operate both in dual buffer
87	  (RING) and linked-list(CHAINED) mode. In RING mode each descriptor
88	  points to two data buffer pointers whereas in CHAINED mode they
89	  points to only one data buffer pointer.
90
91config STMMAC_RING
92	bool "Enable Descriptor Ring Mode"
93
94config STMMAC_CHAINED
95	bool "Enable Descriptor Chained Mode"
96
97endchoice
98
99
100endif
101