1 /*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include "drmP.h"
26
27 #include "nouveau_drv.h"
28 #include "nouveau_i2c.h"
29 #include "nouveau_connector.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_crtc.h"
32 #include "nouveau_gpio.h"
33
34 /******************************************************************************
35 * aux channel util functions
36 *****************************************************************************/
37 #define AUX_DBG(fmt, args...) do { \
38 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) { \
39 NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args); \
40 } \
41 } while (0)
42 #define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
43
44 static void
auxch_fini(struct drm_device * dev,int ch)45 auxch_fini(struct drm_device *dev, int ch)
46 {
47 nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
48 }
49
50 static int
auxch_init(struct drm_device * dev,int ch)51 auxch_init(struct drm_device *dev, int ch)
52 {
53 const u32 unksel = 1; /* nfi which to use, or if it matters.. */
54 const u32 ureq = unksel ? 0x00100000 : 0x00200000;
55 const u32 urep = unksel ? 0x01000000 : 0x02000000;
56 u32 ctrl, timeout;
57
58 /* wait up to 1ms for any previous transaction to be done... */
59 timeout = 1000;
60 do {
61 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
62 udelay(1);
63 if (!timeout--) {
64 AUX_ERR("begin idle timeout 0x%08x", ctrl);
65 return -EBUSY;
66 }
67 } while (ctrl & 0x03010000);
68
69 /* set some magic, and wait up to 1ms for it to appear */
70 nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
71 timeout = 1000;
72 do {
73 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
74 udelay(1);
75 if (!timeout--) {
76 AUX_ERR("magic wait 0x%08x\n", ctrl);
77 auxch_fini(dev, ch);
78 return -EBUSY;
79 }
80 } while ((ctrl & 0x03000000) != urep);
81
82 return 0;
83 }
84
85 static int
auxch_tx(struct drm_device * dev,int ch,u8 type,u32 addr,u8 * data,u8 size)86 auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
87 {
88 u32 ctrl, stat, timeout, retries;
89 u32 xbuf[4] = {};
90 int ret, i;
91
92 AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
93
94 ret = auxch_init(dev, ch);
95 if (ret)
96 goto out;
97
98 stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
99 if (!(stat & 0x10000000)) {
100 AUX_DBG("sink not detected\n");
101 ret = -ENXIO;
102 goto out;
103 }
104
105 if (!(type & 1)) {
106 memcpy(xbuf, data, size);
107 for (i = 0; i < 16; i += 4) {
108 AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
109 nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
110 }
111 }
112
113 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
114 ctrl &= ~0x0001f0ff;
115 ctrl |= type << 12;
116 ctrl |= size - 1;
117 nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
118
119 /* retry transaction a number of times on failure... */
120 ret = -EREMOTEIO;
121 for (retries = 0; retries < 32; retries++) {
122 /* reset, and delay a while if this is a retry */
123 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
124 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
125 if (retries)
126 udelay(400);
127
128 /* transaction request, wait up to 1ms for it to complete */
129 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
130
131 timeout = 1000;
132 do {
133 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
134 udelay(1);
135 if (!timeout--) {
136 AUX_ERR("tx req timeout 0x%08x\n", ctrl);
137 goto out;
138 }
139 } while (ctrl & 0x00010000);
140
141 /* read status, and check if transaction completed ok */
142 stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
143 if (!(stat & 0x000f0f00)) {
144 ret = 0;
145 break;
146 }
147
148 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
149 }
150
151 if (type & 1) {
152 for (i = 0; i < 16; i += 4) {
153 xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
154 AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
155 }
156 memcpy(data, xbuf, size);
157 }
158
159 out:
160 auxch_fini(dev, ch);
161 return ret;
162 }
163
164 u8 *
nouveau_dp_bios_data(struct drm_device * dev,struct dcb_entry * dcb,u8 ** entry)165 nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
166 {
167 struct bit_entry d;
168 u8 *table;
169 int i;
170
171 if (bit_table(dev, 'd', &d)) {
172 NV_ERROR(dev, "BIT 'd' table not found\n");
173 return NULL;
174 }
175
176 if (d.version != 1) {
177 NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
178 return NULL;
179 }
180
181 table = ROMPTR(dev, d.data[0]);
182 if (!table) {
183 NV_ERROR(dev, "displayport table pointer invalid\n");
184 return NULL;
185 }
186
187 switch (table[0]) {
188 case 0x20:
189 case 0x21:
190 case 0x30:
191 case 0x40:
192 break;
193 default:
194 NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
195 return NULL;
196 }
197
198 for (i = 0; i < table[3]; i++) {
199 *entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
200 if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
201 return table;
202 }
203
204 NV_ERROR(dev, "displayport encoder table not found\n");
205 return NULL;
206 }
207
208 /******************************************************************************
209 * link training
210 *****************************************************************************/
211 struct dp_state {
212 struct dp_train_func *func;
213 struct dcb_entry *dcb;
214 int auxch;
215 int crtc;
216 u8 *dpcd;
217 int link_nr;
218 u32 link_bw;
219 u8 stat[6];
220 u8 conf[4];
221 };
222
223 static void
dp_set_link_config(struct drm_device * dev,struct dp_state * dp)224 dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
225 {
226 u8 sink[2];
227
228 NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
229
230 /* set desired link configuration on the source */
231 dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
232 dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
233
234 /* inform the sink of the new configuration */
235 sink[0] = dp->link_bw / 27000;
236 sink[1] = dp->link_nr;
237 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
238 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
239
240 auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
241 }
242
243 static void
dp_set_training_pattern(struct drm_device * dev,struct dp_state * dp,u8 pattern)244 dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
245 {
246 u8 sink_tp;
247
248 NV_DEBUG_KMS(dev, "training pattern %d\n", pattern);
249
250 dp->func->train_set(dev, dp->dcb, pattern);
251
252 auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
253 sink_tp &= ~DP_TRAINING_PATTERN_MASK;
254 sink_tp |= pattern;
255 auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
256 }
257
258 static int
dp_link_train_commit(struct drm_device * dev,struct dp_state * dp)259 dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
260 {
261 int i;
262
263 for (i = 0; i < dp->link_nr; i++) {
264 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
265 u8 lpre = (lane & 0x0c) >> 2;
266 u8 lvsw = (lane & 0x03) >> 0;
267
268 dp->conf[i] = (lpre << 3) | lvsw;
269 if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
270 dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
271 if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
272 dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
273
274 NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
275 dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
276 }
277
278 return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
279 }
280
281 static int
dp_link_train_update(struct drm_device * dev,struct dp_state * dp,u32 delay)282 dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
283 {
284 int ret;
285
286 udelay(delay);
287
288 ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
289 if (ret)
290 return ret;
291
292 NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
293 dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
294 dp->stat[4], dp->stat[5]);
295 return 0;
296 }
297
298 static int
dp_link_train_cr(struct drm_device * dev,struct dp_state * dp)299 dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
300 {
301 bool cr_done = false, abort = false;
302 int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
303 int tries = 0, i;
304
305 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
306
307 do {
308 if (dp_link_train_commit(dev, dp) ||
309 dp_link_train_update(dev, dp, 100))
310 break;
311
312 cr_done = true;
313 for (i = 0; i < dp->link_nr; i++) {
314 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
315 if (!(lane & DP_LANE_CR_DONE)) {
316 cr_done = false;
317 if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
318 abort = true;
319 break;
320 }
321 }
322
323 if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
324 voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
325 tries = 0;
326 }
327 } while (!cr_done && !abort && ++tries < 5);
328
329 return cr_done ? 0 : -1;
330 }
331
332 static int
dp_link_train_eq(struct drm_device * dev,struct dp_state * dp)333 dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
334 {
335 bool eq_done, cr_done = true;
336 int tries = 0, i;
337
338 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
339
340 do {
341 if (dp_link_train_update(dev, dp, 400))
342 break;
343
344 eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
345 for (i = 0; i < dp->link_nr && eq_done; i++) {
346 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
347 if (!(lane & DP_LANE_CR_DONE))
348 cr_done = false;
349 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
350 !(lane & DP_LANE_SYMBOL_LOCKED))
351 eq_done = false;
352 }
353
354 if (dp_link_train_commit(dev, dp))
355 break;
356 } while (!eq_done && cr_done && ++tries <= 5);
357
358 return eq_done ? 0 : -1;
359 }
360
361 static void
dp_set_downspread(struct drm_device * dev,struct dp_state * dp,bool enable)362 dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
363 {
364 u16 script = 0x0000;
365 u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
366 if (table) {
367 if (table[0] >= 0x20 && table[0] <= 0x30) {
368 if (enable) script = ROM16(entry[12]);
369 else script = ROM16(entry[14]);
370 } else
371 if (table[0] == 0x40) {
372 if (enable) script = ROM16(entry[11]);
373 else script = ROM16(entry[13]);
374 }
375 }
376
377 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
378 }
379
380 static void
dp_link_train_init(struct drm_device * dev,struct dp_state * dp)381 dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
382 {
383 u16 script = 0x0000;
384 u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
385 if (table) {
386 if (table[0] >= 0x20 && table[0] <= 0x30)
387 script = ROM16(entry[6]);
388 else
389 if (table[0] == 0x40)
390 script = ROM16(entry[5]);
391 }
392
393 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
394 }
395
396 static void
dp_link_train_fini(struct drm_device * dev,struct dp_state * dp)397 dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
398 {
399 u16 script = 0x0000;
400 u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
401 if (table) {
402 if (table[0] >= 0x20 && table[0] <= 0x30)
403 script = ROM16(entry[8]);
404 else
405 if (table[0] == 0x40)
406 script = ROM16(entry[7]);
407 }
408
409 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
410 }
411
412 bool
nouveau_dp_link_train(struct drm_encoder * encoder,u32 datarate,struct dp_train_func * func)413 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
414 struct dp_train_func *func)
415 {
416 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
417 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
418 struct nouveau_connector *nv_connector =
419 nouveau_encoder_connector_get(nv_encoder);
420 struct drm_device *dev = encoder->dev;
421 struct nouveau_i2c_chan *auxch;
422 const u32 bw_list[] = { 270000, 162000, 0 };
423 const u32 *link_bw = bw_list;
424 struct dp_state dp;
425
426 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
427 if (!auxch)
428 return false;
429
430 dp.func = func;
431 dp.dcb = nv_encoder->dcb;
432 dp.crtc = nv_crtc->index;
433 dp.auxch = auxch->drive;
434 dp.dpcd = nv_encoder->dp.dpcd;
435
436 /* adjust required bandwidth for 8B/10B coding overhead */
437 datarate = (datarate / 8) * 10;
438
439 /* some sinks toggle hotplug in response to some of the actions
440 * we take during link training (DP_SET_POWER is one), we need
441 * to ignore them for the moment to avoid races.
442 */
443 nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);
444
445 /* enable down-spreading, if possible */
446 dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
447
448 /* execute pre-train script from vbios */
449 dp_link_train_init(dev, &dp);
450
451 /* start off at highest link rate supported by encoder and display */
452 while (*link_bw > nv_encoder->dp.link_bw)
453 link_bw++;
454
455 while (link_bw[0]) {
456 /* find minimum required lane count at this link rate */
457 dp.link_nr = nv_encoder->dp.link_nr;
458 while ((dp.link_nr >> 1) * link_bw[0] > datarate)
459 dp.link_nr >>= 1;
460
461 /* drop link rate to minimum with this lane count */
462 while ((link_bw[1] * dp.link_nr) > datarate)
463 link_bw++;
464 dp.link_bw = link_bw[0];
465
466 /* program selected link configuration */
467 dp_set_link_config(dev, &dp);
468
469 /* attempt to train the link at this configuration */
470 memset(dp.stat, 0x00, sizeof(dp.stat));
471 if (!dp_link_train_cr(dev, &dp) &&
472 !dp_link_train_eq(dev, &dp))
473 break;
474
475 /* retry at lower rate */
476 link_bw++;
477 }
478
479 /* finish link training */
480 dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
481
482 /* execute post-train script from vbios */
483 dp_link_train_fini(dev, &dp);
484
485 /* re-enable hotplug detect */
486 nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
487 return true;
488 }
489
490 void
nouveau_dp_dpms(struct drm_encoder * encoder,int mode,u32 datarate,struct dp_train_func * func)491 nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
492 struct dp_train_func *func)
493 {
494 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
495 struct nouveau_i2c_chan *auxch;
496 u8 status;
497
498 auxch = nouveau_i2c_find(encoder->dev, nv_encoder->dcb->i2c_index);
499 if (!auxch)
500 return;
501
502 if (mode == DRM_MODE_DPMS_ON)
503 status = DP_SET_POWER_D0;
504 else
505 status = DP_SET_POWER_D3;
506
507 nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
508
509 if (mode == DRM_MODE_DPMS_ON)
510 nouveau_dp_link_train(encoder, datarate, func);
511 }
512
513 bool
nouveau_dp_detect(struct drm_encoder * encoder)514 nouveau_dp_detect(struct drm_encoder *encoder)
515 {
516 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
517 struct drm_device *dev = encoder->dev;
518 struct nouveau_i2c_chan *auxch;
519 u8 *dpcd = nv_encoder->dp.dpcd;
520 int ret;
521
522 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
523 if (!auxch)
524 return false;
525
526 ret = auxch_tx(dev, auxch->drive, 9, DP_DPCD_REV, dpcd, 8);
527 if (ret)
528 return false;
529
530 nv_encoder->dp.link_bw = 27000 * dpcd[1];
531 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
532
533 NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
534 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
535 NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
536 nv_encoder->dcb->dpconf.link_nr,
537 nv_encoder->dcb->dpconf.link_bw);
538
539 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
540 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
541 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
542 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
543
544 NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
545 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
546
547 return true;
548 }
549
550 int
nouveau_dp_auxch(struct nouveau_i2c_chan * auxch,int cmd,int addr,uint8_t * data,int data_nr)551 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
552 uint8_t *data, int data_nr)
553 {
554 return auxch_tx(auxch->dev, auxch->drive, cmd, addr, data, data_nr);
555 }
556
557 static int
nouveau_dp_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)558 nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
559 {
560 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
561 struct i2c_msg *msg = msgs;
562 int ret, mcnt = num;
563
564 while (mcnt--) {
565 u8 remaining = msg->len;
566 u8 *ptr = msg->buf;
567
568 while (remaining) {
569 u8 cnt = (remaining > 16) ? 16 : remaining;
570 u8 cmd;
571
572 if (msg->flags & I2C_M_RD)
573 cmd = AUX_I2C_READ;
574 else
575 cmd = AUX_I2C_WRITE;
576
577 if (mcnt || remaining > 16)
578 cmd |= AUX_I2C_MOT;
579
580 ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
581 if (ret < 0)
582 return ret;
583
584 ptr += cnt;
585 remaining -= cnt;
586 }
587
588 msg++;
589 }
590
591 return num;
592 }
593
594 static u32
nouveau_dp_i2c_func(struct i2c_adapter * adap)595 nouveau_dp_i2c_func(struct i2c_adapter *adap)
596 {
597 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
598 }
599
600 const struct i2c_algorithm nouveau_dp_i2c_algo = {
601 .master_xfer = nouveau_dp_i2c_xfer,
602 .functionality = nouveau_dp_i2c_func
603 };
604