1 /* 2 * PKUnity Operating System Timer (OST) Registers 3 */ 4 /* 5 * Match Reg 0 OST_OSMR0 6 */ 7 #define OST_OSMR0 (PKUNITY_OST_BASE + 0x0000) 8 /* 9 * Match Reg 1 OST_OSMR1 10 */ 11 #define OST_OSMR1 (PKUNITY_OST_BASE + 0x0004) 12 /* 13 * Match Reg 2 OST_OSMR2 14 */ 15 #define OST_OSMR2 (PKUNITY_OST_BASE + 0x0008) 16 /* 17 * Match Reg 3 OST_OSMR3 18 */ 19 #define OST_OSMR3 (PKUNITY_OST_BASE + 0x000C) 20 /* 21 * Counter Reg OST_OSCR 22 */ 23 #define OST_OSCR (PKUNITY_OST_BASE + 0x0010) 24 /* 25 * Status Reg OST_OSSR 26 */ 27 #define OST_OSSR (PKUNITY_OST_BASE + 0x0014) 28 /* 29 * Watchdog Enable Reg OST_OWER 30 */ 31 #define OST_OWER (PKUNITY_OST_BASE + 0x0018) 32 /* 33 * Interrupt Enable Reg OST_OIER 34 */ 35 #define OST_OIER (PKUNITY_OST_BASE + 0x001C) 36 /* 37 * PWM Pulse Width Control Reg OST_PWMPWCR 38 */ 39 #define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080) 40 /* 41 * PWM Duty Cycle Control Reg OST_PWMDCCR 42 */ 43 #define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084) 44 /* 45 * PWM Period Control Reg OST_PWMPCR 46 */ 47 #define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088) 48 49 /* 50 * Match detected 0 OST_OSSR_M0 51 */ 52 #define OST_OSSR_M0 FIELD(1, 1, 0) 53 /* 54 * Match detected 1 OST_OSSR_M1 55 */ 56 #define OST_OSSR_M1 FIELD(1, 1, 1) 57 /* 58 * Match detected 2 OST_OSSR_M2 59 */ 60 #define OST_OSSR_M2 FIELD(1, 1, 2) 61 /* 62 * Match detected 3 OST_OSSR_M3 63 */ 64 #define OST_OSSR_M3 FIELD(1, 1, 3) 65 66 /* 67 * Interrupt enable 0 OST_OIER_E0 68 */ 69 #define OST_OIER_E0 FIELD(1, 1, 0) 70 /* 71 * Interrupt enable 1 OST_OIER_E1 72 */ 73 #define OST_OIER_E1 FIELD(1, 1, 1) 74 /* 75 * Interrupt enable 2 OST_OIER_E2 76 */ 77 #define OST_OIER_E2 FIELD(1, 1, 2) 78 /* 79 * Interrupt enable 3 OST_OIER_E3 80 */ 81 #define OST_OIER_E3 FIELD(1, 1, 3) 82 83 /* 84 * Watchdog Match Enable OST_OWER_WME 85 */ 86 #define OST_OWER_WME FIELD(1, 1, 0) 87 88 /* 89 * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE 90 */ 91 #define OST_PWMDCCR_FDCYCLE FIELD(1, 1, 10) 92 93