1/* atomic.S: Move this stuff here for better ICACHE hit rates. 2 * 3 * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu) 4 */ 5 6#include <asm/ptrace.h> 7#include <asm/psr.h> 8 9 .text 10 .align 4 11 12 .globl __atomic_begin 13__atomic_begin: 14 15#ifndef CONFIG_SMP 16 .globl ___xchg32_sun4c 17___xchg32_sun4c: 18 rd %psr, %g3 19 andcc %g3, PSR_PIL, %g0 20 bne 1f 21 nop 22 wr %g3, PSR_PIL, %psr 23 nop; nop; nop 241: 25 andcc %g3, PSR_PIL, %g0 26 ld [%g1], %g7 27 bne 1f 28 st %g2, [%g1] 29 wr %g3, 0x0, %psr 30 nop; nop; nop 311: 32 mov %g7, %g2 33 jmpl %o7 + 8, %g0 34 mov %g4, %o7 35 36 .globl ___xchg32_sun4md 37___xchg32_sun4md: 38 swap [%g1], %g2 39 jmpl %o7 + 8, %g0 40 mov %g4, %o7 41#endif 42 43 .globl __atomic_end 44__atomic_end: 45