1 /*
2 * Setup code for SH7720, SH7721.
3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
8 *
9 * Copyright (C) 2006 Paul Mundt
10 * Copyright (C) 2006 Jamie Lenehan
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
19 #include <linux/io.h>
20 #include <linux/serial_sci.h>
21 #include <linux/sh_timer.h>
22 #include <asm/rtc.h>
23 #include <cpu/serial.h>
24
25 static struct resource rtc_resources[] = {
26 [0] = {
27 .start = 0xa413fec0,
28 .end = 0xa413fec0 + 0x28 - 1,
29 .flags = IORESOURCE_IO,
30 },
31 [1] = {
32 /* Shared Period/Carry/Alarm IRQ */
33 .start = 20,
34 .flags = IORESOURCE_IRQ,
35 },
36 };
37
38 static struct sh_rtc_platform_info rtc_info = {
39 .capabilities = RTC_CAP_4_DIGIT_YEAR,
40 };
41
42 static struct platform_device rtc_device = {
43 .name = "sh-rtc",
44 .id = -1,
45 .num_resources = ARRAY_SIZE(rtc_resources),
46 .resource = rtc_resources,
47 .dev = {
48 .platform_data = &rtc_info,
49 },
50 };
51
52 static struct plat_sci_port scif0_platform_data = {
53 .mapbase = 0xa4430000,
54 .flags = UPF_BOOT_AUTOCONF,
55 .scscr = SCSCR_RE | SCSCR_TE,
56 .scbrr_algo_id = SCBRR_ALGO_4,
57 .type = PORT_SCIF,
58 .irqs = { 80, 80, 80, 80 },
59 .ops = &sh7720_sci_port_ops,
60 .regtype = SCIx_SH7705_SCIF_REGTYPE,
61 };
62
63 static struct platform_device scif0_device = {
64 .name = "sh-sci",
65 .id = 0,
66 .dev = {
67 .platform_data = &scif0_platform_data,
68 },
69 };
70
71 static struct plat_sci_port scif1_platform_data = {
72 .mapbase = 0xa4438000,
73 .flags = UPF_BOOT_AUTOCONF,
74 .scscr = SCSCR_RE | SCSCR_TE,
75 .scbrr_algo_id = SCBRR_ALGO_4,
76 .type = PORT_SCIF,
77 .irqs = { 81, 81, 81, 81 },
78 .ops = &sh7720_sci_port_ops,
79 .regtype = SCIx_SH7705_SCIF_REGTYPE,
80 };
81
82 static struct platform_device scif1_device = {
83 .name = "sh-sci",
84 .id = 1,
85 .dev = {
86 .platform_data = &scif1_platform_data,
87 },
88 };
89
90 static struct resource usb_ohci_resources[] = {
91 [0] = {
92 .start = 0xA4428000,
93 .end = 0xA44280FF,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = 67,
98 .end = 67,
99 .flags = IORESOURCE_IRQ,
100 },
101 };
102
103 static u64 usb_ohci_dma_mask = 0xffffffffUL;
104 static struct platform_device usb_ohci_device = {
105 .name = "sh_ohci",
106 .id = -1,
107 .dev = {
108 .dma_mask = &usb_ohci_dma_mask,
109 .coherent_dma_mask = 0xffffffff,
110 },
111 .num_resources = ARRAY_SIZE(usb_ohci_resources),
112 .resource = usb_ohci_resources,
113 };
114
115 static struct resource usbf_resources[] = {
116 [0] = {
117 .name = "sh_udc",
118 .start = 0xA4420000,
119 .end = 0xA44200FF,
120 .flags = IORESOURCE_MEM,
121 },
122 [1] = {
123 .name = "sh_udc",
124 .start = 65,
125 .end = 65,
126 .flags = IORESOURCE_IRQ,
127 },
128 };
129
130 static struct platform_device usbf_device = {
131 .name = "sh_udc",
132 .id = -1,
133 .dev = {
134 .dma_mask = NULL,
135 .coherent_dma_mask = 0xffffffff,
136 },
137 .num_resources = ARRAY_SIZE(usbf_resources),
138 .resource = usbf_resources,
139 };
140
141 static struct sh_timer_config cmt0_platform_data = {
142 .channel_offset = 0x10,
143 .timer_bit = 0,
144 .clockevent_rating = 125,
145 .clocksource_rating = 125,
146 };
147
148 static struct resource cmt0_resources[] = {
149 [0] = {
150 .start = 0x044a0010,
151 .end = 0x044a001b,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = 104,
156 .flags = IORESOURCE_IRQ,
157 },
158 };
159
160 static struct platform_device cmt0_device = {
161 .name = "sh_cmt",
162 .id = 0,
163 .dev = {
164 .platform_data = &cmt0_platform_data,
165 },
166 .resource = cmt0_resources,
167 .num_resources = ARRAY_SIZE(cmt0_resources),
168 };
169
170 static struct sh_timer_config cmt1_platform_data = {
171 .channel_offset = 0x20,
172 .timer_bit = 1,
173 };
174
175 static struct resource cmt1_resources[] = {
176 [0] = {
177 .start = 0x044a0020,
178 .end = 0x044a002b,
179 .flags = IORESOURCE_MEM,
180 },
181 [1] = {
182 .start = 104,
183 .flags = IORESOURCE_IRQ,
184 },
185 };
186
187 static struct platform_device cmt1_device = {
188 .name = "sh_cmt",
189 .id = 1,
190 .dev = {
191 .platform_data = &cmt1_platform_data,
192 },
193 .resource = cmt1_resources,
194 .num_resources = ARRAY_SIZE(cmt1_resources),
195 };
196
197 static struct sh_timer_config cmt2_platform_data = {
198 .channel_offset = 0x30,
199 .timer_bit = 2,
200 };
201
202 static struct resource cmt2_resources[] = {
203 [0] = {
204 .start = 0x044a0030,
205 .end = 0x044a003b,
206 .flags = IORESOURCE_MEM,
207 },
208 [1] = {
209 .start = 104,
210 .flags = IORESOURCE_IRQ,
211 },
212 };
213
214 static struct platform_device cmt2_device = {
215 .name = "sh_cmt",
216 .id = 2,
217 .dev = {
218 .platform_data = &cmt2_platform_data,
219 },
220 .resource = cmt2_resources,
221 .num_resources = ARRAY_SIZE(cmt2_resources),
222 };
223
224 static struct sh_timer_config cmt3_platform_data = {
225 .channel_offset = 0x40,
226 .timer_bit = 3,
227 };
228
229 static struct resource cmt3_resources[] = {
230 [0] = {
231 .start = 0x044a0040,
232 .end = 0x044a004b,
233 .flags = IORESOURCE_MEM,
234 },
235 [1] = {
236 .start = 104,
237 .flags = IORESOURCE_IRQ,
238 },
239 };
240
241 static struct platform_device cmt3_device = {
242 .name = "sh_cmt",
243 .id = 3,
244 .dev = {
245 .platform_data = &cmt3_platform_data,
246 },
247 .resource = cmt3_resources,
248 .num_resources = ARRAY_SIZE(cmt3_resources),
249 };
250
251 static struct sh_timer_config cmt4_platform_data = {
252 .channel_offset = 0x50,
253 .timer_bit = 4,
254 };
255
256 static struct resource cmt4_resources[] = {
257 [0] = {
258 .start = 0x044a0050,
259 .end = 0x044a005b,
260 .flags = IORESOURCE_MEM,
261 },
262 [1] = {
263 .start = 104,
264 .flags = IORESOURCE_IRQ,
265 },
266 };
267
268 static struct platform_device cmt4_device = {
269 .name = "sh_cmt",
270 .id = 4,
271 .dev = {
272 .platform_data = &cmt4_platform_data,
273 },
274 .resource = cmt4_resources,
275 .num_resources = ARRAY_SIZE(cmt4_resources),
276 };
277
278 static struct sh_timer_config tmu0_platform_data = {
279 .channel_offset = 0x02,
280 .timer_bit = 0,
281 .clockevent_rating = 200,
282 };
283
284 static struct resource tmu0_resources[] = {
285 [0] = {
286 .start = 0xa412fe94,
287 .end = 0xa412fe9f,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = 16,
292 .flags = IORESOURCE_IRQ,
293 },
294 };
295
296 static struct platform_device tmu0_device = {
297 .name = "sh_tmu",
298 .id = 0,
299 .dev = {
300 .platform_data = &tmu0_platform_data,
301 },
302 .resource = tmu0_resources,
303 .num_resources = ARRAY_SIZE(tmu0_resources),
304 };
305
306 static struct sh_timer_config tmu1_platform_data = {
307 .channel_offset = 0xe,
308 .timer_bit = 1,
309 .clocksource_rating = 200,
310 };
311
312 static struct resource tmu1_resources[] = {
313 [0] = {
314 .start = 0xa412fea0,
315 .end = 0xa412feab,
316 .flags = IORESOURCE_MEM,
317 },
318 [1] = {
319 .start = 17,
320 .flags = IORESOURCE_IRQ,
321 },
322 };
323
324 static struct platform_device tmu1_device = {
325 .name = "sh_tmu",
326 .id = 1,
327 .dev = {
328 .platform_data = &tmu1_platform_data,
329 },
330 .resource = tmu1_resources,
331 .num_resources = ARRAY_SIZE(tmu1_resources),
332 };
333
334 static struct sh_timer_config tmu2_platform_data = {
335 .channel_offset = 0x1a,
336 .timer_bit = 2,
337 };
338
339 static struct resource tmu2_resources[] = {
340 [0] = {
341 .start = 0xa412feac,
342 .end = 0xa412feb5,
343 .flags = IORESOURCE_MEM,
344 },
345 [1] = {
346 .start = 18,
347 .flags = IORESOURCE_IRQ,
348 },
349 };
350
351 static struct platform_device tmu2_device = {
352 .name = "sh_tmu",
353 .id = 2,
354 .dev = {
355 .platform_data = &tmu2_platform_data,
356 },
357 .resource = tmu2_resources,
358 .num_resources = ARRAY_SIZE(tmu2_resources),
359 };
360
361 static struct platform_device *sh7720_devices[] __initdata = {
362 &scif0_device,
363 &scif1_device,
364 &cmt0_device,
365 &cmt1_device,
366 &cmt2_device,
367 &cmt3_device,
368 &cmt4_device,
369 &tmu0_device,
370 &tmu1_device,
371 &tmu2_device,
372 &rtc_device,
373 &usb_ohci_device,
374 &usbf_device,
375 };
376
sh7720_devices_setup(void)377 static int __init sh7720_devices_setup(void)
378 {
379 return platform_add_devices(sh7720_devices,
380 ARRAY_SIZE(sh7720_devices));
381 }
382 arch_initcall(sh7720_devices_setup);
383
384 static struct platform_device *sh7720_early_devices[] __initdata = {
385 &scif0_device,
386 &scif1_device,
387 &cmt0_device,
388 &cmt1_device,
389 &cmt2_device,
390 &cmt3_device,
391 &cmt4_device,
392 &tmu0_device,
393 &tmu1_device,
394 &tmu2_device,
395 };
396
plat_early_device_setup(void)397 void __init plat_early_device_setup(void)
398 {
399 early_platform_add_devices(sh7720_early_devices,
400 ARRAY_SIZE(sh7720_early_devices));
401 }
402
403 enum {
404 UNUSED = 0,
405
406 /* interrupt sources */
407 TMU0, TMU1, TMU2, RTC,
408 WDT, REF_RCMI, SIM,
409 IRQ0, IRQ1, IRQ2, IRQ3,
410 USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
411 DMAC1, LCDC, SSL,
412 ADC, DMAC2, USBFI, CMT,
413 SCIF0, SCIF1,
414 PINT07, PINT815, TPU, IIC,
415 SIOF0, SIOF1, MMC, PCC,
416 USBHI, AFEIF,
417 H_UDI,
418 };
419
420 static struct intc_vect vectors[] __initdata = {
421 /* IRQ0->5 are handled in setup-sh3.c */
422 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
423 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
424 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
425 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
426 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
427 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
428 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
429 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
430 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
431 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
432 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
433 INTC_VECT(SSL, 0x980),
434 #endif
435 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
436 INTC_VECT(USBHI, 0xa60),
437 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
438 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
439 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
440 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
441 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
442 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
443 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
444 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
445 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
446 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
447 INTC_VECT(AFEIF, 0xfe0),
448 };
449
450 static struct intc_prio_reg prio_registers[] __initdata = {
451 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
452 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
453 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
454 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
455 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
456 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
457 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
458 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
459 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
460 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
461 };
462
463 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
464 NULL, prio_registers, NULL);
465
plat_irq_setup(void)466 void __init plat_irq_setup(void)
467 {
468 register_intc_controller(&intc_desc);
469 plat_irq_setup_sh3();
470 }
471