1 /*
2 * SH7203 and SH7263 Setup
3 *
4 * Copyright (C) 2007 - 2009 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/sh_timer.h>
15 #include <linux/io.h>
16
17 enum {
18 UNUSED = 0,
19
20 /* interrupt sources */
21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
23 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
24 USB, LCDC, CMT0, CMT1, BSC, WDT,
25
26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
27 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
28
29 ADC_ADI,
30
31 IIC30, IIC31, IIC32, IIC33,
32 SCIF0, SCIF1, SCIF2, SCIF3,
33
34 SSU0, SSU1,
35
36 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
37
38 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
39 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
40 SRC, IEBI,
41
42 /* interrupt groups */
43 PINT,
44 };
45
46 static struct intc_vect vectors[] __initdata = {
47 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
48 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
49 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
50 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
51 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
52 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
53 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
54 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
55 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
56 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
57 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
58 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
59 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
60 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
61 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
62 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
63 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
64 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
65 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
66 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
67 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
68 INTC_IRQ(MTU0_VEF, 150),
69 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
70 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
71 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
72 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
73 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
74 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
75 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
76 INTC_IRQ(MTU2_TCI3V, 165),
77 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
78 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
79 INTC_IRQ(MTU2_TCI4V, 170),
80 INTC_IRQ(ADC_ADI, 171),
81 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
82 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
83 INTC_IRQ(IIC30, 176),
84 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
85 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
86 INTC_IRQ(IIC31, 181),
87 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
88 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
89 INTC_IRQ(IIC32, 186),
90 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
91 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
92 INTC_IRQ(IIC33, 191),
93 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
94 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
95 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
96 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
97 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
98 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
99 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
100 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
101 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
102 INTC_IRQ(SSU0, 210),
103 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
104 INTC_IRQ(SSU1, 213),
105 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
106 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
107 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
108 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
109 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
110 INTC_IRQ(RTC, 233),
111 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
112 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
113 INTC_IRQ(RCAN0, 238),
114 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
115 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
116 INTC_IRQ(RCAN1, 243),
117
118 /* SH7263-specific trash */
119 #ifdef CONFIG_CPU_SUBTYPE_SH7263
120 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
121 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
122 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
123
124 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
125 INTC_IRQ(SDHI, 230),
126
127 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
128 INTC_IRQ(SRC, 246),
129
130 INTC_IRQ(IEBI, 247),
131 #endif
132 };
133
134 static struct intc_group groups[] __initdata = {
135 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
136 PINT4, PINT5, PINT6, PINT7),
137 };
138
139 static struct intc_prio_reg prio_registers[] __initdata = {
140 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
141 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
142 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
143 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
144 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
145 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
146 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
147 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
148 MTU2_VU } },
149 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
150 MTU2_TCI4V } },
151 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
152 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
153 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
154 #ifdef CONFIG_CPU_SUBTYPE_SH7203
155 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
156 SSI3_SSII, 0 } },
157 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
158 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
159 #else
160 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
161 SSI3_SSII, ROMDEC } },
162 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
163 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
164 #endif
165 };
166
167 static struct intc_mask_reg mask_registers[] __initdata = {
168 { 0xfffe0808, 0, 16, /* PINTER */
169 { 0, 0, 0, 0, 0, 0, 0, 0,
170 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
171 };
172
173 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
174 mask_registers, prio_registers, NULL);
175
176 static struct plat_sci_port scif0_platform_data = {
177 .mapbase = 0xfffe8000,
178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
180 SCSCR_REIE,
181 .scbrr_algo_id = SCBRR_ALGO_2,
182 .type = PORT_SCIF,
183 .irqs = { 192, 192, 192, 192 },
184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
185 };
186
187 static struct platform_device scif0_device = {
188 .name = "sh-sci",
189 .id = 0,
190 .dev = {
191 .platform_data = &scif0_platform_data,
192 },
193 };
194
195 static struct plat_sci_port scif1_platform_data = {
196 .mapbase = 0xfffe8800,
197 .flags = UPF_BOOT_AUTOCONF,
198 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
199 SCSCR_REIE,
200 .scbrr_algo_id = SCBRR_ALGO_2,
201 .type = PORT_SCIF,
202 .irqs = { 196, 196, 196, 196 },
203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
204 };
205
206 static struct platform_device scif1_device = {
207 .name = "sh-sci",
208 .id = 1,
209 .dev = {
210 .platform_data = &scif1_platform_data,
211 },
212 };
213
214 static struct plat_sci_port scif2_platform_data = {
215 .mapbase = 0xfffe9000,
216 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
218 SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF,
221 .irqs = { 200, 200, 200, 200 },
222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
223 };
224
225 static struct platform_device scif2_device = {
226 .name = "sh-sci",
227 .id = 2,
228 .dev = {
229 .platform_data = &scif2_platform_data,
230 },
231 };
232
233 static struct plat_sci_port scif3_platform_data = {
234 .mapbase = 0xfffe9800,
235 .flags = UPF_BOOT_AUTOCONF,
236 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
237 SCSCR_REIE,
238 .scbrr_algo_id = SCBRR_ALGO_2,
239 .type = PORT_SCIF,
240 .irqs = { 204, 204, 204, 204 },
241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
242 };
243
244 static struct platform_device scif3_device = {
245 .name = "sh-sci",
246 .id = 3,
247 .dev = {
248 .platform_data = &scif3_platform_data,
249 },
250 };
251
252 static struct sh_timer_config cmt0_platform_data = {
253 .channel_offset = 0x02,
254 .timer_bit = 0,
255 .clockevent_rating = 125,
256 .clocksource_rating = 0, /* disabled due to code generation issues */
257 };
258
259 static struct resource cmt0_resources[] = {
260 [0] = {
261 .start = 0xfffec002,
262 .end = 0xfffec007,
263 .flags = IORESOURCE_MEM,
264 },
265 [1] = {
266 .start = 142,
267 .flags = IORESOURCE_IRQ,
268 },
269 };
270
271 static struct platform_device cmt0_device = {
272 .name = "sh_cmt",
273 .id = 0,
274 .dev = {
275 .platform_data = &cmt0_platform_data,
276 },
277 .resource = cmt0_resources,
278 .num_resources = ARRAY_SIZE(cmt0_resources),
279 };
280
281 static struct sh_timer_config cmt1_platform_data = {
282 .channel_offset = 0x08,
283 .timer_bit = 1,
284 .clockevent_rating = 125,
285 .clocksource_rating = 0, /* disabled due to code generation issues */
286 };
287
288 static struct resource cmt1_resources[] = {
289 [0] = {
290 .start = 0xfffec008,
291 .end = 0xfffec00d,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = 143,
296 .flags = IORESOURCE_IRQ,
297 },
298 };
299
300 static struct platform_device cmt1_device = {
301 .name = "sh_cmt",
302 .id = 1,
303 .dev = {
304 .platform_data = &cmt1_platform_data,
305 },
306 .resource = cmt1_resources,
307 .num_resources = ARRAY_SIZE(cmt1_resources),
308 };
309
310 static struct sh_timer_config mtu2_0_platform_data = {
311 .channel_offset = -0x80,
312 .timer_bit = 0,
313 .clockevent_rating = 200,
314 };
315
316 static struct resource mtu2_0_resources[] = {
317 [0] = {
318 .start = 0xfffe4300,
319 .end = 0xfffe4326,
320 .flags = IORESOURCE_MEM,
321 },
322 [1] = {
323 .start = 146,
324 .flags = IORESOURCE_IRQ,
325 },
326 };
327
328 static struct platform_device mtu2_0_device = {
329 .name = "sh_mtu2",
330 .id = 0,
331 .dev = {
332 .platform_data = &mtu2_0_platform_data,
333 },
334 .resource = mtu2_0_resources,
335 .num_resources = ARRAY_SIZE(mtu2_0_resources),
336 };
337
338 static struct sh_timer_config mtu2_1_platform_data = {
339 .channel_offset = -0x100,
340 .timer_bit = 1,
341 .clockevent_rating = 200,
342 };
343
344 static struct resource mtu2_1_resources[] = {
345 [0] = {
346 .start = 0xfffe4380,
347 .end = 0xfffe4390,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = 153,
352 .flags = IORESOURCE_IRQ,
353 },
354 };
355
356 static struct platform_device mtu2_1_device = {
357 .name = "sh_mtu2",
358 .id = 1,
359 .dev = {
360 .platform_data = &mtu2_1_platform_data,
361 },
362 .resource = mtu2_1_resources,
363 .num_resources = ARRAY_SIZE(mtu2_1_resources),
364 };
365
366 static struct resource rtc_resources[] = {
367 [0] = {
368 .start = 0xffff2000,
369 .end = 0xffff2000 + 0x58 - 1,
370 .flags = IORESOURCE_IO,
371 },
372 [1] = {
373 /* Shared Period/Carry/Alarm IRQ */
374 .start = 231,
375 .flags = IORESOURCE_IRQ,
376 },
377 };
378
379 static struct platform_device rtc_device = {
380 .name = "sh-rtc",
381 .id = -1,
382 .num_resources = ARRAY_SIZE(rtc_resources),
383 .resource = rtc_resources,
384 };
385
386 static struct platform_device *sh7203_devices[] __initdata = {
387 &scif0_device,
388 &scif1_device,
389 &scif2_device,
390 &scif3_device,
391 &cmt0_device,
392 &cmt1_device,
393 &mtu2_0_device,
394 &mtu2_1_device,
395 &rtc_device,
396 };
397
sh7203_devices_setup(void)398 static int __init sh7203_devices_setup(void)
399 {
400 return platform_add_devices(sh7203_devices,
401 ARRAY_SIZE(sh7203_devices));
402 }
403 arch_initcall(sh7203_devices_setup);
404
plat_irq_setup(void)405 void __init plat_irq_setup(void)
406 {
407 register_intc_controller(&intc_desc);
408 }
409
410 static struct platform_device *sh7203_early_devices[] __initdata = {
411 &scif0_device,
412 &scif1_device,
413 &scif2_device,
414 &scif3_device,
415 &cmt0_device,
416 &cmt1_device,
417 &mtu2_0_device,
418 &mtu2_1_device,
419 };
420
421 #define STBCR3 0xfffe0408
422 #define STBCR4 0xfffe040c
423
plat_early_device_setup(void)424 void __init plat_early_device_setup(void)
425 {
426 /* enable CMT clock */
427 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
428
429 /* enable MTU2 clock */
430 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
431
432 early_platform_add_devices(sh7203_early_devices,
433 ARRAY_SIZE(sh7203_early_devices));
434 }
435