1 /*
2 * P1022DS board specific routines
3 *
4 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
5 * Dave Liu <daveliu@freescale.com>
6 * Timur Tabi <timur@freescale.com>
7 *
8 * Copyright 2010 Freescale Semiconductor, Inc.
9 *
10 * This file is taken from the Freescale P1022DS BSP, with modifications:
11 * 2) No AMP support
12 * 3) No PCI endpoint support
13 *
14 * This file is licensed under the terms of the GNU General Public License
15 * version 2. This program is licensed "as is" without any warranty of any
16 * kind, whether express or implied.
17 */
18
19 #include <linux/pci.h>
20 #include <linux/of_platform.h>
21 #include <linux/memblock.h>
22 #include <asm/div64.h>
23 #include <asm/mpic.h>
24 #include <asm/swiotlb.h>
25
26 #include <sysdev/fsl_soc.h>
27 #include <sysdev/fsl_pci.h>
28 #include <asm/udbg.h>
29 #include <asm/fsl_guts.h>
30 #include <asm/fsl_lbc.h>
31 #include "smp.h"
32
33 #include "mpc85xx.h"
34
35 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
36
37 #define PMUXCR_ELBCDIU_MASK 0xc0000000
38 #define PMUXCR_ELBCDIU_NOR16 0x80000000
39 #define PMUXCR_ELBCDIU_DIU 0x40000000
40
41 /*
42 * Board-specific initialization of the DIU. This code should probably be
43 * executed when the DIU is opened, rather than in arch code, but the DIU
44 * driver does not have a mechanism for this (yet).
45 *
46 * This is especially problematic on the P1022DS because the local bus (eLBC)
47 * and the DIU video signals share the same pins, which means that enabling the
48 * DIU will disable access to NOR flash.
49 */
50
51 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
52 #define CLKDVDR_PXCKEN 0x80000000
53 #define CLKDVDR_PXCKINV 0x10000000
54 #define CLKDVDR_PXCKDLY 0x06000000
55 #define CLKDVDR_PXCLK_MASK 0x00FF0000
56
57 /* Some ngPIXIS register definitions */
58 #define PX_CTL 3
59 #define PX_BRDCFG0 8
60 #define PX_BRDCFG1 9
61
62 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
63 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
64 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
65 #define PX_BRDCFG0_ELBC_DIU 0x02
66
67 #define PX_BRDCFG1_DVIEN 0x80
68 #define PX_BRDCFG1_DFPEN 0x40
69 #define PX_BRDCFG1_BACKLIGHT 0x20
70 #define PX_BRDCFG1_DDCEN 0x10
71
72 #define PX_CTL_ALTACC 0x80
73
74 /*
75 * DIU Area Descriptor
76 *
77 * Note that we need to byte-swap the value before it's written to the AD
78 * register. So even though the registers don't look like they're in the same
79 * bit positions as they are on the MPC8610, the same value is written to the
80 * AD register on the MPC8610 and on the P1022.
81 */
82 #define AD_BYTE_F 0x10000000
83 #define AD_ALPHA_C_MASK 0x0E000000
84 #define AD_ALPHA_C_SHIFT 25
85 #define AD_BLUE_C_MASK 0x01800000
86 #define AD_BLUE_C_SHIFT 23
87 #define AD_GREEN_C_MASK 0x00600000
88 #define AD_GREEN_C_SHIFT 21
89 #define AD_RED_C_MASK 0x00180000
90 #define AD_RED_C_SHIFT 19
91 #define AD_PALETTE 0x00040000
92 #define AD_PIXEL_S_MASK 0x00030000
93 #define AD_PIXEL_S_SHIFT 16
94 #define AD_COMP_3_MASK 0x0000F000
95 #define AD_COMP_3_SHIFT 12
96 #define AD_COMP_2_MASK 0x00000F00
97 #define AD_COMP_2_SHIFT 8
98 #define AD_COMP_1_MASK 0x000000F0
99 #define AD_COMP_1_SHIFT 4
100 #define AD_COMP_0_MASK 0x0000000F
101 #define AD_COMP_0_SHIFT 0
102
103 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
104 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
105 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
106 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
107 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
108 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
109
110 /**
111 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
112 *
113 * The Area Descriptor is a 32-bit value that determine which bits in each
114 * pixel are to be used for each color.
115 */
p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,unsigned int bits_per_pixel)116 static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
117 unsigned int bits_per_pixel)
118 {
119 switch (bits_per_pixel) {
120 case 32:
121 /* 0x88883316 */
122 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
123 case 24:
124 /* 0x88082219 */
125 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
126 case 16:
127 /* 0x65053118 */
128 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
129 default:
130 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
131 return 0;
132 }
133 }
134
135 /**
136 * p1022ds_set_gamma_table: update the gamma table, if necessary
137 *
138 * On some boards, the gamma table for some ports may need to be modified.
139 * This is not the case on the P1022DS, so we do nothing.
140 */
p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,char * gamma_table_base)141 static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
142 char *gamma_table_base)
143 {
144 }
145
146 struct fsl_law {
147 u32 lawbar;
148 u32 reserved1;
149 u32 lawar;
150 u32 reserved[5];
151 };
152
153 #define LAWBAR_MASK 0x00F00000
154 #define LAWBAR_SHIFT 12
155
156 #define LAWAR_EN 0x80000000
157 #define LAWAR_TGT_MASK 0x01F00000
158 #define LAW_TRGT_IF_LBC (0x04 << 20)
159
160 #define LAWAR_MASK (LAWAR_EN | LAWAR_TGT_MASK)
161 #define LAWAR_MATCH (LAWAR_EN | LAW_TRGT_IF_LBC)
162
163 #define BR_BA 0xFFFF8000
164
165 /*
166 * Map a BRx value to a physical address
167 *
168 * The localbus BRx registers only store the lower 32 bits of the address. To
169 * obtain the upper four bits, we need to scan the LAW table. The entry which
170 * maps to the localbus will contain the upper four bits.
171 */
lbc_br_to_phys(const void * ecm,unsigned int count,u32 br)172 static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
173 {
174 #ifndef CONFIG_PHYS_64BIT
175 /*
176 * If we only have 32-bit addressing, then the BRx address *is* the
177 * physical address.
178 */
179 return br & BR_BA;
180 #else
181 const struct fsl_law *law = ecm + 0xc08;
182 unsigned int i;
183
184 for (i = 0; i < count; i++) {
185 u64 lawbar = in_be32(&law[i].lawbar);
186 u32 lawar = in_be32(&law[i].lawar);
187
188 if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
189 /* Extract the upper four bits */
190 return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
191 }
192
193 return 0;
194 #endif
195 }
196
197 /**
198 * p1022ds_set_monitor_port: switch the output to a different monitor port
199 */
p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)200 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
201 {
202 struct device_node *guts_node;
203 struct device_node *lbc_node = NULL;
204 struct device_node *law_node = NULL;
205 struct ccsr_guts __iomem *guts;
206 struct fsl_lbc_regs *lbc = NULL;
207 void *ecm = NULL;
208 u8 __iomem *lbc_lcs0_ba = NULL;
209 u8 __iomem *lbc_lcs1_ba = NULL;
210 phys_addr_t cs0_addr, cs1_addr;
211 u32 br0, or0, br1, or1;
212 const __be32 *iprop;
213 unsigned int num_laws;
214 u8 b;
215
216 /* Map the global utilities registers. */
217 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
218 if (!guts_node) {
219 pr_err("p1022ds: missing global utilties device node\n");
220 return;
221 }
222
223 guts = of_iomap(guts_node, 0);
224 if (!guts) {
225 pr_err("p1022ds: could not map global utilties device\n");
226 goto exit;
227 }
228
229 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
230 if (!lbc_node) {
231 pr_err("p1022ds: missing localbus node\n");
232 goto exit;
233 }
234
235 lbc = of_iomap(lbc_node, 0);
236 if (!lbc) {
237 pr_err("p1022ds: could not map localbus node\n");
238 goto exit;
239 }
240
241 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
242 if (!law_node) {
243 pr_err("p1022ds: missing local access window node\n");
244 goto exit;
245 }
246
247 ecm = of_iomap(law_node, 0);
248 if (!ecm) {
249 pr_err("p1022ds: could not map local access window node\n");
250 goto exit;
251 }
252
253 iprop = of_get_property(law_node, "fsl,num-laws", 0);
254 if (!iprop) {
255 pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
256 goto exit;
257 }
258 num_laws = be32_to_cpup(iprop);
259
260 /*
261 * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
262 * otherwise writes to these addresses won't actually appear on the
263 * local bus, and so the PIXIS won't see them.
264 *
265 * In FCM mode, writes go to the NAND controller, which does not pass
266 * them to the localbus directly. So we force BR0 and BR1 into GPCM
267 * mode, since we don't care about what's behind the localbus any
268 * more.
269 */
270 br0 = in_be32(&lbc->bank[0].br);
271 br1 = in_be32(&lbc->bank[1].br);
272 or0 = in_be32(&lbc->bank[0].or);
273 or1 = in_be32(&lbc->bank[1].or);
274
275 /* Make sure CS0 and CS1 are programmed */
276 if (!(br0 & BR_V) || !(br1 & BR_V)) {
277 pr_err("p1022ds: CS0 and/or CS1 is not programmed\n");
278 goto exit;
279 }
280
281 /*
282 * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
283 * force the values to simple 32KB GPCM windows with the most
284 * conservative timing.
285 */
286 if ((br0 & BR_MSEL) != BR_MS_GPCM) {
287 br0 = (br0 & BR_BA) | BR_V;
288 or0 = 0xFFFF8000 | 0xFF7;
289 out_be32(&lbc->bank[0].br, br0);
290 out_be32(&lbc->bank[0].or, or0);
291 }
292 if ((br1 & BR_MSEL) != BR_MS_GPCM) {
293 br1 = (br1 & BR_BA) | BR_V;
294 or1 = 0xFFFF8000 | 0xFF7;
295 out_be32(&lbc->bank[1].br, br1);
296 out_be32(&lbc->bank[1].or, or1);
297 }
298
299 cs0_addr = lbc_br_to_phys(ecm, num_laws, br0);
300 if (!cs0_addr) {
301 pr_err("p1022ds: could not determine physical address for CS0"
302 " (BR0=%08x)\n", br0);
303 goto exit;
304 }
305 cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
306 if (!cs0_addr) {
307 pr_err("p1022ds: could not determine physical address for CS1"
308 " (BR1=%08x)\n", br1);
309 goto exit;
310 }
311
312 lbc_lcs0_ba = ioremap(cs0_addr, 1);
313 if (!lbc_lcs0_ba) {
314 pr_err("p1022ds: could not ioremap CS0 address %llx\n",
315 (unsigned long long)cs0_addr);
316 goto exit;
317 }
318 lbc_lcs1_ba = ioremap(cs1_addr, 1);
319 if (!lbc_lcs1_ba) {
320 pr_err("p1022ds: could not ioremap CS1 address %llx\n",
321 (unsigned long long)cs1_addr);
322 goto exit;
323 }
324
325 /* Make sure we're in indirect mode first. */
326 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
327 PMUXCR_ELBCDIU_DIU) {
328 struct device_node *pixis_node;
329 void __iomem *pixis;
330
331 pixis_node =
332 of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
333 if (!pixis_node) {
334 pr_err("p1022ds: missing pixis node\n");
335 goto exit;
336 }
337
338 pixis = of_iomap(pixis_node, 0);
339 of_node_put(pixis_node);
340 if (!pixis) {
341 pr_err("p1022ds: could not map pixis registers\n");
342 goto exit;
343 }
344
345 /* Enable indirect PIXIS mode. */
346 setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
347 iounmap(pixis);
348
349 /* Switch the board mux to the DIU */
350 out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
351 b = in_8(lbc_lcs1_ba);
352 b |= PX_BRDCFG0_ELBC_DIU;
353 out_8(lbc_lcs1_ba, b);
354
355 /* Set the chip mux to DIU mode. */
356 clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
357 PMUXCR_ELBCDIU_DIU);
358 in_be32(&guts->pmuxcr);
359 }
360
361
362 switch (port) {
363 case FSL_DIU_PORT_DVI:
364 /* Enable the DVI port, disable the DFP and the backlight */
365 out_8(lbc_lcs0_ba, PX_BRDCFG1);
366 b = in_8(lbc_lcs1_ba);
367 b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
368 b |= PX_BRDCFG1_DVIEN;
369 out_8(lbc_lcs1_ba, b);
370 break;
371 case FSL_DIU_PORT_LVDS:
372 /*
373 * LVDS also needs backlight enabled, otherwise the display
374 * will be blank.
375 */
376 /* Enable the DFP port, disable the DVI and the backlight */
377 out_8(lbc_lcs0_ba, PX_BRDCFG1);
378 b = in_8(lbc_lcs1_ba);
379 b &= ~PX_BRDCFG1_DVIEN;
380 b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
381 out_8(lbc_lcs1_ba, b);
382 break;
383 default:
384 pr_err("p1022ds: unsupported monitor port %i\n", port);
385 }
386
387 exit:
388 if (lbc_lcs1_ba)
389 iounmap(lbc_lcs1_ba);
390 if (lbc_lcs0_ba)
391 iounmap(lbc_lcs0_ba);
392 if (lbc)
393 iounmap(lbc);
394 if (ecm)
395 iounmap(ecm);
396 if (guts)
397 iounmap(guts);
398
399 of_node_put(law_node);
400 of_node_put(lbc_node);
401 of_node_put(guts_node);
402 }
403
404 /**
405 * p1022ds_set_pixel_clock: program the DIU's clock
406 *
407 * @pixclock: the wavelength, in picoseconds, of the clock
408 */
p1022ds_set_pixel_clock(unsigned int pixclock)409 void p1022ds_set_pixel_clock(unsigned int pixclock)
410 {
411 struct device_node *guts_np = NULL;
412 struct ccsr_guts __iomem *guts;
413 unsigned long freq;
414 u64 temp;
415 u32 pxclk;
416
417 /* Map the global utilities registers. */
418 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
419 if (!guts_np) {
420 pr_err("p1022ds: missing global utilties device node\n");
421 return;
422 }
423
424 guts = of_iomap(guts_np, 0);
425 of_node_put(guts_np);
426 if (!guts) {
427 pr_err("p1022ds: could not map global utilties device\n");
428 return;
429 }
430
431 /* Convert pixclock from a wavelength to a frequency */
432 temp = 1000000000000ULL;
433 do_div(temp, pixclock);
434 freq = temp;
435
436 /*
437 * 'pxclk' is the ratio of the platform clock to the pixel clock.
438 * This number is programmed into the CLKDVDR register, and the valid
439 * range of values is 2-255.
440 */
441 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
442 pxclk = clamp_t(u32, pxclk, 2, 255);
443
444 /* Disable the pixel clock, and set it to non-inverted and no delay */
445 clrbits32(&guts->clkdvdr,
446 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
447
448 /* Enable the clock and set the pxclk */
449 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
450
451 iounmap(guts);
452 }
453
454 /**
455 * p1022ds_valid_monitor_port: set the monitor port for sysfs
456 */
457 enum fsl_diu_monitor_port
p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)458 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
459 {
460 switch (port) {
461 case FSL_DIU_PORT_DVI:
462 case FSL_DIU_PORT_LVDS:
463 return port;
464 default:
465 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
466 }
467 }
468
469 #endif
470
p1022_ds_pic_init(void)471 void __init p1022_ds_pic_init(void)
472 {
473 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
474 MPIC_SINGLE_DEST_CPU,
475 0, 256, " OpenPIC ");
476 BUG_ON(mpic == NULL);
477 mpic_init(mpic);
478 }
479
480 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
481
482 /*
483 * Disables a node in the device tree.
484 *
485 * This function is called before kmalloc() is available, so the 'new' object
486 * should be allocated in the global area. The easiest way is to do that is
487 * to allocate one static local variable for each call to this function.
488 */
disable_one_node(struct device_node * np,struct property * new)489 static void __init disable_one_node(struct device_node *np, struct property *new)
490 {
491 struct property *old;
492
493 old = of_find_property(np, new->name, NULL);
494 if (old)
495 prom_update_property(np, new, old);
496 else
497 prom_add_property(np, new);
498
499 pr_info("p1022ds: disabling %s node\n", np->full_name);
500 }
501
502 /* TRUE if there is a "video=fslfb" command-line parameter. */
503 static bool fslfb;
504
505 /*
506 * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
507 * true if we find it.
508 *
509 * We need to use early_param() instead of __setup() because the normal
510 * __setup() gets called to late. However, early_param() gets called very
511 * early, before the device tree is unflattened, so all we can do now is set a
512 * global variable. Later on, p1022_ds_setup_arch() will use that variable
513 * to determine if we need to update the device tree.
514 */
early_video_setup(char * options)515 static int __init early_video_setup(char *options)
516 {
517 fslfb = (strncmp(options, "fslfb:", 6) == 0);
518
519 return 0;
520 }
521 early_param("video", early_video_setup);
522
523 #endif
524
525 /*
526 * Setup the architecture
527 */
p1022_ds_setup_arch(void)528 static void __init p1022_ds_setup_arch(void)
529 {
530 #ifdef CONFIG_PCI
531 struct device_node *np;
532 #endif
533 dma_addr_t max = 0xffffffff;
534
535 if (ppc_md.progress)
536 ppc_md.progress("p1022_ds_setup_arch()", 0);
537
538 #ifdef CONFIG_PCI
539 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
540 struct resource rsrc;
541 struct pci_controller *hose;
542
543 of_address_to_resource(np, 0, &rsrc);
544
545 if ((rsrc.start & 0xfffff) == 0x8000)
546 fsl_add_bridge(np, 1);
547 else
548 fsl_add_bridge(np, 0);
549
550 hose = pci_find_hose_for_OF_device(np);
551 max = min(max, hose->dma_window_base_cur +
552 hose->dma_window_size);
553 }
554 #endif
555
556 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
557 diu_ops.get_pixel_format = p1022ds_get_pixel_format;
558 diu_ops.set_gamma_table = p1022ds_set_gamma_table;
559 diu_ops.set_monitor_port = p1022ds_set_monitor_port;
560 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
561 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
562
563 /*
564 * Disable the NOR and NAND flash nodes if there is video=fslfb...
565 * command-line parameter. When the DIU is active, the localbus is
566 * unavailable, so we have to disable these nodes before the MTD
567 * driver loads.
568 */
569 if (fslfb) {
570 struct device_node *np =
571 of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
572
573 if (np) {
574 struct device_node *np2;
575
576 of_node_get(np);
577 np2 = of_find_compatible_node(np, NULL, "cfi-flash");
578 if (np2) {
579 static struct property nor_status = {
580 .name = "status",
581 .value = "disabled",
582 .length = sizeof("disabled"),
583 };
584
585 disable_one_node(np2, &nor_status);
586 of_node_put(np2);
587 }
588
589 of_node_get(np);
590 np2 = of_find_compatible_node(np, NULL,
591 "fsl,elbc-fcm-nand");
592 if (np2) {
593 static struct property nand_status = {
594 .name = "status",
595 .value = "disabled",
596 .length = sizeof("disabled"),
597 };
598
599 disable_one_node(np2, &nand_status);
600 of_node_put(np2);
601 }
602
603 of_node_put(np);
604 }
605
606 }
607
608 #endif
609
610 mpc85xx_smp_init();
611
612 #ifdef CONFIG_SWIOTLB
613 if (memblock_end_of_DRAM() > max) {
614 ppc_swiotlb_enable = 1;
615 set_pci_dma_ops(&swiotlb_dma_ops);
616 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
617 }
618 #endif
619
620 pr_info("Freescale P1022 DS reference board\n");
621 }
622
623 machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
624
625 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
626
627 /*
628 * Called very early, device-tree isn't unflattened
629 */
p1022_ds_probe(void)630 static int __init p1022_ds_probe(void)
631 {
632 unsigned long root = of_get_flat_dt_root();
633
634 return of_flat_dt_is_compatible(root, "fsl,p1022ds");
635 }
636
define_machine(p1022_ds)637 define_machine(p1022_ds) {
638 .name = "P1022 DS",
639 .probe = p1022_ds_probe,
640 .setup_arch = p1022_ds_setup_arch,
641 .init_IRQ = p1022_ds_pic_init,
642 #ifdef CONFIG_PCI
643 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
644 #endif
645 .get_irq = mpic_get_irq,
646 .restart = fsl_rstcr_restart,
647 .calibrate_decr = generic_calibrate_decr,
648 .progress = udbg_progress,
649 };
650