1 /*
2  * Port for PPC64 David Engebretsen, IBM Corp.
3  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
4  *
5  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6  *   Rework, based on alpha PCI code.
7  *
8  *      This program is free software; you can redistribute it and/or
9  *      modify it under the terms of the GNU General Public License
10  *      as published by the Free Software Foundation; either version
11  *      2 of the License, or (at your option) any later version.
12  */
13 
14 #undef DEBUG
15 
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
21 #include <linux/export.h>
22 #include <linux/mm.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
25 #include <linux/irq.h>
26 #include <linux/vmalloc.h>
27 
28 #include <asm/processor.h>
29 #include <asm/io.h>
30 #include <asm/prom.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/byteorder.h>
33 #include <asm/machdep.h>
34 #include <asm/ppc-pci.h>
35 
36 /* pci_io_base -- the base address from which io bars are offsets.
37  * This is the lowest I/O base address (so bar values are always positive),
38  * and it *must* be the start of ISA space if an ISA bus exists because
39  * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
40  * is mapped on the first 64K of IO space
41  */
42 unsigned long pci_io_base = ISA_IO_BASE;
43 EXPORT_SYMBOL(pci_io_base);
44 
pcibios_init(void)45 static int __init pcibios_init(void)
46 {
47 	struct pci_controller *hose, *tmp;
48 
49 	printk(KERN_INFO "PCI: Probing PCI hardware\n");
50 
51 	/* For now, override phys_mem_access_prot. If we need it,g
52 	 * later, we may move that initialization to each ppc_md
53 	 */
54 	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
55 
56 	/* On ppc64, we always enable PCI domains and we keep domain 0
57 	 * backward compatible in /proc for video cards
58 	 */
59 	pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
60 
61 	/* Scan all of the recorded PCI controllers.  */
62 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
63 		pcibios_scan_phb(hose);
64 		pci_bus_add_devices(hose->bus);
65 	}
66 
67 	/* Call common code to handle resource allocation */
68 	pcibios_resource_survey();
69 
70 	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
71 
72 	return 0;
73 }
74 
75 subsys_initcall(pcibios_init);
76 
77 #ifdef CONFIG_HOTPLUG
78 
pcibios_unmap_io_space(struct pci_bus * bus)79 int pcibios_unmap_io_space(struct pci_bus *bus)
80 {
81 	struct pci_controller *hose;
82 
83 	WARN_ON(bus == NULL);
84 
85 	/* If this is not a PHB, we only flush the hash table over
86 	 * the area mapped by this bridge. We don't play with the PTE
87 	 * mappings since we might have to deal with sub-page alignemnts
88 	 * so flushing the hash table is the only sane way to make sure
89 	 * that no hash entries are covering that removed bridge area
90 	 * while still allowing other busses overlapping those pages
91 	 *
92 	 * Note: If we ever support P2P hotplug on Book3E, we'll have
93 	 * to do an appropriate TLB flush here too
94 	 */
95 	if (bus->self) {
96 #ifdef CONFIG_PPC_STD_MMU_64
97 		struct resource *res = bus->resource[0];
98 #endif
99 
100 		pr_debug("IO unmapping for PCI-PCI bridge %s\n",
101 			 pci_name(bus->self));
102 
103 #ifdef CONFIG_PPC_STD_MMU_64
104 		__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
105 					 res->end + _IO_BASE + 1);
106 #endif
107 		return 0;
108 	}
109 
110 	/* Get the host bridge */
111 	hose = pci_bus_to_host(bus);
112 
113 	/* Check if we have IOs allocated */
114 	if (hose->io_base_alloc == 0)
115 		return 0;
116 
117 	pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
118 	pr_debug("  alloc=0x%p\n", hose->io_base_alloc);
119 
120 	/* This is a PHB, we fully unmap the IO area */
121 	vunmap(hose->io_base_alloc);
122 
123 	return 0;
124 }
125 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
126 
127 #endif /* CONFIG_HOTPLUG */
128 
pcibios_map_phb_io_space(struct pci_controller * hose)129 static int __devinit pcibios_map_phb_io_space(struct pci_controller *hose)
130 {
131 	struct vm_struct *area;
132 	unsigned long phys_page;
133 	unsigned long size_page;
134 	unsigned long io_virt_offset;
135 
136 	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
137 	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
138 
139 	/* Make sure IO area address is clear */
140 	hose->io_base_alloc = NULL;
141 
142 	/* If there's no IO to map on that bus, get away too */
143 	if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
144 		return 0;
145 
146 	/* Let's allocate some IO space for that guy. We don't pass
147 	 * VM_IOREMAP because we don't care about alignment tricks that
148 	 * the core does in that case. Maybe we should due to stupid card
149 	 * with incomplete address decoding but I'd rather not deal with
150 	 * those outside of the reserved 64K legacy region.
151 	 */
152 	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
153 	if (area == NULL)
154 		return -ENOMEM;
155 	hose->io_base_alloc = area->addr;
156 	hose->io_base_virt = (void __iomem *)(area->addr +
157 					      hose->io_base_phys - phys_page);
158 
159 	pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
160 	pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
161 		 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
162 	pr_debug("  size=0x%016llx (alloc=0x%016lx)\n",
163 		 hose->pci_io_size, size_page);
164 
165 	/* Establish the mapping */
166 	if (__ioremap_at(phys_page, area->addr, size_page,
167 			 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
168 		return -ENOMEM;
169 
170 	/* Fixup hose IO resource */
171 	io_virt_offset = pcibios_io_space_offset(hose);
172 	hose->io_resource.start += io_virt_offset;
173 	hose->io_resource.end += io_virt_offset;
174 
175 	pr_debug("  hose->io_resource=%pR\n", &hose->io_resource);
176 
177 	return 0;
178 }
179 
pcibios_map_io_space(struct pci_bus * bus)180 int __devinit pcibios_map_io_space(struct pci_bus *bus)
181 {
182 	WARN_ON(bus == NULL);
183 
184 	/* If this not a PHB, nothing to do, page tables still exist and
185 	 * thus HPTEs will be faulted in when needed
186 	 */
187 	if (bus->self) {
188 		pr_debug("IO mapping for PCI-PCI bridge %s\n",
189 			 pci_name(bus->self));
190 		pr_debug("  virt=0x%016llx...0x%016llx\n",
191 			 bus->resource[0]->start + _IO_BASE,
192 			 bus->resource[0]->end + _IO_BASE);
193 		return 0;
194 	}
195 
196 	return pcibios_map_phb_io_space(pci_bus_to_host(bus));
197 }
198 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
199 
pcibios_setup_phb_io_space(struct pci_controller * hose)200 void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
201 {
202 	pcibios_map_phb_io_space(hose);
203 }
204 
205 #define IOBASE_BRIDGE_NUMBER	0
206 #define IOBASE_MEMORY		1
207 #define IOBASE_IO		2
208 #define IOBASE_ISA_IO		3
209 #define IOBASE_ISA_MEM		4
210 
sys_pciconfig_iobase(long which,unsigned long in_bus,unsigned long in_devfn)211 long sys_pciconfig_iobase(long which, unsigned long in_bus,
212 			  unsigned long in_devfn)
213 {
214 	struct pci_controller* hose;
215 	struct list_head *ln;
216 	struct pci_bus *bus = NULL;
217 	struct device_node *hose_node;
218 
219 	/* Argh ! Please forgive me for that hack, but that's the
220 	 * simplest way to get existing XFree to not lockup on some
221 	 * G5 machines... So when something asks for bus 0 io base
222 	 * (bus 0 is HT root), we return the AGP one instead.
223 	 */
224 	if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
225 		struct device_node *agp;
226 
227 		agp = of_find_compatible_node(NULL, NULL, "u3-agp");
228 		if (agp)
229 			in_bus = 0xf0;
230 		of_node_put(agp);
231 	}
232 
233 	/* That syscall isn't quite compatible with PCI domains, but it's
234 	 * used on pre-domains setup. We return the first match
235 	 */
236 
237 	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
238 		bus = pci_bus_b(ln);
239 		if (in_bus >= bus->number && in_bus <= bus->subordinate)
240 			break;
241 		bus = NULL;
242 	}
243 	if (bus == NULL || bus->dev.of_node == NULL)
244 		return -ENODEV;
245 
246 	hose_node = bus->dev.of_node;
247 	hose = PCI_DN(hose_node)->phb;
248 
249 	switch (which) {
250 	case IOBASE_BRIDGE_NUMBER:
251 		return (long)hose->first_busno;
252 	case IOBASE_MEMORY:
253 		return (long)hose->pci_mem_offset;
254 	case IOBASE_IO:
255 		return (long)hose->io_base_phys;
256 	case IOBASE_ISA_IO:
257 		return (long)isa_io_base;
258 	case IOBASE_ISA_MEM:
259 		return -EINVAL;
260 	}
261 
262 	return -EOPNOTSUPP;
263 }
264 
265 #ifdef CONFIG_NUMA
pcibus_to_node(struct pci_bus * bus)266 int pcibus_to_node(struct pci_bus *bus)
267 {
268 	struct pci_controller *phb = pci_bus_to_host(bus);
269 	return phb->node;
270 }
271 EXPORT_SYMBOL(pcibus_to_node);
272 #endif
273