1/* 2 * P3041DS Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "fsl/p3041si-pre.dtsi" 36 37/ { 38 model = "fsl,P3041DS"; 39 compatible = "fsl,P3041DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 memory { 45 device_type = "memory"; 46 }; 47 48 dcsr: dcsr@f00000000 { 49 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 50 }; 51 52 soc: soc@ffe000000 { 53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 54 reg = <0xf 0xfe000000 0 0x00001000>; 55 spi@110000 { 56 flash@0 { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 compatible = "spansion,s25sl12801"; 60 reg = <0>; 61 spi-max-frequency = <40000000>; /* input clock */ 62 partition@u-boot { 63 label = "u-boot"; 64 reg = <0x00000000 0x00100000>; 65 read-only; 66 }; 67 partition@kernel { 68 label = "kernel"; 69 reg = <0x00100000 0x00500000>; 70 read-only; 71 }; 72 partition@dtb { 73 label = "dtb"; 74 reg = <0x00600000 0x00100000>; 75 read-only; 76 }; 77 partition@fs { 78 label = "file system"; 79 reg = <0x00700000 0x00900000>; 80 }; 81 }; 82 }; 83 84 i2c@118100 { 85 eeprom@51 { 86 compatible = "at24,24c256"; 87 reg = <0x51>; 88 }; 89 eeprom@52 { 90 compatible = "at24,24c256"; 91 reg = <0x52>; 92 }; 93 }; 94 95 i2c@119100 { 96 rtc@68 { 97 compatible = "dallas,ds3232"; 98 reg = <0x68>; 99 interrupts = <0x1 0x1 0 0>; 100 }; 101 }; 102 }; 103 104 rio: rapidio@ffe0c0000 { 105 reg = <0xf 0xfe0c0000 0 0x11000>; 106 107 port1 { 108 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 109 }; 110 port2 { 111 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 112 }; 113 }; 114 115 lbc: localbus@ffe124000 { 116 reg = <0xf 0xfe124000 0 0x1000>; 117 ranges = <0 0 0xf 0xe8000000 0x08000000 118 2 0 0xf 0xffa00000 0x00040000 119 3 0 0xf 0xffdf0000 0x00008000>; 120 121 flash@0,0 { 122 compatible = "cfi-flash"; 123 reg = <0 0 0x08000000>; 124 bank-width = <2>; 125 device-width = <2>; 126 }; 127 128 nand@2,0 { 129 #address-cells = <1>; 130 #size-cells = <1>; 131 compatible = "fsl,elbc-fcm-nand"; 132 reg = <0x2 0x0 0x40000>; 133 134 partition@0 { 135 label = "NAND U-Boot Image"; 136 reg = <0x0 0x02000000>; 137 read-only; 138 }; 139 140 partition@2000000 { 141 label = "NAND Root File System"; 142 reg = <0x02000000 0x10000000>; 143 }; 144 145 partition@12000000 { 146 label = "NAND Compressed RFS Image"; 147 reg = <0x12000000 0x08000000>; 148 }; 149 150 partition@1a000000 { 151 label = "NAND Linux Kernel Image"; 152 reg = <0x1a000000 0x04000000>; 153 }; 154 155 partition@1e000000 { 156 label = "NAND DTB Image"; 157 reg = <0x1e000000 0x01000000>; 158 }; 159 160 partition@1f000000 { 161 label = "NAND Writable User area"; 162 reg = <0x1f000000 0x21000000>; 163 }; 164 }; 165 166 board-control@3,0 { 167 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; 168 reg = <3 0 0x30>; 169 }; 170 }; 171 172 pci0: pcie@ffe200000 { 173 reg = <0xf 0xfe200000 0 0x1000>; 174 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 175 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 176 pcie@0 { 177 ranges = <0x02000000 0 0xe0000000 178 0x02000000 0 0xe0000000 179 0 0x20000000 180 181 0x01000000 0 0x00000000 182 0x01000000 0 0x00000000 183 0 0x00010000>; 184 }; 185 }; 186 187 pci1: pcie@ffe201000 { 188 reg = <0xf 0xfe201000 0 0x1000>; 189 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 190 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 191 pcie@0 { 192 ranges = <0x02000000 0 0xe0000000 193 0x02000000 0 0xe0000000 194 0 0x20000000 195 196 0x01000000 0 0x00000000 197 0x01000000 0 0x00000000 198 0 0x00010000>; 199 }; 200 }; 201 202 pci2: pcie@ffe202000 { 203 reg = <0xf 0xfe202000 0 0x1000>; 204 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 205 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 206 pcie@0 { 207 ranges = <0x02000000 0 0xe0000000 208 0x02000000 0 0xe0000000 209 0 0x20000000 210 211 0x01000000 0 0x00000000 212 0x01000000 0 0x00000000 213 0 0x00010000>; 214 }; 215 }; 216 217 pci3: pcie@ffe203000 { 218 reg = <0xf 0xfe203000 0 0x1000>; 219 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 220 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 221 pcie@0 { 222 ranges = <0x02000000 0 0xe0000000 223 0x02000000 0 0xe0000000 224 0 0x20000000 225 226 0x01000000 0 0x00000000 227 0x01000000 0 0x00000000 228 0 0x00010000>; 229 }; 230 }; 231}; 232 233/include/ "fsl/p3041si-post.dtsi" 234