1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2008 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_FPA_DEFS_H__
29 #define __CVMX_FPA_DEFS_H__
30 
31 #define CVMX_FPA_BIST_STATUS \
32 	 CVMX_ADD_IO_SEG(0x00011800280000E8ull)
33 #define CVMX_FPA_CTL_STATUS \
34 	 CVMX_ADD_IO_SEG(0x0001180028000050ull)
35 #define CVMX_FPA_FPF0_MARKS \
36 	 CVMX_ADD_IO_SEG(0x0001180028000000ull)
37 #define CVMX_FPA_FPF0_SIZE \
38 	 CVMX_ADD_IO_SEG(0x0001180028000058ull)
39 #define CVMX_FPA_FPF1_MARKS \
40 	 CVMX_ADD_IO_SEG(0x0001180028000008ull)
41 #define CVMX_FPA_FPF2_MARKS \
42 	 CVMX_ADD_IO_SEG(0x0001180028000010ull)
43 #define CVMX_FPA_FPF3_MARKS \
44 	 CVMX_ADD_IO_SEG(0x0001180028000018ull)
45 #define CVMX_FPA_FPF4_MARKS \
46 	 CVMX_ADD_IO_SEG(0x0001180028000020ull)
47 #define CVMX_FPA_FPF5_MARKS \
48 	 CVMX_ADD_IO_SEG(0x0001180028000028ull)
49 #define CVMX_FPA_FPF6_MARKS \
50 	 CVMX_ADD_IO_SEG(0x0001180028000030ull)
51 #define CVMX_FPA_FPF7_MARKS \
52 	 CVMX_ADD_IO_SEG(0x0001180028000038ull)
53 #define CVMX_FPA_FPFX_MARKS(offset) \
54 	 CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1)
55 #define CVMX_FPA_FPFX_SIZE(offset) \
56 	 CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1)
57 #define CVMX_FPA_INT_ENB \
58 	 CVMX_ADD_IO_SEG(0x0001180028000048ull)
59 #define CVMX_FPA_INT_SUM \
60 	 CVMX_ADD_IO_SEG(0x0001180028000040ull)
61 #define CVMX_FPA_QUE0_PAGE_INDEX \
62 	 CVMX_ADD_IO_SEG(0x00011800280000F0ull)
63 #define CVMX_FPA_QUE1_PAGE_INDEX \
64 	 CVMX_ADD_IO_SEG(0x00011800280000F8ull)
65 #define CVMX_FPA_QUE2_PAGE_INDEX \
66 	 CVMX_ADD_IO_SEG(0x0001180028000100ull)
67 #define CVMX_FPA_QUE3_PAGE_INDEX \
68 	 CVMX_ADD_IO_SEG(0x0001180028000108ull)
69 #define CVMX_FPA_QUE4_PAGE_INDEX \
70 	 CVMX_ADD_IO_SEG(0x0001180028000110ull)
71 #define CVMX_FPA_QUE5_PAGE_INDEX \
72 	 CVMX_ADD_IO_SEG(0x0001180028000118ull)
73 #define CVMX_FPA_QUE6_PAGE_INDEX \
74 	 CVMX_ADD_IO_SEG(0x0001180028000120ull)
75 #define CVMX_FPA_QUE7_PAGE_INDEX \
76 	 CVMX_ADD_IO_SEG(0x0001180028000128ull)
77 #define CVMX_FPA_QUEX_AVAILABLE(offset) \
78 	 CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8))
79 #define CVMX_FPA_QUEX_PAGE_INDEX(offset) \
80 	 CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8))
81 #define CVMX_FPA_QUE_ACT \
82 	 CVMX_ADD_IO_SEG(0x0001180028000138ull)
83 #define CVMX_FPA_QUE_EXP \
84 	 CVMX_ADD_IO_SEG(0x0001180028000130ull)
85 #define CVMX_FPA_WART_CTL \
86 	 CVMX_ADD_IO_SEG(0x00011800280000D8ull)
87 #define CVMX_FPA_WART_STATUS \
88 	 CVMX_ADD_IO_SEG(0x00011800280000E0ull)
89 
90 union cvmx_fpa_bist_status {
91 	uint64_t u64;
92 	struct cvmx_fpa_bist_status_s {
93 		uint64_t reserved_5_63:59;
94 		uint64_t frd:1;
95 		uint64_t fpf0:1;
96 		uint64_t fpf1:1;
97 		uint64_t ffr:1;
98 		uint64_t fdr:1;
99 	} s;
100 	struct cvmx_fpa_bist_status_s cn30xx;
101 	struct cvmx_fpa_bist_status_s cn31xx;
102 	struct cvmx_fpa_bist_status_s cn38xx;
103 	struct cvmx_fpa_bist_status_s cn38xxp2;
104 	struct cvmx_fpa_bist_status_s cn50xx;
105 	struct cvmx_fpa_bist_status_s cn52xx;
106 	struct cvmx_fpa_bist_status_s cn52xxp1;
107 	struct cvmx_fpa_bist_status_s cn56xx;
108 	struct cvmx_fpa_bist_status_s cn56xxp1;
109 	struct cvmx_fpa_bist_status_s cn58xx;
110 	struct cvmx_fpa_bist_status_s cn58xxp1;
111 };
112 
113 union cvmx_fpa_ctl_status {
114 	uint64_t u64;
115 	struct cvmx_fpa_ctl_status_s {
116 		uint64_t reserved_18_63:46;
117 		uint64_t reset:1;
118 		uint64_t use_ldt:1;
119 		uint64_t use_stt:1;
120 		uint64_t enb:1;
121 		uint64_t mem1_err:7;
122 		uint64_t mem0_err:7;
123 	} s;
124 	struct cvmx_fpa_ctl_status_s cn30xx;
125 	struct cvmx_fpa_ctl_status_s cn31xx;
126 	struct cvmx_fpa_ctl_status_s cn38xx;
127 	struct cvmx_fpa_ctl_status_s cn38xxp2;
128 	struct cvmx_fpa_ctl_status_s cn50xx;
129 	struct cvmx_fpa_ctl_status_s cn52xx;
130 	struct cvmx_fpa_ctl_status_s cn52xxp1;
131 	struct cvmx_fpa_ctl_status_s cn56xx;
132 	struct cvmx_fpa_ctl_status_s cn56xxp1;
133 	struct cvmx_fpa_ctl_status_s cn58xx;
134 	struct cvmx_fpa_ctl_status_s cn58xxp1;
135 };
136 
137 union cvmx_fpa_fpfx_marks {
138 	uint64_t u64;
139 	struct cvmx_fpa_fpfx_marks_s {
140 		uint64_t reserved_22_63:42;
141 		uint64_t fpf_wr:11;
142 		uint64_t fpf_rd:11;
143 	} s;
144 	struct cvmx_fpa_fpfx_marks_s cn38xx;
145 	struct cvmx_fpa_fpfx_marks_s cn38xxp2;
146 	struct cvmx_fpa_fpfx_marks_s cn56xx;
147 	struct cvmx_fpa_fpfx_marks_s cn56xxp1;
148 	struct cvmx_fpa_fpfx_marks_s cn58xx;
149 	struct cvmx_fpa_fpfx_marks_s cn58xxp1;
150 };
151 
152 union cvmx_fpa_fpfx_size {
153 	uint64_t u64;
154 	struct cvmx_fpa_fpfx_size_s {
155 		uint64_t reserved_11_63:53;
156 		uint64_t fpf_siz:11;
157 	} s;
158 	struct cvmx_fpa_fpfx_size_s cn38xx;
159 	struct cvmx_fpa_fpfx_size_s cn38xxp2;
160 	struct cvmx_fpa_fpfx_size_s cn56xx;
161 	struct cvmx_fpa_fpfx_size_s cn56xxp1;
162 	struct cvmx_fpa_fpfx_size_s cn58xx;
163 	struct cvmx_fpa_fpfx_size_s cn58xxp1;
164 };
165 
166 union cvmx_fpa_fpf0_marks {
167 	uint64_t u64;
168 	struct cvmx_fpa_fpf0_marks_s {
169 		uint64_t reserved_24_63:40;
170 		uint64_t fpf_wr:12;
171 		uint64_t fpf_rd:12;
172 	} s;
173 	struct cvmx_fpa_fpf0_marks_s cn38xx;
174 	struct cvmx_fpa_fpf0_marks_s cn38xxp2;
175 	struct cvmx_fpa_fpf0_marks_s cn56xx;
176 	struct cvmx_fpa_fpf0_marks_s cn56xxp1;
177 	struct cvmx_fpa_fpf0_marks_s cn58xx;
178 	struct cvmx_fpa_fpf0_marks_s cn58xxp1;
179 };
180 
181 union cvmx_fpa_fpf0_size {
182 	uint64_t u64;
183 	struct cvmx_fpa_fpf0_size_s {
184 		uint64_t reserved_12_63:52;
185 		uint64_t fpf_siz:12;
186 	} s;
187 	struct cvmx_fpa_fpf0_size_s cn38xx;
188 	struct cvmx_fpa_fpf0_size_s cn38xxp2;
189 	struct cvmx_fpa_fpf0_size_s cn56xx;
190 	struct cvmx_fpa_fpf0_size_s cn56xxp1;
191 	struct cvmx_fpa_fpf0_size_s cn58xx;
192 	struct cvmx_fpa_fpf0_size_s cn58xxp1;
193 };
194 
195 union cvmx_fpa_int_enb {
196 	uint64_t u64;
197 	struct cvmx_fpa_int_enb_s {
198 		uint64_t reserved_28_63:36;
199 		uint64_t q7_perr:1;
200 		uint64_t q7_coff:1;
201 		uint64_t q7_und:1;
202 		uint64_t q6_perr:1;
203 		uint64_t q6_coff:1;
204 		uint64_t q6_und:1;
205 		uint64_t q5_perr:1;
206 		uint64_t q5_coff:1;
207 		uint64_t q5_und:1;
208 		uint64_t q4_perr:1;
209 		uint64_t q4_coff:1;
210 		uint64_t q4_und:1;
211 		uint64_t q3_perr:1;
212 		uint64_t q3_coff:1;
213 		uint64_t q3_und:1;
214 		uint64_t q2_perr:1;
215 		uint64_t q2_coff:1;
216 		uint64_t q2_und:1;
217 		uint64_t q1_perr:1;
218 		uint64_t q1_coff:1;
219 		uint64_t q1_und:1;
220 		uint64_t q0_perr:1;
221 		uint64_t q0_coff:1;
222 		uint64_t q0_und:1;
223 		uint64_t fed1_dbe:1;
224 		uint64_t fed1_sbe:1;
225 		uint64_t fed0_dbe:1;
226 		uint64_t fed0_sbe:1;
227 	} s;
228 	struct cvmx_fpa_int_enb_s cn30xx;
229 	struct cvmx_fpa_int_enb_s cn31xx;
230 	struct cvmx_fpa_int_enb_s cn38xx;
231 	struct cvmx_fpa_int_enb_s cn38xxp2;
232 	struct cvmx_fpa_int_enb_s cn50xx;
233 	struct cvmx_fpa_int_enb_s cn52xx;
234 	struct cvmx_fpa_int_enb_s cn52xxp1;
235 	struct cvmx_fpa_int_enb_s cn56xx;
236 	struct cvmx_fpa_int_enb_s cn56xxp1;
237 	struct cvmx_fpa_int_enb_s cn58xx;
238 	struct cvmx_fpa_int_enb_s cn58xxp1;
239 };
240 
241 union cvmx_fpa_int_sum {
242 	uint64_t u64;
243 	struct cvmx_fpa_int_sum_s {
244 		uint64_t reserved_28_63:36;
245 		uint64_t q7_perr:1;
246 		uint64_t q7_coff:1;
247 		uint64_t q7_und:1;
248 		uint64_t q6_perr:1;
249 		uint64_t q6_coff:1;
250 		uint64_t q6_und:1;
251 		uint64_t q5_perr:1;
252 		uint64_t q5_coff:1;
253 		uint64_t q5_und:1;
254 		uint64_t q4_perr:1;
255 		uint64_t q4_coff:1;
256 		uint64_t q4_und:1;
257 		uint64_t q3_perr:1;
258 		uint64_t q3_coff:1;
259 		uint64_t q3_und:1;
260 		uint64_t q2_perr:1;
261 		uint64_t q2_coff:1;
262 		uint64_t q2_und:1;
263 		uint64_t q1_perr:1;
264 		uint64_t q1_coff:1;
265 		uint64_t q1_und:1;
266 		uint64_t q0_perr:1;
267 		uint64_t q0_coff:1;
268 		uint64_t q0_und:1;
269 		uint64_t fed1_dbe:1;
270 		uint64_t fed1_sbe:1;
271 		uint64_t fed0_dbe:1;
272 		uint64_t fed0_sbe:1;
273 	} s;
274 	struct cvmx_fpa_int_sum_s cn30xx;
275 	struct cvmx_fpa_int_sum_s cn31xx;
276 	struct cvmx_fpa_int_sum_s cn38xx;
277 	struct cvmx_fpa_int_sum_s cn38xxp2;
278 	struct cvmx_fpa_int_sum_s cn50xx;
279 	struct cvmx_fpa_int_sum_s cn52xx;
280 	struct cvmx_fpa_int_sum_s cn52xxp1;
281 	struct cvmx_fpa_int_sum_s cn56xx;
282 	struct cvmx_fpa_int_sum_s cn56xxp1;
283 	struct cvmx_fpa_int_sum_s cn58xx;
284 	struct cvmx_fpa_int_sum_s cn58xxp1;
285 };
286 
287 union cvmx_fpa_quex_available {
288 	uint64_t u64;
289 	struct cvmx_fpa_quex_available_s {
290 		uint64_t reserved_29_63:35;
291 		uint64_t que_siz:29;
292 	} s;
293 	struct cvmx_fpa_quex_available_s cn30xx;
294 	struct cvmx_fpa_quex_available_s cn31xx;
295 	struct cvmx_fpa_quex_available_s cn38xx;
296 	struct cvmx_fpa_quex_available_s cn38xxp2;
297 	struct cvmx_fpa_quex_available_s cn50xx;
298 	struct cvmx_fpa_quex_available_s cn52xx;
299 	struct cvmx_fpa_quex_available_s cn52xxp1;
300 	struct cvmx_fpa_quex_available_s cn56xx;
301 	struct cvmx_fpa_quex_available_s cn56xxp1;
302 	struct cvmx_fpa_quex_available_s cn58xx;
303 	struct cvmx_fpa_quex_available_s cn58xxp1;
304 };
305 
306 union cvmx_fpa_quex_page_index {
307 	uint64_t u64;
308 	struct cvmx_fpa_quex_page_index_s {
309 		uint64_t reserved_25_63:39;
310 		uint64_t pg_num:25;
311 	} s;
312 	struct cvmx_fpa_quex_page_index_s cn30xx;
313 	struct cvmx_fpa_quex_page_index_s cn31xx;
314 	struct cvmx_fpa_quex_page_index_s cn38xx;
315 	struct cvmx_fpa_quex_page_index_s cn38xxp2;
316 	struct cvmx_fpa_quex_page_index_s cn50xx;
317 	struct cvmx_fpa_quex_page_index_s cn52xx;
318 	struct cvmx_fpa_quex_page_index_s cn52xxp1;
319 	struct cvmx_fpa_quex_page_index_s cn56xx;
320 	struct cvmx_fpa_quex_page_index_s cn56xxp1;
321 	struct cvmx_fpa_quex_page_index_s cn58xx;
322 	struct cvmx_fpa_quex_page_index_s cn58xxp1;
323 };
324 
325 union cvmx_fpa_que_act {
326 	uint64_t u64;
327 	struct cvmx_fpa_que_act_s {
328 		uint64_t reserved_29_63:35;
329 		uint64_t act_que:3;
330 		uint64_t act_indx:26;
331 	} s;
332 	struct cvmx_fpa_que_act_s cn30xx;
333 	struct cvmx_fpa_que_act_s cn31xx;
334 	struct cvmx_fpa_que_act_s cn38xx;
335 	struct cvmx_fpa_que_act_s cn38xxp2;
336 	struct cvmx_fpa_que_act_s cn50xx;
337 	struct cvmx_fpa_que_act_s cn52xx;
338 	struct cvmx_fpa_que_act_s cn52xxp1;
339 	struct cvmx_fpa_que_act_s cn56xx;
340 	struct cvmx_fpa_que_act_s cn56xxp1;
341 	struct cvmx_fpa_que_act_s cn58xx;
342 	struct cvmx_fpa_que_act_s cn58xxp1;
343 };
344 
345 union cvmx_fpa_que_exp {
346 	uint64_t u64;
347 	struct cvmx_fpa_que_exp_s {
348 		uint64_t reserved_29_63:35;
349 		uint64_t exp_que:3;
350 		uint64_t exp_indx:26;
351 	} s;
352 	struct cvmx_fpa_que_exp_s cn30xx;
353 	struct cvmx_fpa_que_exp_s cn31xx;
354 	struct cvmx_fpa_que_exp_s cn38xx;
355 	struct cvmx_fpa_que_exp_s cn38xxp2;
356 	struct cvmx_fpa_que_exp_s cn50xx;
357 	struct cvmx_fpa_que_exp_s cn52xx;
358 	struct cvmx_fpa_que_exp_s cn52xxp1;
359 	struct cvmx_fpa_que_exp_s cn56xx;
360 	struct cvmx_fpa_que_exp_s cn56xxp1;
361 	struct cvmx_fpa_que_exp_s cn58xx;
362 	struct cvmx_fpa_que_exp_s cn58xxp1;
363 };
364 
365 union cvmx_fpa_wart_ctl {
366 	uint64_t u64;
367 	struct cvmx_fpa_wart_ctl_s {
368 		uint64_t reserved_16_63:48;
369 		uint64_t ctl:16;
370 	} s;
371 	struct cvmx_fpa_wart_ctl_s cn30xx;
372 	struct cvmx_fpa_wart_ctl_s cn31xx;
373 	struct cvmx_fpa_wart_ctl_s cn38xx;
374 	struct cvmx_fpa_wart_ctl_s cn38xxp2;
375 	struct cvmx_fpa_wart_ctl_s cn50xx;
376 	struct cvmx_fpa_wart_ctl_s cn52xx;
377 	struct cvmx_fpa_wart_ctl_s cn52xxp1;
378 	struct cvmx_fpa_wart_ctl_s cn56xx;
379 	struct cvmx_fpa_wart_ctl_s cn56xxp1;
380 	struct cvmx_fpa_wart_ctl_s cn58xx;
381 	struct cvmx_fpa_wart_ctl_s cn58xxp1;
382 };
383 
384 union cvmx_fpa_wart_status {
385 	uint64_t u64;
386 	struct cvmx_fpa_wart_status_s {
387 		uint64_t reserved_32_63:32;
388 		uint64_t status:32;
389 	} s;
390 	struct cvmx_fpa_wart_status_s cn30xx;
391 	struct cvmx_fpa_wart_status_s cn31xx;
392 	struct cvmx_fpa_wart_status_s cn38xx;
393 	struct cvmx_fpa_wart_status_s cn38xxp2;
394 	struct cvmx_fpa_wart_status_s cn50xx;
395 	struct cvmx_fpa_wart_status_s cn52xx;
396 	struct cvmx_fpa_wart_status_s cn52xxp1;
397 	struct cvmx_fpa_wart_status_s cn56xx;
398 	struct cvmx_fpa_wart_status_s cn56xxp1;
399 	struct cvmx_fpa_wart_status_s cn58xx;
400 	struct cvmx_fpa_wart_status_s cn58xxp1;
401 };
402 
403 #endif
404