1 /*
2  *
3  * BRIEF MODULE DESCRIPTION
4  *   Interrupt specific definitions
5  *
6  * Author: source@mvista.com
7  *
8  *  This program is free software; you can distribute it and/or modify it
9  *  under the terms of the GNU General Public License (Version 2) as
10  *  published by the Free Software Foundation.
11  *
12  *  This program is distributed in the hope it will be useful, but WITHOUT
13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15  *  for more details.
16  *
17  *  You should have received a copy of the GNU General Public License along
18  *  with this program; if not, write to the Free Software Foundation, Inc.,
19  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20  */
21 
22 #ifndef __PNX8550_INT_H
23 #define __PNX8550_INT_H
24 
25 #define PNX8550_GIC_BASE	0xBBE3E000
26 
27 #define PNX8550_GIC_PRIMASK_0	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
28 #define PNX8550_GIC_PRIMASK_1	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
29 #define PNX8550_GIC_VECTOR_0	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
30 #define PNX8550_GIC_VECTOR_1	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
31 #define PNX8550_GIC_PEND_1_31	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
32 #define PNX8550_GIC_PEND_32_63	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
33 #define PNX8550_GIC_PEND_64_70	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
34 #define PNX8550_GIC_FEATURES	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
35 #define PNX8550_GIC_REQ(x)	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
36 #define PNX8550_GIC_MOD_ID	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
37 
38 // cp0 is two software + six hw exceptions
39 #define PNX8550_INT_CP0_TOTINT	8
40 #define PNX8550_INT_CP0_MIN	0
41 #define PNX8550_INT_CP0_MAX	(PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
42 
43 #define MIPS_CPU_GIC_IRQ        2
44 #define MIPS_CPU_TIMER_IRQ      7
45 
46 // GIC are 71 exceptions connected to cp0's first hardware exception
47 #define PNX8550_INT_GIC_TOTINT	71
48 #define PNX8550_INT_GIC_MIN	(PNX8550_INT_CP0_MAX+1)
49 #define PNX8550_INT_GIC_MAX	(PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
50 
51 #define PNX8550_INT_UNDEF              (PNX8550_INT_GIC_MIN+0)
52 #define PNX8550_INT_IPC_TARGET0_MIPS   (PNX8550_INT_GIC_MIN+1)
53 #define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
54 #define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
55 #define PNX8550_INT_RESERVED_4         (PNX8550_INT_GIC_MIN+4)
56 #define PNX8550_INT_USB                (PNX8550_INT_GIC_MIN+5)
57 #define PNX8550_INT_GPIO_EQ1           (PNX8550_INT_GIC_MIN+6)
58 #define PNX8550_INT_GPIO_EQ2           (PNX8550_INT_GIC_MIN+7)
59 #define PNX8550_INT_GPIO_EQ3           (PNX8550_INT_GIC_MIN+8)
60 #define PNX8550_INT_GPIO_EQ4           (PNX8550_INT_GIC_MIN+9)
61 
62 #define PNX8550_INT_GPIO_EQ5           (PNX8550_INT_GIC_MIN+10)
63 #define PNX8550_INT_GPIO_EQ6           (PNX8550_INT_GIC_MIN+11)
64 #define PNX8550_INT_RESERVED_12        (PNX8550_INT_GIC_MIN+12)
65 #define PNX8550_INT_QVCP1              (PNX8550_INT_GIC_MIN+13)
66 #define PNX8550_INT_QVCP2              (PNX8550_INT_GIC_MIN+14)
67 #define PNX8550_INT_I2C1               (PNX8550_INT_GIC_MIN+15)
68 #define PNX8550_INT_I2C2               (PNX8550_INT_GIC_MIN+16)
69 #define PNX8550_INT_ISO_UART1          (PNX8550_INT_GIC_MIN+17)
70 #define PNX8550_INT_ISO_UART2          (PNX8550_INT_GIC_MIN+18)
71 #define PNX8550_INT_UART1              (PNX8550_INT_GIC_MIN+19)
72 
73 #define PNX8550_INT_UART2              (PNX8550_INT_GIC_MIN+20)
74 #define PNX8550_INT_QNTR               (PNX8550_INT_GIC_MIN+21)
75 #define PNX8550_INT_RESERVED22         (PNX8550_INT_GIC_MIN+22)
76 #define PNX8550_INT_T_DSC              (PNX8550_INT_GIC_MIN+23)
77 #define PNX8550_INT_M_DSC              (PNX8550_INT_GIC_MIN+24)
78 #define PNX8550_INT_RESERVED25         (PNX8550_INT_GIC_MIN+25)
79 #define PNX8550_INT_2D_DRAW_ENG        (PNX8550_INT_GIC_MIN+26)
80 #define PNX8550_INT_MEM_BASED_SCALAR1  (PNX8550_INT_GIC_MIN+27)
81 #define PNX8550_INT_VIDEO_MPEG         (PNX8550_INT_GIC_MIN+28)
82 #define PNX8550_INT_VIDEO_INPUT_P1     (PNX8550_INT_GIC_MIN+29)
83 
84 #define PNX8550_INT_VIDEO_INPUT_P2     (PNX8550_INT_GIC_MIN+30)
85 #define PNX8550_INT_SPDI1              (PNX8550_INT_GIC_MIN+31)
86 #define PNX8550_INT_SPDO               (PNX8550_INT_GIC_MIN+32)
87 #define PNX8550_INT_AUDIO_INPUT1       (PNX8550_INT_GIC_MIN+33)
88 #define PNX8550_INT_AUDIO_OUTPUT1      (PNX8550_INT_GIC_MIN+34)
89 #define PNX8550_INT_AUDIO_INPUT2       (PNX8550_INT_GIC_MIN+35)
90 #define PNX8550_INT_AUDIO_OUTPUT2      (PNX8550_INT_GIC_MIN+36)
91 #define PNX8550_INT_MEMBASED_SCALAR2   (PNX8550_INT_GIC_MIN+37)
92 #define PNX8550_INT_VPK                (PNX8550_INT_GIC_MIN+38)
93 #define PNX8550_INT_MPEG1_MIPS         (PNX8550_INT_GIC_MIN+39)
94 
95 #define PNX8550_INT_MPEG1_TM           (PNX8550_INT_GIC_MIN+40)
96 #define PNX8550_INT_MPEG2_MIPS         (PNX8550_INT_GIC_MIN+41)
97 #define PNX8550_INT_MPEG2_TM           (PNX8550_INT_GIC_MIN+42)
98 #define PNX8550_INT_TS_DMA             (PNX8550_INT_GIC_MIN+43)
99 #define PNX8550_INT_EDMA               (PNX8550_INT_GIC_MIN+44)
100 #define PNX8550_INT_TM_DEBUG1          (PNX8550_INT_GIC_MIN+45)
101 #define PNX8550_INT_TM_DEBUG2          (PNX8550_INT_GIC_MIN+46)
102 #define PNX8550_INT_PCI_INTA           (PNX8550_INT_GIC_MIN+47)
103 #define PNX8550_INT_CLOCK_MODULE       (PNX8550_INT_GIC_MIN+48)
104 #define PNX8550_INT_PCI_XIO_INTA_PCI   (PNX8550_INT_GIC_MIN+49)
105 
106 #define PNX8550_INT_PCI_XIO_INTB_DMA   (PNX8550_INT_GIC_MIN+50)
107 #define PNX8550_INT_PCI_XIO_INTC_GPPM  (PNX8550_INT_GIC_MIN+51)
108 #define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
109 #define PNX8550_INT_DVD_CSS            (PNX8550_INT_GIC_MIN+53)
110 #define PNX8550_INT_VLD                (PNX8550_INT_GIC_MIN+54)
111 #define PNX8550_INT_GPIO_TSU_7_0       (PNX8550_INT_GIC_MIN+55)
112 #define PNX8550_INT_GPIO_TSU_15_8      (PNX8550_INT_GIC_MIN+56)
113 #define PNX8550_INT_GPIO_CTU_IR        (PNX8550_INT_GIC_MIN+57)
114 #define PNX8550_INT_GPIO0              (PNX8550_INT_GIC_MIN+58)
115 #define PNX8550_INT_GPIO1              (PNX8550_INT_GIC_MIN+59)
116 
117 #define PNX8550_INT_GPIO2              (PNX8550_INT_GIC_MIN+60)
118 #define PNX8550_INT_GPIO3              (PNX8550_INT_GIC_MIN+61)
119 #define PNX8550_INT_GPIO4              (PNX8550_INT_GIC_MIN+62)
120 #define PNX8550_INT_GPIO5              (PNX8550_INT_GIC_MIN+63)
121 #define PNX8550_INT_GPIO6              (PNX8550_INT_GIC_MIN+64)
122 #define PNX8550_INT_GPIO7              (PNX8550_INT_GIC_MIN+65)
123 #define PNX8550_INT_PMAN_SECURITY      (PNX8550_INT_GIC_MIN+66)
124 #define PNX8550_INT_I2C3               (PNX8550_INT_GIC_MIN+67)
125 #define PNX8550_INT_RESERVED_68        (PNX8550_INT_GIC_MIN+68)
126 #define PNX8550_INT_SPDI2              (PNX8550_INT_GIC_MIN+69)
127 
128 #define PNX8550_INT_I2C4               (PNX8550_INT_GIC_MIN+70)
129 
130 // Timer are 3 exceptions connected to cp0's 7th hardware exception
131 #define PNX8550_INT_TIMER_TOTINT       3
132 #define PNX8550_INT_TIMER_MIN	       (PNX8550_INT_GIC_MAX+1)
133 #define PNX8550_INT_TIMER_MAX          (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
134 
135 #define PNX8550_INT_TIMER1             (PNX8550_INT_TIMER_MIN+0)
136 #define PNX8550_INT_TIMER2             (PNX8550_INT_TIMER_MIN+1)
137 #define PNX8550_INT_TIMER3             (PNX8550_INT_TIMER_MIN+2)
138 #define PNX8550_INT_WATCHDOG           PNX8550_INT_TIMER3
139 
140 #endif
141