1
2/ {
3	#address-cells = <1>;
4	#size-cells = <1>;
5
6	cpus {
7		#address-cells = <1>;
8		#size-cells = <0>;
9
10		cpu@0 {
11			device_type = "cpu";
12			model = "ti,c64x+";
13			reg = <0>;
14		};
15	};
16
17	soc {
18		compatible = "simple-bus";
19		model = "tms320c6457";
20		#address-cells = <1>;
21		#size-cells = <1>;
22		ranges;
23
24		core_pic: interrupt-controller {
25			interrupt-controller;
26			#interrupt-cells = <1>;
27			compatible = "ti,c64x+core-pic";
28		};
29
30		megamod_pic: interrupt-controller@1800000 {
31			compatible = "ti,c64x+megamod-pic";
32			interrupt-controller;
33			#interrupt-cells = <1>;
34			interrupt-parent = <&core_pic>;
35			reg = <0x1800000 0x1000>;
36		};
37
38		cache-controller@1840000 {
39			compatible = "ti,c64x+cache";
40			reg = <0x01840000 0x8400>;
41		};
42
43		device-state-controller@2880800 {
44			compatible = "ti,c64x+dscr";
45			reg = <0x02880800 0x400>;
46
47			ti,dscr-devstat = <0x20>;
48			ti,dscr-silicon-rev = <0x18 28 0xf>;
49			ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
50						 0x118 0 0 1 2>;
51			ti,dscr-kick-regs = <0x38 0x83E70B13
52					     0x3c 0x95A4F1E0>;
53		};
54
55		timer0: timer@2940000 {
56			compatible = "ti,c64x+timer64";
57			reg = <0x2940000 0x40>;
58		};
59
60		clock-controller@29a0000 {
61			compatible = "ti,c6457-pll", "ti,c64x+pll";
62			reg = <0x029a0000 0x200>;
63			ti,c64x+pll-bypass-delay = <300>;
64			ti,c64x+pll-reset-delay = <24000>;
65			ti,c64x+pll-lock-delay = <50000>;
66		};
67	};
68};
69